Re: [PATCH 07/15] v4l: vsp1: Move DRM atomic commit pipeline setup to separate function

Hi Kieran, On Wednesday, 28 March 2018 17:43:13 EEST Kieran Bingham wrote: > On 26/02/18 21:45, Laurent Pinchart wrote: > > The DRM pipeline setup code used at atomic commit time is similar to the > > setup code used when enabling the pipeline. Move it to a separate > > function in order to share

Re: [PATCH 02/15] v4l: vsp1: Remove outdated comment

Hi Kieran, On Wednesday, 28 March 2018 22:04:49 EEST Kieran Bingham wrote: > On 28/03/18 13:27, Kieran Bingham wrote: > > On 26/02/18 21:45, Laurent Pinchart wrote: > >> The entities in the pipeline are all started when the LIF is setup. > >> Remove the outdated comment that state otherwise. > >>

Re: [PATCH 05/15] v4l: vsp1: Use vsp1_entity.pipe to check if entity belongs to a pipeline

Hi Kieran, On Wednesday, 28 March 2018 17:10:10 EEST Kieran Bingham wrote: > On 26/02/18 21:45, Laurent Pinchart wrote: > > The DRM pipeline handling code uses the entity's pipe list head to check > > whether the entity is already included in a pipeline. This method is a > > bit fragile in the

Re: [PATCH v2 5/8] ARM: shmobile: r8a77470: basic SoC support

On Wed, Mar 28, 2018 at 9:26 PM, Biju Das wrote: > Add minimal support for the RZ/G1C (R8A77470) SoC. > > Signed-off-by: Biju Das > Reviewed-by: Fabrizio Castro > --- > V1->V2: > * No change Hence my Reviewed-by:

Re: [PATCH v2 8/8] ARM: multi_v7_defconfig: Enable r8a77470 SoC

On Wed, Mar 28, 2018 at 9:26 PM, Biju Das wrote: > Enable recently added r8a77470 (RZ/G1C) SoC. > > Signed-off-by: Biju Das > Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven

[PATCH v3 4/8] reset: Renesas RZ/N1 reboot driver

The Renesas RZ/N1 Family (Part #R9A06G0xx) needs a small driver to reboot the Cortex-A7 cores. This driver is a sub driver of the sysctrl MFD. Signed-off-by: Michel Pollet --- drivers/power/reset/Kconfig | 7 +++ drivers/power/reset/Makefile | 1 +

[PATCH v3 3/8] DT: arm: renesas,rzn1: add the RZ/N1 SoC and RZN1D-DB board

This documents the RZ/N1 bindings for both the RZ/N1 and the RZN1D-DB board. Signed-off-by: Michel Pollet --- Documentation/devicetree/bindings/arm/shmobile.txt | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git

[PATCH v3 2/8] DT: reset: renesas,rzn1-reboot: document RZ/N1 reboot driver

The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver as part of the sysctrl MFD to handle rebooting the CA7 cores. This documents the driver bindings. Signed-off-by: Michel Pollet --- .../bindings/power/renesas,rzn1-reboot.txt | 20

[PATCH] dmaengine: rcar-dmac: Fix too early/late system suspend/resume callbacks

If serial console wake-up is enabled ("echo enabled > /sys/.../ttySC0/power/wakeup"), and any serial input is received while the system is suspended, serial port input no longer works after system resume. Note that: 1) The system can still be woken up using the serial console, 2) Serial port

[PATCH 2/5] clk: renesas: r8a7745: Fix LB clock divider

The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where the LB clock divider depends on the value of the MD18 pin. On RZ/G1E, the LB clock divider is fixed to 24. Hence model the clock as a fixed factor clock instead. Signed-off-by: Geert Uytterhoeven

[PATCH 1/5] clk: renesas: r8a7743: Fix LB clock divider

The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where the LB clock divider depends on the value of the MD18 pin. On RZ/G1M, the LB clock divider is fixed to 24. Hence model the clock as a fixed factor clock instead. Signed-off-by: Geert Uytterhoeven

[PATCH 5/5] clk: renesas: r8a7794: Fix LB clock divider

The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where the LB clock divider depends on the value of the MD18 pin. On R-Car E2, the LB clock divider is fixed to 24. Hence model the clock as a fixed factor clock instead. Signed-off-by: Geert Uytterhoeven

[PATCH 0/5] clk: renesas: r-car gen2: Fix LB clock divider

Hi all, The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where the LB clock divider depends on the value of the MD18 pin. However, on most RZ/G1 and R-Car Gen2 SoCs, the LB clock divider is fixed to 24. Hence this series corrects the LB clock on affected SoCs by

[PATCH 3/5] clk: renesas: r8a7791/r8a7793: Fix LB clock divider

The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where the LB clock divider depends on the value of the MD18 pin. On R-Car M2-W and M2-N, the LB clock divider is fixed to 24. Hence model the clock as a fixed factor clock instead. Signed-off-by: Geert Uytterhoeven

[PATCH 4/5] clk: renesas: r8a7792: Fix LB clock divider

The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where the LB clock divider depends on the value of the MD18 pin. On R-Car V2H, the LB clock divider is fixed to 24. Hence model the clock as a fixed factor clock instead. Signed-off-by: Geert Uytterhoeven

[PATCH v3 5/8] arm: shmobile: Add the RZ/N1 arch to the shmobile Kconfig

Add the RZ/N1 Family (Part #R9A06G0xx) ARCH config to the rest of the Renesas SoC collection. Signed-off-by: Michel Pollet Reviewed-by: Geert Uytterhoeven --- arch/arm/mach-shmobile/Kconfig | 5 + 1 file changed, 5 insertions(+) diff

RE: [PATCH] gpio: dwapb: Add support for 32 interrupts

Hi, On 28 March 2018 15:23, Phil Edworthy wrote: > The DesignWare GPIO IP can be configured for either 1 or 32 interrupts, > but the driver currently only supports 1 interrupt. See the DesignWare > DW_apb_gpio Databook description of the 'GPIO_INTR_IO' parameter. > > This change allows the

RE: [PATCH 09/12] ARM: shmobile: Document iW-RainboW-G23S single board computer

Hello Simon, thank you for reworking the subject. > Subject: Re: [PATCH 09/12] ARM: shmobile: Document iW-RainboW-G23S single > board computer > > On Wed, Mar 28, 2018 at 09:36:10AM +0200, Geert Uytterhoeven wrote: > > On Tue, Mar 27, 2018 at 4:37 PM, Biju Das wrote: >

[PATCH net-next] dt-bindings: net: renesas-ravb: Add support for r8a77470 SoC

Add a new compatible string for the RZ/G1C (R8A77470) SoC. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro --- Documentation/devicetree/bindings/net/renesas,ravb.txt | 1 + 1 file changed, 1 insertion(+) diff --git

[PATCH v3 0/8] arm: Base support for Renesas RZN1D-DB Board

This series adds the plain basic support for booting a bare kernel on the RZ/N1D-DB Board. It's been trimmed to the strict minimum as a 'base', further patches that will add the rest of the support, pinctrl, clock architecture and quite a few others. Thanks for the comments on the previous

[PATCH v3 7/8] DT: arm: Add Renesas RZN1D-DB Board base file

This adds a base device tree file for the RZN1-DB board, with only the basic support allowing the system to boot to a prompt. Only one UART is used, with only a single CPU running. Signed-off-by: Michel Pollet --- arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts | 26

[PATCH v3 8/8] DT: arm: Add the RZN1D-DB Board to Renesas Makefile target

This adds the newly added board to the Renesas built target Signed-off-by: Michel Pollet Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/Makefile

[PATCH v3 1/8] DT: mfd: renesas,rzn1-sysctrl: document RZ/N1 sysctrl node

The Renesas RZ/N1 Family (Part #R9A06G0xx) has a multi-function system controller. This documents the node used to encapsulate it's sub drivers. Signed-off-by: Michel Pollet --- .../devicetree/bindings/mfd/renesas,rzn1-sysctrl.txt | 19 +++ 1 file

[PATCH v3 6/8] DT: arm: Add Renesas RZ/N1 SoC base device tree file

This adds the Renesas RZ/N1 Family (Part #R9A06G0xx) SoC bare bone support. This currently only handles generic parts (gic, architected timer) and a UART. For simplicity sake, this also relies on the bootloader to set the pinctrl and clocks. Signed-off-by: Michel Pollet

Re: [PATCH v2 4/8] clk: renesas: cpg-mssr: Add r8a77470 support

Hi Biju, On Wed, Mar 28, 2018 at 9:26 PM, Biju Das wrote: > Add RZ/G1C (R8A77470) Clock Pulse Generator / Module Standby and Software > Reset support. > > Signed-off-by: Biju Das > Reviewed-by: Fabrizio Castro >

Re: [PATCH v2 3/8] clk: renesas: Add r8a77470 CPG Core Clock Definitions

Hi Biju, On Wed, Mar 28, 2018 at 9:26 PM, Biju Das wrote: > Add all RZ/G1C Clock Pulse Generator Core Clock Outputs, as listed in > Table 7.2 ("List of Clocks [RZ/G1C]") of the RZ/G1C Hardware User's > Manual. > > Signed-off-by: Biju Das >

Re: [PATCH v6 1/3] dt-bindings: display: bridge: Document THC63LVD1024 LVDS decoder

Hi Vladimir, On Tue, Mar 27, 2018 at 02:03:25PM +0300, Vladimir Zapolskiy wrote: > Hi Jacopo, > > On 03/27/2018 01:10 PM, jacopo mondi wrote: > > Hi Vladimir, > > > > On Tue, Mar 27, 2018 at 12:37:31PM +0300, Vladimir Zapolskiy wrote: > >> Hi Jacopo, > >> > >> On 03/27/2018 11:57 AM, jacopo mondi

[PATCH] dt-bindings: rcar-dmac: Document r8a77470 support

Renesas RZ/G SoC also have the R-Car gen2/3 compatible DMA controllers. Document RZ/G1C (also known as R8A77470) SoC bindings. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro ---

[PATCH] dt-bindings: irqchip: renesas-irqc: Document r8a77470 support

Renesas RZ/G SoC have the R-Car gen2 compatible IRQC interrupt controllers. Document RZ/G1C (also known as R8A77470) SoC bindings. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro ---

RE: [PATCH v3 4/8] reset: Renesas RZ/N1 reboot driver

On 29 March 2018 08:47, I messed up: [snip] > > The Renesas RZ/N1 Family (Part #R9A06G0xx) needs a small driver to reboot > the Cortex-A7 cores. This driver is a sub driver of the sysctrl MFD. > > Signed-off-by: Michel Pollet > --- > drivers/power/reset/Kconfig

[PATCH] ARM: debug-ll: Add support for r8a77470

Enable low-level debugging support for RZ/G1C (r8a77470). RZ/G1C uses SCIF1 for the debug console. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro --- * This patch has runtime depency on

Re: [PATCH 12/15] v4l: vsp1: Generalize detection of entity removal from DRM pipeline

Hi Laurent, Thank you for the patch, On 26/02/18 21:45, Laurent Pinchart wrote: > When disabling a DRM plane, the corresponding RPF is only marked as > removed from the pipeline in the atomic update handler, with the actual > removal happening when configuring the pipeline at atomic commit time.

Re: [PATCH 10/15] v4l: vsp1: Move DRM pipeline output setup code to a function

Hi Laurent, Thank you for another patch :D On 26/02/18 21:45, Laurent Pinchart wrote: > In order to make the vsp1_du_setup_lif() easier to read, and for > symmetry with the DRM pipeline input setup, move the pipeline output > setup code to a separate function. > > Signed-off-by: Laurent

Re: [PATCH v3 6/8] DT: arm: Add Renesas RZ/N1 SoC base device tree file

Hi Michel The subject of all your patches for arch/arm should start with: ARM: dts: A git log on that directory clearly shows that's the preferred one. I would also say that you are missing a symbol definition in arch/arm/mach-shmobile/Kconfig (even if you got rid of any board file) I would

Re: [PATCH v13 2/2] rcar-csi2: add Renesas R-Car MIPI CSI-2 receiver driver

Hi Niklas, On Tue, Feb 13, 2018 at 12:01:32AM +0100, Niklas Söderlund wrote: > + switch (priv->lanes) { > + case 1: > + phycnt = PHYCNT_ENABLECLK | PHYCNT_ENABLE_0; > + break; > + case 2: > + phycnt = PHYCNT_ENABLECLK | PHYCNT_ENABLE_1 |

[PATCH/RFT v2 1/3] thermal: rcar_thermal: add r8a77995 support

Add support for R-Car D3 (r8a77995) thermal sensor. Signed-off-by: Yoshihiro Kaneko --- drivers/thermal/rcar_thermal.c | 148 - 1 file changed, 116 insertions(+), 32 deletions(-) diff --git a/drivers/thermal/rcar_thermal.c

[PATCH/RFT v2 0/3] thermal: add support for r8a77995

This series adds thermal support for r8a77995. R-Car D3 (r8a77995) have a thermal sensor module which is similar to Gen2. Therefore this series adds r8a77995 support to rcar_thermal driver not rcar_gen3_thermal driver. This series is based on the next branch of Zhang Rui's linux tree. v2

[PATCH/RFT v2 3/3] arm64: dts: renesas: r8a77995: add thermal device support

Signed-off-by: Yoshihiro Kaneko --- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 30 ++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index cff42cd..9a52b41

[PATCH/RFT v2 2/3] dt-bindings: thermal: rcar-thermal: add R8A77995 support

Signed-off-by: Yoshihiro Kaneko --- Documentation/devicetree/bindings/thermal/rcar-thermal.txt | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt

Re: [PATCH net-next] dt-bindings: net: renesas-ravb: Add support for r8a77470 SoC

Hello! On 03/29/2018 01:02 PM, Biju Das wrote: > Add a new compatible string for the RZ/G1C (R8A77470) SoC. Needed solely to please checkpatch.pl. :-) > Signed-off-by: Biju Das > Reviewed-by: Fabrizio Castro Acked-by: Sergei