On Mon, Sep 10, 2018 at 03:41:27PM +0100, Fabrizio Castro wrote:
> Add support for the RZ/G2E (R8A774C0) SoC power areas to the
> R-Car SYSC driver.
>
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Biju Das
Thanks,
This looks fine to me but I will wait to see if there are other reviews
On Mon, Sep 10, 2018 at 03:41:28PM +0100, Fabrizio Castro wrote:
> Document bindings for the RZ/G2E (a.k.a. R8A774C0) system
> controller.
>
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Biju Das
Thanks,
This looks fine to me but I will wait to see if there are other reviews
before
On Mon, Sep 10, 2018 at 04:09:41PM +0100, Fabrizio Castro wrote:
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Biju Das
Thanks,
This looks fine to me but I will wait to see if there are other reviews
before applying.
Reviewed-by: Simon Horman
On Mon, Sep 10, 2018 at 04:09:40PM +0100, Fabrizio Castro wrote:
> Document bindings for the RZ/G2E (a.k.a. R8A774C0) reset
> module.
>
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Biju Das
Thanks,
This looks fine to me but I will wait to see if there are other reviews
before applying.
There's no good reason for the sh_cmt_of_table[] initializer to
violate the 80-column limit, especially after the commit 8d50e9476bb4
("clocksource/drivers/sh_cmt: Mark "renesas,cmt-48-gen2" deprecated")
partially fixed it -- fix the R-Car gen2 related entries as well.
Signed-off-by: Sergei
Document support for the R-Car gen3 CMT types 0/1 bindings -- they seem
to be the same CMT types 0/1 as in the R-Car gen2 SoCs.
Also document R8A779{7|8}0 bindings as these are the R-Car gen3 SoCs for
which the initial support was done.
Signed-off-by: Sergei Shtylyov
---
Changes in version 2:
Hello!
Here's the set of 3 patches against the 'tip.git' repo's 'timers/core' branch
plus the CMT driver fixups for the 32/64-bit machines posted recently. We're
adding support for the CMT types0/1 found in the R-Car gen3 SoCs.
[1/3] clocksource: sh_cmt: properly line-wrap sh_cmt_of_table[]
Add support for the R-Car gen3 CMT types 0/1 -- they seem to be the same
CMT types 0/1 as in R-Car gen2 SoCs.
Signed-off-by: Sergei Shtylyov
---
Changes in version 2:
- split the bindings update into a separate patch.
drivers/clocksource/sh_cmt.c |8
1 file changed, 8
On Mon, Sep 10, 2018 at 03:41:26PM +0100, Fabrizio Castro wrote:
> This patch adds power domain indices for RZ/G2E.
>
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Biju Das
Thanks Fabrizio,
This looks fine to me but I will wait to see if there are other reviews
before applying.
Hi Simon,
On Wed, Sep 12, 2018 at 12:25 PM Simon Horman wrote:
> On Thu, Sep 06, 2018 at 12:59:20PM +0300, Laurent Pinchart wrote:
> > On Thursday, 6 September 2018 12:42:32 EEST Simon Horman wrote:
> > > On Thu, Aug 23, 2018 at 11:58:54AM +0200, Geert Uytterhoeven wrote:
> > > > On Sun, Aug 19,
Hi Vinod,
On Wed, Sep 12, 2018 at 11:43 AM Vinod wrote:
> Btw I have sent the series for dma_slave_config direction removal, sh/
> drivers turned to be bit more, can you guys take care of it please?
I'm sorry, I can't seem to find that.
Can you please provide a link to the patch series?
On 12-09-18, 14:05, Geert Uytterhoeven wrote:
> Hi Vinod,
>
> On Wed, Sep 12, 2018 at 11:43 AM Vinod wrote:
> > Btw I have sent the series for dma_slave_config direction removal, sh/
> > drivers turned to be bit more, can you guys take care of it please?
>
> I'm sorry, I can't seem to find
Enable the Renesas RZ/G2E (R8A774C0) SoC in the ARM64 Renesas
defconfig.
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
---
This patch applies on top of renesas-drivers-2018-09-11-v4.19-rc3
arch/arm64/configs/renesas_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git
Hi Simon,
On Wed, Sep 12, 2018 at 11:37 AM Simon Horman wrote:
> On Tue, Sep 11, 2018 at 09:26:27PM +0300, Sergei Shtylyov wrote:
> > On 09/10/2018 05:24 PM, Geert Uytterhoeven wrote:
> > >> Document the R-Car V3{M|H} (R8A779{7|8}0) SoC in the Renesas TMU
> > >> bindings;
> > >> the TMU
Hi Simon,
On Fri, Aug 17, 2018 at 12:53 PM Simon Horman wrote:
> please find the details of the corrected tag below:
>
>
> The following changes since commit 2ae6c0413b4768f9d8fc6f718a732f9dae014b67:
>
> Linux 4.14.61 (2018-08-06 16:20:52 +0200)
>
> are available in the git repository at:
>
>
Dear All,
this patch series adds PFC support to the RZ/G2E (a.k.a. r8a774c0),
and it applies on top of renesas-drivers-2018-09-11-v4.19-rc3.
Thanks,
Fab
Fabrizio Castro (2):
dt-bindings: pinctrl: sh-pfc: Document r8a774c0 PFC support
pinctrl: sh-pfc: r8a77990: Add R8A774C0 PFC support
Document PFC support for the R8A774C0 SoC.
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
---
Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
Renesas RZ/G2E (a.k.a. r8a774c0) is pin compatible with R-Car
E3 (a.k.a. r8a77990), however it doesn't have several automotive
specific peripherals. Add a r8a77990 specific pin groups/functions
along with common pin groups/functions for supporting both r8a77990
and r8a774c0 SoCs.
Signed-off-by:
On Tue, Sep 11, 2018 at 09:35:50PM +0300, Sergei Shtylyov wrote:
> Hello!
>
> On 09/11/2018 04:36 PM, Simon Horman wrote:
>
> Describe TMUs in the R8A779{7|8}0 device trees.
>
> Based on the original (and large) patches by Vladimir Barinov.
>
> Signed-off-by: Vladimir
On Tue, Sep 11, 2018 at 11:12:47AM +0100, Biju Das wrote:
> Add binding documentation for the RZ/G1N (R8A7744) Clock Pulse
> Generator driver.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Simon Horman
On Tue, Sep 11, 2018 at 11:12:48AM +0100, Biju Das wrote:
> Add all RZ/G1N Clock Pulse Generator Core Clock Outputs, as listed in
> Table 7.2b ("List of Clocks [RZ/G1M/N]") of the RZ/G1 Hardware User's
> Manual.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Simon
On Mon, Sep 10, 2018 at 03:09:42PM +0200, Simon Horman wrote:
> On Fri, Sep 07, 2018 at 01:52:28AM +, Kuninori Morimoto wrote:
> >
> > From: Kuninori Morimoto
> >
> > This patch updates license to use SPDX-License-Identifier
> > instead of verbose license text on Renesas related headers.
>
On Tue, Sep 11, 2018 at 11:12:42AM +0100, Biju Das wrote:
> Add binding documentation for the RZ/G1N (R8A7744) SYSC block.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Thanks,
This looks fine to me but I will wait to see if there are other reviews
before applying.
Reviewed-by:
On Thu, Sep 06, 2018 at 02:41:01PM +0200, Geert Uytterhoeven wrote:
> - Device nodes with unit addresses are sorted by unit address,
> - Device nodes without unit addresses and references are sorted
> alphabetically.
>
> Signed-off-by: Geert Uytterhoeven
Thanks, applied for v4.20.
On Mon, Sep 10, 2018 at 11:34:49PM +0300, Sergei Shtylyov wrote:
> On 09/10/2018 11:22 PM, Sergei Shtylyov wrote:
>
> > The driver seems to abuse *unsigned long* not only for the (32-bit)
> > register values but also for the 'sh_cmt_channel::total_cycles' which
> > needs to always be 64-bit -- as
Dear All,
this series adds clock support for the RZ/G2E (a.k.a. r8a774c0),
and applies on top of renesas-devel-20180910-v4.19-rc3.
Thanks,
Fab
Fabrizio Castro (3):
clk: renesas: Add r8a774c0 CPG Core Clock Definitions
clk: renesas: cpg-mssr: Add r8a774c0 support
dt-bindings: clock:
This patch documents RZ/G2E (a.k.a. R8A774C0) bindings for the
Clock Pulse Generator driver.
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
---
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git
Add all RZ/G2E (a.k.a. R8A774C0) Clock Pulse Generator Core
Clock Outputs, as listed in Table 8.2g ("List of Clocks
[RZ/G2E]") of the RZ/G2 Hardware User's Manual.
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
---
include/dt-bindings/clock/r8a774c0-cpg-mssr.h | 60
Add RZ/G2E (R8A774C0) Clock Pulse Generator / Module Standby and
Software Reset support.
Based on Table 8.2g of "RZ/G Series, 2nd Generation User's Manual:
Hardware (Rev. 0.61, June 12, 2018)".
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
---
drivers/clk/renesas/Kconfig |
On Tue, Sep 11, 2018 at 11:30:04AM +0100, Biju Das wrote:
> Document PFC support for the RZ/G1N (R8A7744) SoC.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Simon Horman
On Tue, Sep 11, 2018 at 11:30:05AM +0100, Biju Das wrote:
> Renesas RZ/G1N (R8A7744) is pin compatible with R-Car M2-W/N (R8A7791/3)
> and RZ/G1M.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Simon Horman
On Tue, Sep 11, 2018 at 09:26:27PM +0300, Sergei Shtylyov wrote:
> On 09/10/2018 05:24 PM, Geert Uytterhoeven wrote:
>
> >> Document the R-Car V3{M|H} (R8A779{7|8}0) SoC in the Renesas TMU bindings;
> >> the TMU hardware in those is the Renesas standard 3-channel timer unit.
> >>
> >>
On 11-09-18, 10:17, Geert Uytterhoeven wrote:
> Hi Vinod,
>
> On Tue, Sep 11, 2018 at 9:48 AM Vinod wrote:
> > On 07-09-18, 01:58, Kuninori Morimoto wrote:
> > > From: Kuninori Morimoto
> > >
> > > This patch updates license to use SPDX-License-Identifier
> > > instead of verbose license text.
Hi Simon,
On Wed, Sep 12, 2018 at 11:29:51AM +0200, Simon Horman wrote:
> On Mon, Sep 10, 2018 at 05:21:08PM +0300, Laurent Pinchart wrote:
> > Hi Jacopo,
> >
> > Thank you for the patch.
> >
> > On Wednesday, 5 September 2018 18:29:45 EEST Jacopo Mondi wrote:
> > > Add HDMI and CVBS inputs
On Mon, Sep 10, 2018 at 05:02:54PM +0100, Phil Edworthy wrote:
> - UART0 was missing the bus clock ("apb_pclk").
> - Now that the relevant rzn1 bindings have been added, replace the Synopsys
> compat string with the rzn1 strings.
Perhaps: Use recently accepted r9a06g032 and rzn1 compat strings.
On Mon, Sep 10, 2018 at 05:21:08PM +0300, Laurent Pinchart wrote:
> Hi Jacopo,
>
> Thank you for the patch.
>
> On Wednesday, 5 September 2018 18:29:45 EEST Jacopo Mondi wrote:
> > Add HDMI and CVBS inputs device nodes to R-Car E3 Ebisu board.
> >
> > Both HDMI and CVBS inputs are connected to
On Tue, Sep 11, 2018 at 11:12:45AM +0100, Biju Das wrote:
> Document bindings for the RZ/G1N (R8A7744) reset module.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Thanks,
This looks fine to me but I will wait to see if there are other reviews
before applying.
Reviewed-by: Simon
On Tue, Sep 11, 2018 at 11:12:44AM +0100, Biju Das wrote:
> Add support for RZ/G1N (R8A7744) SoC power areas to the R-Car SYSC driver.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Thanks,
This looks fine to me but I will wait to see if there are other reviews
before applying.
On Tue, Sep 11, 2018 at 11:12:43AM +0100, Biju Das wrote:
> Add power domain indices for RZ/G1N (R8A7744) SoC.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Thanks,
This looks fine to me but I will wait to see if there are other reviews
before applying.
Reviewed-by: Simon Horman
On Tue, Sep 11, 2018 at 11:12:49AM +0100, Biju Das wrote:
> Add RZ/G1N (R8A7744) Clock Pulse Generator / Module Standby and Software
> Reset support.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Simon Horman
On Tue, Sep 11, 2018 at 04:37:30PM +0200, Geert Uytterhoeven wrote:
> The thermal device is supposed to be always enabled. As the default
> value of the status property is "okay", there is no need to make this
> explicit in SoC-specific .dtsi files where no override is involved.
>
>
On Tue, Sep 11, 2018 at 03:06:26PM +0200, Wolfram Sang wrote:
> From: Wolfram Sang
>
> Fixes: 26eb2607fa28 ("mmc: renesas_sdhi: add eMMC HS400 mode support")
> Signed-off-by: Wolfram Sang
> ---
>
> So, adding HS400 support broke the detection here. I suggest we discuss
> internally, if this
On Tue, Sep 11, 2018 at 11:12:50AM +0100, Biju Das wrote:
> Add minimal support for the RZ/G1N (R8A7744) SoC.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Simon Horman
On Tue, Sep 11, 2018 at 11:12:51AM +0100, Biju Das wrote:
> Add the compatible strings for supporting the generic cpufreq driver on
> the Renesas RZ/G1N (R8A7744) SoC.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Simon Horman
On Thu, Sep 06, 2018 at 12:59:20PM +0300, Laurent Pinchart wrote:
> Hello,
>
> On Thursday, 6 September 2018 12:42:32 EEST Simon Horman wrote:
> > On Thu, Aug 23, 2018 at 11:58:54AM +0200, Geert Uytterhoeven wrote:
> > > On Sun, Aug 19, 2018 at 9:44 PM Laurent Pinchart wrote:
> > >> The
On Tue, Aug 28, 2018 at 12:56:18PM +0300, Laurent Pinchart wrote:
> Hi Simon,
>
> On Monday, 27 August 2018 15:57:05 EEST Simon Horman wrote:
> > On Fri, Aug 24, 2018 at 11:45:52AM +0300, Laurent Pinchart wrote:
> > > On Friday, 24 August 2018 07:52:28 EEST Nguyen An Hoan wrote:
> > > > From:
46 matches
Mail list logo