Fix warning when running with CONFIG_DMA_API_DEBUG_SG=y by allocating a
device_dma_parameters structure and filling in the max segment size.
Signed-off-by: Wolfram Sang
---
Change since RFC: use better value, confirmed with Geert (thanks!)
drivers/dma/sh/rcar-dmac.c | 3 +++
1 file changed, 3
On 12/09/2018 22:10, Sergei Shtylyov wrote:
> Hello!
>
> Here's the set of 3 patches against the 'tip.git' repo's 'timers/core' branch
> plus the CMT driver fixups for the 32/64-bit machines posted recently. We're
> adding support for the CMT types0/1 found in the R-Car gen3 SoCs.
>
> [1/3]
On 10/09/2018 22:22, Sergei Shtylyov wrote:
> The driver seems to abuse *unsigned long* not only for the (32-bit)
> register values but also for the 'sh_cmt_channel::total_cycles' which
> needs to always be 64-bit -- as a result, the clocksource's mask is
> needlessly clamped down to 32-bits on
On 08/09/2018 22:54, Sergei Shtylyov wrote:
> When trying to use CMT for clockevents on R-Car gen3 SoCs, I noticed
> that 'max_delta_ns' for the broadcast timer (CMT) was shown as 1000 in
> /proc/timer_list. It turned out that when calculating it, the driver did
> 1 << 32 (causing what I think was
Update the comment because we don't set the pointer to NULL anymore.
Also use the correct pointer name 'dma_ops' instead of 'dma_map_ops'.
Fixes: 1874619a7df4 ("ARM: dma-mapping: Set proper DMA ops in
arm_iommu_detach_device()")
Signed-off-by: Wolfram Sang
Reviewed-by: Geert Uytterhoeven
---
On 09/11/2018 09:26 PM, Sergei Shtylyov wrote:
>>> Document the R-Car V3{M|H} (R8A779{7|8}0) SoC in the Renesas TMU bindings;
>>> the TMU hardware in those is the Renesas standard 3-channel timer unit.
>>>
>>> Signed-off-by: Sergei Shtylyov
>>
>> Thanks for your patch!
>>
>> Not all channels
On 09/12/2018 03:23 PM, Geert Uytterhoeven wrote:
> Document the R-Car V3{M|H} (R8A779{7|8}0) SoC in the Renesas TMU bindings;
> the TMU hardware in those is the Renesas standard 3-channel timer unit.
>
> Signed-off-by: Sergei Shtylyov
Thanks for your patch!
Hi Geert,
Please consider including this release in renesas-drivers.
Please note - unlike the previous VSP1 pull request, which is a direct request
of Laurent's v4l2/vsp1/next, this one is actually a branch on my tree.
This pull request covers both Laurent's drm/du/next and one extra commit in
Hi Geert,
On 14/09/18 21:50, Kieran Bingham wrote:
> Hi Geert,
>
> Please consider including this release in renesas-drivers.
>
> --
> Regards
>
> Kieran
>
> The following changes since commit 78cf8c842c111df656c63b5d04997ea4e40ef26a:
>
> media: drxj: fix spelling mistake in fall-through
Hi Geert,
Please consider including this release in renesas-drivers.
--
Regards
Kieran
The following changes since commit 78cf8c842c111df656c63b5d04997ea4e40ef26a:
media: drxj: fix spelling mistake in fall-through annotations (2018-09-12
11:21:52 -0400)
are available in the Git repository
On Tue, Sep 11, 2018 at 2:04 PM Geert Uytterhoeven wrote:
> On Sun, Jul 29, 2018 at 11:33 PM Linus Walleij
> wrote:> > On Wed, Jul 25, 2018 at 10:20 PM Wolfram Sang
> wrote:
> > > > That all being said, I think this patch is still useful as is.
> > >
> > > Linus, do you have time to comment
> > Any plans to apply it? drivers/gpio/gpiolib.c is your territory, I believe
> > ;-)
>
> Ooops sorry.
>
> Patch applied.
Thanks Geert & Linus!
signature.asc
Description: PGP signature
On Tue, Sep 11, 2018 at 12:19 PM Biju Das wrote:
> Add binding documentation for the RZ/G1N (R8A7744) SYSC block.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's
On Tue, Sep 11, 2018 at 12:19 PM Biju Das wrote:
> Add power domain indices for RZ/G1N (R8A7744) SoC.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux
On Tue, Sep 11, 2018 at 12:19 PM Biju Das wrote:
> Add support for RZ/G1N (R8A7744) SoC power areas to the R-Car SYSC driver.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven
On Tue, Sep 11, 2018 at 12:19 PM Biju Das wrote:
> Document bindings for the RZ/G1N (R8A7744) reset module.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of
On Tue, Sep 11, 2018 at 12:19 PM Biju Das wrote:
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal
On Tue, Sep 11, 2018 at 12:19 PM Biju Das wrote:
> Add minimal support for the RZ/G1N (R8A7744) SoC.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux
On Tue, Sep 11, 2018 at 12:20 PM Biju Das wrote:
> Add the compatible strings for supporting the generic cpufreq driver on
> the Renesas RZ/G1N (R8A7744) SoC.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
On Tue, Sep 11, 2018 at 12:19 PM Biju Das wrote:
> Add binding documentation for the RZ/G1N (R8A7744) Clock Pulse
> Generator driver.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
i.e. will queue in clk-renesas-for-v4.20.
Gr{oetje,eeting}s,
On Tue, Sep 11, 2018 at 12:19 PM Biju Das wrote:
> Add all RZ/G1N Clock Pulse Generator Core Clock Outputs, as listed in
> Table 7.2b ("List of Clocks [RZ/G1M/N]") of the RZ/G1 Hardware User's
> Manual.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
On Tue, Sep 11, 2018 at 12:36 PM Biju Das wrote:
> Document PFC support for the RZ/G1N (R8A7744) SoC.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
i.e. will queue in sh-pfc-for-v4.20.
Gr{oetje,eeting}s,
Geert
--
Geert
Hi Laurent,
On 14/09/18 12:11, Laurent Pinchart wrote:
> Hi Kieran,
>
> Thank you for the patch.
>
> How about renaming the subject line to "Add support for missing pixel
> formats"
> ?
>
Ack.
> On Friday, 31 August 2018 21:12:58 EEST Kieran Bingham wrote:
>> From: Koji Matsuoka
>>
>>
On Tue, Sep 11, 2018 at 12:19 PM Biju Das wrote:
> Add RZ/G1N (R8A7744) Clock Pulse Generator / Module Standby and Software
> Reset support.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
i.e. will queue in clk-renesas-for-v4.20.
Gr{oetje,eeting}s,
On Tue, Sep 11, 2018 at 12:36 PM Biju Das wrote:
> Renesas RZ/G1N (R8A7744) is pin compatible with R-Car M2-W/N (R8A7791/3)
> and RZ/G1M.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
i.e. will queue in sh-pfc-for-v4.20.
Gr{oetje,eeting}s,
On Wed, Sep 12, 2018 at 3:31 PM Fabrizio Castro
wrote:
> Document PFC support for the R8A774C0 SoC.
>
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Biju Das
Reviewed-by: Geert Uytterhoeven
i.e. will queue in sh-pfc-for-v4.20.
Gr{oetje,eeting}s,
Geert
--
Geert
Hi Chris,
On Thu, Sep 13, 2018 at 4:54 PM Chris Brandt wrote:
> On Thursday, September 13, 2018, Geert Uytterhoeven wrote:
> > > > I wonder they just didn't make a clock_initcall() and timer_initcall()
> > > > instead.
> > >
> > > What happens if you place the clk_init() before board_time_init()
On Sat, Sep 8, 2018 at 10:54 PM Sergei Shtylyov
wrote:
> When trying to use CMT for clockevents on R-Car gen3 SoCs, I noticed
> that 'max_delta_ns' for the broadcast timer (CMT) was shown as 1000 in
> /proc/timer_list. It turned out that when calculating it, the driver did
> 1 << 32 (causing what
On Mon, Sep 10, 2018 at 10:23 PM Sergei Shtylyov
wrote:
> The driver seems to abuse *unsigned long* not only for the (32-bit)
> register values but also for the 'sh_cmt_channel::total_cycles' which
> needs to always be 64-bit -- as a result, the clocksource's mask is
> needlessly clamped down to
On Wed, Sep 12, 2018 at 10:17 PM Sergei Shtylyov
wrote:
> Add support for the R-Car gen3 CMT types 0/1 -- they seem to be the same
> CMT types 0/1 as in R-Car gen2 SoCs.
>
> Signed-off-by: Sergei Shtylyov
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
On Wed, Sep 12, 2018 at 10:16 PM Sergei Shtylyov
wrote:
> Document support for the R-Car gen3 CMT types 0/1 bindings -- they seem
> to be the same CMT types 0/1 as in the R-Car gen2 SoCs.
>
> Also document R8A779{7|8}0 bindings as these are the R-Car gen3 SoCs for
> which the initial support was
Hi Wolfram,
On Thu, Sep 13, 2018 at 4:53 PM Wolfram Sang
wrote:
> Fix warning when running with CONFIG_DMA_API_DEBUG_SG=y by allocating a
> device_dma_parameters structure and filling in the max segment size.
>
> Signed-off-by: Wolfram Sang
> ---
>
> According to this discussion [1], this is
On Mon, 2018-09-10 at 16:09 +0100, Fabrizio Castro wrote:
> Document bindings for the RZ/G2E (a.k.a. R8A774C0) reset
> module.
>
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Biju Das
> ---
> Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 +
> 1 file changed, 1 insertion(+)
>
>
On Fri, Sep 7, 2018 at 5:02 AM Kuninori Morimoto
wrote:
> From: Kuninori Morimoto
>
> This patch updates license to use SPDX-License-Identifier
> instead of verbose license text on Renesas related headers.
>
> Signed-off-by: Kuninori Morimoto
Reviewed-by: Geert Uytterhoeven
i.e. will queue in
On Wed, Sep 12, 2018 at 10:42:20AM +0200, Simon Horman wrote:
> On Mon, Sep 10, 2018 at 03:41:26PM +0100, Fabrizio Castro wrote:
> > This patch adds power domain indices for RZ/G2E.
> >
> > Signed-off-by: Fabrizio Castro
> > Reviewed-by: Biju Das
>
> Thanks Fabrizio,
>
> This looks fine to me
On Wed, Sep 12, 2018 at 10:58:41AM +0200, Simon Horman wrote:
> On Mon, Sep 10, 2018 at 03:41:27PM +0100, Fabrizio Castro wrote:
> > Add support for the RZ/G2E (R8A774C0) SoC power areas to the
> > R-Car SYSC driver.
> >
> > Signed-off-by: Fabrizio Castro
> > Reviewed-by: Biju Das
>
> Thanks,
On Wed, Sep 12, 2018 at 10:59:14AM +0200, Simon Horman wrote:
> On Mon, Sep 10, 2018 at 03:41:28PM +0100, Fabrizio Castro wrote:
> > Document bindings for the RZ/G2E (a.k.a. R8A774C0) system
> > controller.
> >
> > Signed-off-by: Fabrizio Castro
> > Reviewed-by: Biju Das
>
> Thanks,
>
> This
On Wed, Sep 12, 2018 at 11:20:39AM +0200, Simon Horman wrote:
> On Mon, Sep 10, 2018 at 05:02:54PM +0100, Phil Edworthy wrote:
> > - UART0 was missing the bus clock ("apb_pclk").
> > - Now that the relevant rzn1 bindings have been added, replace the Synopsys
> > compat string with the rzn1
Hi Geert,
> > + dmac->dev->dma_parms = >parms;
> > + dma_set_max_seg_size(dmac->dev, 0x0100);
>
> That is one too much, cfr.
>
> drivers/dma/sh/rcar-dmac.c:#define RCAR_DMATCR_MASK 0x00ff
I see. Will fix and send an updated patch. Nice to see that I was not
On Wed, Sep 12, 2018 at 11:34:56AM +0200, Simon Horman wrote:
> On Tue, Sep 11, 2018 at 04:37:30PM +0200, Geert Uytterhoeven wrote:
> > The thermal device is supposed to be always enabled. As the default
> > value of the status property is "okay", there is no need to make this
> > explicit in
On Wed, Sep 12, 2018 at 11:41:52AM +0100, Fabrizio Castro wrote:
> Add all RZ/G2E (a.k.a. R8A774C0) Clock Pulse Generator Core
> Clock Outputs, as listed in Table 8.2g ("List of Clocks
> [RZ/G2E]") of the RZ/G2 Hardware User's Manual.
>
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Biju Das
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