Re: [PATCH 02/15] clk: renesas: cpg-msr: Add support for R-Car M3-N
On Tue, Feb 13, 2018 at 10:45:49AM +0100, Jacopo Mondi wrote: > Initial support for R-Car M3-N (r8a77965), including core and module > clocks. > > Signed-off-by: Jacopo Mondi > --- > .../devicetree/bindings/clock/renesas,cpg-mssr.txt | 1 + > drivers/clk/renesas/Kconfig| 5 + > drivers/clk/renesas/Makefile | 1 + > drivers/clk/renesas/r8a77965-cpg-mssr.c| 333 > + > drivers/clk/renesas/renesas-cpg-mssr.c | 6 + > drivers/clk/renesas/renesas-cpg-mssr.h | 1 + > include/dt-bindings/clock/r8a77965-cpg-mssr.h | 62 > 7 files changed, 409 insertions(+) > create mode 100644 drivers/clk/renesas/r8a77965-cpg-mssr.c > create mode 100644 include/dt-bindings/clock/r8a77965-cpg-mssr.h For the DT bits: Reviewed-by: Rob Herring
Re: [PATCH 02/15] clk: renesas: cpg-msr: Add support for R-Car M3-N
Hi Simon, On Thu, Feb 15, 2018 at 4:31 PM, Simon Horman wrote: > On Tue, Feb 13, 2018 at 10:45:49AM +0100, Jacopo Mondi wrote: >> Initial support for R-Car M3-N (r8a77965), including core and module >> clocks. >> >> Signed-off-by: Jacopo Mondi >> --- >> .../devicetree/bindings/clock/renesas,cpg-mssr.txt | 1 + >> drivers/clk/renesas/Kconfig| 5 + >> drivers/clk/renesas/Makefile | 1 + >> drivers/clk/renesas/r8a77965-cpg-mssr.c| 333 >> + >> drivers/clk/renesas/renesas-cpg-mssr.c | 6 + >> drivers/clk/renesas/renesas-cpg-mssr.h | 1 + >> include/dt-bindings/clock/r8a77965-cpg-mssr.h | 62 >> 7 files changed, 409 insertions(+) >> create mode 100644 drivers/clk/renesas/r8a77965-cpg-mssr.c >> create mode 100644 include/dt-bindings/clock/r8a77965-cpg-mssr.h >> >> diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt >> b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt >> index f1890d0..246ab63 100644 >> --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt >> +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt >> @@ -22,6 +22,7 @@ Required Properties: >>- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2) >>- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3) >>- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W) >> + - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N) >>- "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M) >>- "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3) >> > > Its up to Geert, but would it be better if the bindings documentation > and driver changes where in separate patches? I don't care that much anymore. It used to be a good idea when the bindings header went in separately, as it was a dependency for both driver and DTS. But now we use hardcoded constants in the first version of the DTS, so it doesn't matter anymore. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Re: [PATCH 02/15] clk: renesas: cpg-msr: Add support for R-Car M3-N
On Tue, Feb 13, 2018 at 10:45:49AM +0100, Jacopo Mondi wrote: > Initial support for R-Car M3-N (r8a77965), including core and module > clocks. > > Signed-off-by: Jacopo Mondi > --- > .../devicetree/bindings/clock/renesas,cpg-mssr.txt | 1 + > drivers/clk/renesas/Kconfig| 5 + > drivers/clk/renesas/Makefile | 1 + > drivers/clk/renesas/r8a77965-cpg-mssr.c| 333 > + > drivers/clk/renesas/renesas-cpg-mssr.c | 6 + > drivers/clk/renesas/renesas-cpg-mssr.h | 1 + > include/dt-bindings/clock/r8a77965-cpg-mssr.h | 62 > 7 files changed, 409 insertions(+) > create mode 100644 drivers/clk/renesas/r8a77965-cpg-mssr.c > create mode 100644 include/dt-bindings/clock/r8a77965-cpg-mssr.h > > diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt > b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt > index f1890d0..246ab63 100644 > --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt > +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt > @@ -22,6 +22,7 @@ Required Properties: >- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2) >- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3) >- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W) > + - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N) >- "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M) >- "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3) > Its up to Geert, but would it be better if the bindings documentation and driver changes where in separate patches? > diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig > index 84b40b9..047d6b5 100644 > --- a/drivers/clk/renesas/Kconfig > +++ b/drivers/clk/renesas/Kconfig > @@ -15,6 +15,7 @@ config CLK_RENESAS > select CLK_R8A7794 if ARCH_R8A7794 > select CLK_R8A7795 if ARCH_R8A7795 > select CLK_R8A7796 if ARCH_R8A7796 > + select CLK_R8A77965 if ARCH_R8A77965 > select CLK_R8A77970 if ARCH_R8A77970 > select CLK_R8A77995 if ARCH_R8A77995 > select CLK_SH73A0 if ARCH_SH73A0 > @@ -97,6 +98,10 @@ config CLK_R8A7796 > bool "R-Car M3-W clock support" if COMPILE_TEST > select CLK_RCAR_GEN3_CPG > > +config CLK_R8A77965 > + bool "R-Car M3-N clock support" if COMPILE_TEST > + select CLK_RCAR_GEN3_CPG > + > config CLK_R8A77970 > bool "R-Car V3M clock support" if COMPILE_TEST > select CLK_RCAR_GEN3_CPG > diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile > index 34c4e0b..2e0982f 100644 > --- a/drivers/clk/renesas/Makefile > +++ b/drivers/clk/renesas/Makefile > @@ -14,6 +14,7 @@ obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o > obj-$(CONFIG_CLK_R8A7794)+= r8a7794-cpg-mssr.o > obj-$(CONFIG_CLK_R8A7795)+= r8a7795-cpg-mssr.o > obj-$(CONFIG_CLK_R8A7796)+= r8a7796-cpg-mssr.o > +obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o > obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o > obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o > obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o > diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c > b/drivers/clk/renesas/r8a77965-cpg-mssr.c > new file mode 100644 > index 000..f29d42c > --- /dev/null > +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c > @@ -0,0 +1,333 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * r8a77965 Clock Pulse Generator / Module Standby and Software Reset > + * > + * Copyright (C) 2018 Jacopo Mondi > + * > + * Based on r8a7795-cpg-mssr.c > + * > + * Copyright (C) 2015 Glider bvba > + * Copyright (C) 2015 Renesas Electronics Corp. > + */ > + > +#include > +#include > +#include > +#include > + > +#include > + > +#include "renesas-cpg-mssr.h" > +#include "rcar-gen3-cpg.h" > + > +enum clk_ids { > + /* Core Clock Outputs exported to DT */ > + LAST_DT_CORE_CLK = R8A77965_CLK_OSC, > + > + /* External Input Clocks */ > + CLK_EXTAL, > + CLK_EXTALR, > + > + /* Internal Core Clocks */ > + CLK_MAIN, > + CLK_PLL0, > + CLK_PLL1, > + CLK_PLL3, > + CLK_PLL4, > + CLK_PLL1_DIV2, > + CLK_PLL1_DIV4, > + CLK_S0, > + CLK_S1, > + CLK_S2, > + CLK_S3, > + CLK_SDSRC, > + CLK_SSPSRC, > + CLK_RINT, > + > + /* Module Clocks */ > + MOD_CLK_BASE > +}; > + > +static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { > + /* External Clock Inputs */ > + DEF_INPUT("extal", CLK_EXTAL), > + DEF_INPUT("extalr", CLK_EXTALR), > + > + /* Internal Core Clocks */ > + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), > + DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), > + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), > + DEF_BASE(".pll3",
Re: [PATCH 02/15] clk: renesas: cpg-msr: Add support for R-Car M3-N
Hi Jacopo, On Tue, Feb 13, 2018 at 10:45 AM, Jacopo Mondi wrote: > Initial support for R-Car M3-N (r8a77965), including core and module > clocks. > > Signed-off-by: Jacopo Mondi Thanks for your patch! Please refer to Table 8.2d of R-Car Series, 3rd Generation User's Manual: Hardware (Rev. 0.80, Oct 31, 2017), so we know which exact version of the datasheet was used for the core clock definitions. > --- /dev/null > +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c > @@ -0,0 +1,333 @@ > +static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { > + DEF_MOD("scif5",202,R8A77965_CLK_S3D4), > + DEF_MOD("scif4",203,R8A77965_CLK_S3D4), > + DEF_MOD("scif3",204,R8A77965_CLK_S3D4), > + DEF_MOD("scif1",206,R8A77965_CLK_S3D4), > + DEF_MOD("scif0",207,R8A77965_CLK_S3D4), > + DEF_MOD("sys-dmac2",217,R8A77965_CLK_S0D3), > + DEF_MOD("sys-dmac1",218,R8A77965_CLK_S0D3), > + DEF_MOD("sys-dmac0",219,R8A77965_CLK_S0D3), > + > + DEF_MOD("cmt3", 300,R8A77965_CLK_R), > + DEF_MOD("cmt2", 301,R8A77965_CLK_R), > + DEF_MOD("cmt1", 302,R8A77965_CLK_R), > + DEF_MOD("cmt0", 303,R8A77965_CLK_R), > + DEF_MOD("scif2",310,R8A77965_CLK_S3D4), > + DEF_MOD("sdif3",311,R8A77965_CLK_SD3), > + DEF_MOD("sdif2",312,R8A77965_CLK_SD2), > + DEF_MOD("sdif1",313,R8A77965_CLK_SD1), > + DEF_MOD("sdif0",314,R8A77965_CLK_SD0), > + DEF_MOD("pcie1",318,R8A77965_CLK_S3D1), > + DEF_MOD("pcie0",319,R8A77965_CLK_S3D1), > + DEF_MOD("usb3-if0", 328,R8A77965_CLK_S3D1), > + DEF_MOD("usb-dmac0",330,R8A77965_CLK_S3D1), > + DEF_MOD("usb-dmac1",331,R8A77965_CLK_S3D1), > + > + DEF_MOD("rwdt", 402,R8A77965_CLK_R), > + DEF_MOD("intc-ex", 407,R8A77965_CLK_CP), > + DEF_MOD("intc-ap", 408,R8A77965_CLK_S3D1), According to Figure 12A.1 the parent clock is S0D3. See also commit 6e7ddf89d67c2b0c ("clk: renesas: r8a7796: Correct parent clock of INTC-AP"). > +static int __init r8a77965_cpg_mssr_init(struct device *dev) > +{ [...] > + > + return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); > +}; Stray semicolon. With the above fixed: Reviewed-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Re: [PATCH 02/15] clk: renesas: cpg-msr: Add support for R-Car M3-N
Hi Jacopo, Thanks for the patch. I haven't really looked at the rest of the patch yet - but the title stands out: [PATCH 02/15] clk: renesas: cpg-msr: Add support for R-Car M3-N Should this be s/cpg-msr/cpg-mssr/ ? -- Regards Kieran On 13/02/18 09:45, Jacopo Mondi wrote: > Initial support for R-Car M3-N (r8a77965), including core and module > clocks. > > Signed-off-by: Jacopo Mondi > --- > .../devicetree/bindings/clock/renesas,cpg-mssr.txt | 1 + > drivers/clk/renesas/Kconfig| 5 + > drivers/clk/renesas/Makefile | 1 + > drivers/clk/renesas/r8a77965-cpg-mssr.c| 333 > + > drivers/clk/renesas/renesas-cpg-mssr.c | 6 + > drivers/clk/renesas/renesas-cpg-mssr.h | 1 + > include/dt-bindings/clock/r8a77965-cpg-mssr.h | 62 > 7 files changed, 409 insertions(+) > create mode 100644 drivers/clk/renesas/r8a77965-cpg-mssr.c > create mode 100644 include/dt-bindings/clock/r8a77965-cpg-mssr.h > > diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt > b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt > index f1890d0..246ab63 100644 > --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt > +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt > @@ -22,6 +22,7 @@ Required Properties: >- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2) >- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3) >- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W) > + - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N) >- "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M) >- "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3) > > diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig > index 84b40b9..047d6b5 100644 > --- a/drivers/clk/renesas/Kconfig > +++ b/drivers/clk/renesas/Kconfig > @@ -15,6 +15,7 @@ config CLK_RENESAS > select CLK_R8A7794 if ARCH_R8A7794 > select CLK_R8A7795 if ARCH_R8A7795 > select CLK_R8A7796 if ARCH_R8A7796 > + select CLK_R8A77965 if ARCH_R8A77965 > select CLK_R8A77970 if ARCH_R8A77970 > select CLK_R8A77995 if ARCH_R8A77995 > select CLK_SH73A0 if ARCH_SH73A0 > @@ -97,6 +98,10 @@ config CLK_R8A7796 > bool "R-Car M3-W clock support" if COMPILE_TEST > select CLK_RCAR_GEN3_CPG > > +config CLK_R8A77965 > + bool "R-Car M3-N clock support" if COMPILE_TEST > + select CLK_RCAR_GEN3_CPG > + > config CLK_R8A77970 > bool "R-Car V3M clock support" if COMPILE_TEST > select CLK_RCAR_GEN3_CPG > diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile > index 34c4e0b..2e0982f 100644 > --- a/drivers/clk/renesas/Makefile > +++ b/drivers/clk/renesas/Makefile > @@ -14,6 +14,7 @@ obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o > obj-$(CONFIG_CLK_R8A7794)+= r8a7794-cpg-mssr.o > obj-$(CONFIG_CLK_R8A7795)+= r8a7795-cpg-mssr.o > obj-$(CONFIG_CLK_R8A7796)+= r8a7796-cpg-mssr.o > +obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o > obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o > obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o > obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o > diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c > b/drivers/clk/renesas/r8a77965-cpg-mssr.c > new file mode 100644 > index 000..f29d42c > --- /dev/null > +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c > @@ -0,0 +1,333 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * r8a77965 Clock Pulse Generator / Module Standby and Software Reset > + * > + * Copyright (C) 2018 Jacopo Mondi > + * > + * Based on r8a7795-cpg-mssr.c > + * > + * Copyright (C) 2015 Glider bvba > + * Copyright (C) 2015 Renesas Electronics Corp. > + */ > + > +#include > +#include > +#include > +#include > + > +#include > + > +#include "renesas-cpg-mssr.h" > +#include "rcar-gen3-cpg.h" > + > +enum clk_ids { > + /* Core Clock Outputs exported to DT */ > + LAST_DT_CORE_CLK = R8A77965_CLK_OSC, > + > + /* External Input Clocks */ > + CLK_EXTAL, > + CLK_EXTALR, > + > + /* Internal Core Clocks */ > + CLK_MAIN, > + CLK_PLL0, > + CLK_PLL1, > + CLK_PLL3, > + CLK_PLL4, > + CLK_PLL1_DIV2, > + CLK_PLL1_DIV4, > + CLK_S0, > + CLK_S1, > + CLK_S2, > + CLK_S3, > + CLK_SDSRC, > + CLK_SSPSRC,
[PATCH 02/15] clk: renesas: cpg-msr: Add support for R-Car M3-N
Initial support for R-Car M3-N (r8a77965), including core and module clocks. Signed-off-by: Jacopo Mondi --- .../devicetree/bindings/clock/renesas,cpg-mssr.txt | 1 + drivers/clk/renesas/Kconfig| 5 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r8a77965-cpg-mssr.c| 333 + drivers/clk/renesas/renesas-cpg-mssr.c | 6 + drivers/clk/renesas/renesas-cpg-mssr.h | 1 + include/dt-bindings/clock/r8a77965-cpg-mssr.h | 62 7 files changed, 409 insertions(+) create mode 100644 drivers/clk/renesas/r8a77965-cpg-mssr.c create mode 100644 include/dt-bindings/clock/r8a77965-cpg-mssr.h diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt index f1890d0..246ab63 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt @@ -22,6 +22,7 @@ Required Properties: - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2) - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3) - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W) + - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N) - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M) - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3) diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 84b40b9..047d6b5 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -15,6 +15,7 @@ config CLK_RENESAS select CLK_R8A7794 if ARCH_R8A7794 select CLK_R8A7795 if ARCH_R8A7795 select CLK_R8A7796 if ARCH_R8A7796 + select CLK_R8A77965 if ARCH_R8A77965 select CLK_R8A77970 if ARCH_R8A77970 select CLK_R8A77995 if ARCH_R8A77995 select CLK_SH73A0 if ARCH_SH73A0 @@ -97,6 +98,10 @@ config CLK_R8A7796 bool "R-Car M3-W clock support" if COMPILE_TEST select CLK_RCAR_GEN3_CPG +config CLK_R8A77965 + bool "R-Car M3-N clock support" if COMPILE_TEST + select CLK_RCAR_GEN3_CPG + config CLK_R8A77970 bool "R-Car V3M clock support" if COMPILE_TEST select CLK_RCAR_GEN3_CPG diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 34c4e0b..2e0982f 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o +obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c new file mode 100644 index 000..f29d42c --- /dev/null +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -0,0 +1,333 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * r8a77965 Clock Pulse Generator / Module Standby and Software Reset + * + * Copyright (C) 2018 Jacopo Mondi + * + * Based on r8a7795-cpg-mssr.c + * + * Copyright (C) 2015 Glider bvba + * Copyright (C) 2015 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +#include + +#include "renesas-cpg-mssr.h" +#include "rcar-gen3-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R8A77965_CLK_OSC, + + /* External Input Clocks */ + CLK_EXTAL, + CLK_EXTALR, + + /* Internal Core Clocks */ + CLK_MAIN, + CLK_PLL0, + CLK_PLL1, + CLK_PLL3, + CLK_PLL4, + CLK_PLL1_DIV2, + CLK_PLL1_DIV4, + CLK_S0, + CLK_S1, + CLK_S2, + CLK_S3, + CLK_SDSRC, + CLK_SSPSRC, + CLK_RINT, + + /* Module Clocks */ + MOD_CLK_BASE +}; + +static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + DEF_INPUT("extalr", CLK_EXTALR), + + /* Internal Core Clocks */ + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), + DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), + DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN), + + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), + DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".s0",CLK_S0, CLK_PLL1_