Re: [PATCH 09/15] pinctrl: sh-pfc: r8a77965: Add SCIFs groups/functions

2018-02-14 Thread Geert Uytterhoeven 
On Tue, Feb 13, 2018 at 10:45 AM, Jacopo Mondi
 wrote:
> Add SCIF[0-5] groups and pin function definitions for R-Car M3-N.
>
> Signed-off-by: Jacopo Mondi 

Reviewed-by: Geert Uytterhoeven 

Minor nit below...

> --- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
> @@ -1577,10 +1577,306 @@ static const struct sh_pfc_pin pinmux_pins[] = {
> SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
>  };
>
> +/* - SCIF0 
> -- */
> +static const unsigned int scif0_data_pins[] = {
> +   /* RX, TX */
> +   RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
> +};
> +static const unsigned int scif0_data_mux[] = {
> +   RX0_MARK, TX0_MARK,
> +};
> +static const unsigned int scif0_clk_pins[] = {
> +   /* SCK */
> +   RCAR_GP_PIN(5, 0),
> +};
> +static const unsigned int scif0_clk_mux[] = {
> +   SCK0_MARK,
> +};
> +static const unsigned int scif0_ctrl_pins[] = {
> +   /* RTS, CTS */
> +   RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
> +};
> +static const unsigned int scif0_ctrl_mux[] = {
> +   RTS0_N_TANS_MARK, CTS0_N_MARK,

Without TANS please (cfr. recent fixes to pfc-r8a7796.c).

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH 09/15] pinctrl: sh-pfc: r8a77965: Add SCIFs groups/functions

2018-02-13 Thread Jacopo Mondi 
Add SCIF[0-5] groups and pin function definitions for R-Car M3-N.

Signed-off-by: Jacopo Mondi 
---
 drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 296 ++
 1 file changed, 296 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
index 9286aa2..6989db2 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
@@ -1577,10 +1577,306 @@ static const struct sh_pfc_pin pinmux_pins[] = {
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
 };
 
+/* - SCIF0 -- 
*/
+static const unsigned int scif0_data_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+};
+static const unsigned int scif0_data_mux[] = {
+   RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_clk_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(5, 0),
+};
+static const unsigned int scif0_clk_mux[] = {
+   SCK0_MARK,
+};
+static const unsigned int scif0_ctrl_pins[] = {
+   /* RTS, CTS */
+   RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
+};
+static const unsigned int scif0_ctrl_mux[] = {
+   RTS0_N_TANS_MARK, CTS0_N_MARK,
+};
+/* - SCIF1 -- 
*/
+static const unsigned int scif1_data_a_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
+};
+static const unsigned int scif1_data_a_mux[] = {
+   RX1_A_MARK, TX1_A_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(6, 21),
+};
+static const unsigned int scif1_clk_mux[] = {
+   SCK1_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+   /* RTS, CTS */
+   RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
+};
+static const unsigned int scif1_ctrl_mux[] = {
+   RTS1_N_TANS_MARK, CTS1_N_MARK,
+};
+static const unsigned int scif1_data_b_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
+};
+static const unsigned int scif1_data_b_mux[] = {
+   RX1_B_MARK, TX1_B_MARK,
+};
+/* - SCIF2 -- 
*/
+static const unsigned int scif2_data_a_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
+};
+static const unsigned int scif2_data_a_mux[] = {
+   RX2_A_MARK, TX2_A_MARK,
+};
+static const unsigned int scif2_clk_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(5, 9),
+};
+static const unsigned int scif2_clk_mux[] = {
+   SCK2_MARK,
+};
+static const unsigned int scif2_data_b_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
+};
+static const unsigned int scif2_data_b_mux[] = {
+   RX2_B_MARK, TX2_B_MARK,
+};
+/* - SCIF3 -- 
*/
+static const unsigned int scif3_data_a_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
+};
+static const unsigned int scif3_data_a_mux[] = {
+   RX3_A_MARK, TX3_A_MARK,
+};
+static const unsigned int scif3_clk_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(1, 22),
+};
+static const unsigned int scif3_clk_mux[] = {
+   SCK3_MARK,
+};
+static const unsigned int scif3_ctrl_pins[] = {
+   /* RTS, CTS */
+   RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
+};
+static const unsigned int scif3_ctrl_mux[] = {
+   RTS3_N_TANS_MARK, CTS3_N_MARK,
+};
+static const unsigned int scif3_data_b_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
+};
+static const unsigned int scif3_data_b_mux[] = {
+   RX3_B_MARK, TX3_B_MARK,
+};
+/* - SCIF4 -- 
*/
+static const unsigned int scif4_data_a_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
+};
+static const unsigned int scif4_data_a_mux[] = {
+   RX4_A_MARK, TX4_A_MARK,
+};
+static const unsigned int scif4_clk_a_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(2, 10),
+};
+static const unsigned int scif4_clk_a_mux[] = {
+   SCK4_A_MARK,
+};
+static const unsigned int scif4_ctrl_a_pins[] = {
+   /* RTS, CTS */
+   RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int scif4_ctrl_a_mux[] = {
+   RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
+};
+static const unsigned int scif4_data_b_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+};
+static const unsigned int scif4_data_b_mux[] = {
+   RX4_B_MARK, TX4_B_MARK,
+};
+static const unsigned int scif4_clk_b_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(1, 5),
+};
+static const unsigned int scif4_clk_b_mux[] = {
+   SCK4_B_MARK,
+};
+static const unsigned int scif4_ctrl_b_pins[] = {
+   /* RTS, CTS */
+   RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
+};
+static const unsigned int scif4_ctrl_b_mux[] = {
+   RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
+};