Re: [PATCH v2 1/2] pinctrl: sh-pfc: Add r8a77470 PFC support

2018-05-04 Thread Geert Uytterhoeven 
Hi Sergei,

On Sat, Apr 28, 2018 at 8:30 PM, Sergei Shtylyov
<sergei.shtyl...@cogentembedded.com> wrote:
> On 04/28/2018 08:40 PM, Sergei Shtylyov wrote:
>>>>> Subject: Re: [PATCH v2 1/2] pinctrl: sh-pfc: Add r8a77470 PFC support
>>>>> On Wed, Apr 4, 2018 at 5:22 PM, Biju Das <biju@bp.renesas.com> wrote:
>>>>>> Add PFC support for the R8A77470 SoC including pin groups for some
>>>>>> on-chip devices such as SCIF, AVB and MMC.
>>>>>>
>>>>>> Signed-off-by: Biju Das <biju@bp.renesas.com>
>>>>>> Reviewed-by: Fabrizio Castro <fabrizio.cas...@bp.renesas.com>
>>>
>>>>>> --- /dev/null
>>>>>> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
>>>
>>>>>> +/* - AVB
>>>>>> + */ 
>>>>>> static const
>>>>> unsigned int avb_link_pins[] = {
>>>>>> +   RCAR_GP_PIN(5, 14),
>>>>>> +};
>>>>>> +static const unsigned int avb_link_mux[] = {
>>>>>> +   AVB_LINK_MARK,
>>>>>> +};
>>>>>> +static const unsigned int avb_magic_pins[] = {
>>>>>> +   RCAR_GP_PIN(5, 15),
>>>>>> +};
>>>>>> +static const unsigned int avb_magic_mux[] = {
>>>>>> +   AVB_MAGIC_MARK,
>>>>>> +};
>>>>>> +static const unsigned int avb_phy_int_pins[] = {
>>>>>> +   RCAR_GP_PIN(5, 16),
>>>>>> +};
>>>>>> +static const unsigned int avb_phy_int_mux[] = {
>>>>>> +   AVB_PHY_INT_MARK,
>>>>>> +};
>>>>>> +static const unsigned int avb_mdio_pins[] = {
>>>>>> +   RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), }; static const
>>>>>> +unsigned int avb_mdio_mux[] = {
>>>>>> +   AVB_MDC_MARK, AVB_MDIO_MARK,
>>>>>> +};
>>>>>> +static const unsigned int avb_mii_pins[] = {
>>>>>> +   RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
>>>>>> +   RCAR_GP_PIN(3, 27),
>>>>>> +
>>>>>> +   RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
>>>>>> +   RCAR_GP_PIN(3, 5),
>>>>>> +
>>>>>> +   RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
>>>>>> +   RCAR_GP_PIN(5, 17), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(5, 23),
>>>>>> +   RCAR_GP_PIN(3, 12),
>>>>>> +};
>>>>>> +static const unsigned int avb_mii_mux[] = {
>>>>>> +   AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
>>>>>> +   AVB_TXD3_MARK,
>>>>>> +
>>>>>> +   AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
>>>>>> +   AVB_RXD3_MARK,
>>>>>> +
>>>>>> +   AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
>>>>>> +   AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
>>>>>> +   AVB_TX_CLK_MARK,
>>>>>
>>>>> You forgot AVB_COL, which is GP5_18?
>>>>
>>>> GP5_18 is shred between the signals AVB_COL and VI0_CLK. As per the RZ/G1C 
>>>> board schematic /hardware user guide
>>>> Ethernet Phy collision pin(AVB_COL) pin  is not populated on this board by 
>>>> default. It is populated only for
>>>> Video Input Channel0 pixel clock.
>>>>
>>>> Since it is initial submission, I thought of adding only board specific 
>>>> pins first and later
>>>> add this collision pin alone as a separate pin entry  in the avb group. 
>>>> That way we can support existing board
>>>> as well as any future RZ/G1C board which populates this pin. Are you ok 
>>>> for this approach?
>>
>>> Oops. That means our grouping is suboptimal. Perhaps we should revisit
>>> (for all SoCs, while keeping backwards compatibility)?
>>
>>
>>> After reading some wikipedia, I came up with:
>>>
>>> mii_tx
>>> mii_tx_er (optional)
>>> mii_rx
>>
>>I don't see why we should have the separate TX/RX subgroups just because 
>> they're
>> described separately in the Wikipedia. Or did you have some special reason 
>> to do it?

OK, so for MII:

mii_tx_rx
mii_tx_er

and for GMII:

gmii_tx_rx

>>>

Re: [PATCH v2 1/2] pinctrl: sh-pfc: Add r8a77470 PFC support

2018-04-28 Thread Sergei Shtylyov 
On 04/28/2018 08:40 PM, Sergei Shtylyov wrote:

>>>> Subject: Re: [PATCH v2 1/2] pinctrl: sh-pfc: Add r8a77470 PFC support
>>>> On Wed, Apr 4, 2018 at 5:22 PM, Biju Das <biju@bp.renesas.com> wrote:
>>>>> Add PFC support for the R8A77470 SoC including pin groups for some
>>>>> on-chip devices such as SCIF, AVB and MMC.
>>>>>
>>>>> Signed-off-by: Biju Das <biju@bp.renesas.com>
>>>>> Reviewed-by: Fabrizio Castro <fabrizio.cas...@bp.renesas.com>
>>
>>>>> --- /dev/null
>>>>> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
>>
>>>>> +/* - AVB
>>>>> + */ 
>>>>> static const
>>>> unsigned int avb_link_pins[] = {
>>>>> +   RCAR_GP_PIN(5, 14),
>>>>> +};
>>>>> +static const unsigned int avb_link_mux[] = {
>>>>> +   AVB_LINK_MARK,
>>>>> +};
>>>>> +static const unsigned int avb_magic_pins[] = {
>>>>> +   RCAR_GP_PIN(5, 15),
>>>>> +};
>>>>> +static const unsigned int avb_magic_mux[] = {
>>>>> +   AVB_MAGIC_MARK,
>>>>> +};
>>>>> +static const unsigned int avb_phy_int_pins[] = {
>>>>> +   RCAR_GP_PIN(5, 16),
>>>>> +};
>>>>> +static const unsigned int avb_phy_int_mux[] = {
>>>>> +   AVB_PHY_INT_MARK,
>>>>> +};
>>>>> +static const unsigned int avb_mdio_pins[] = {
>>>>> +   RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), }; static const
>>>>> +unsigned int avb_mdio_mux[] = {
>>>>> +   AVB_MDC_MARK, AVB_MDIO_MARK,
>>>>> +};
>>>>> +static const unsigned int avb_mii_pins[] = {
>>>>> +   RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
>>>>> +   RCAR_GP_PIN(3, 27),
>>>>> +
>>>>> +   RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
>>>>> +   RCAR_GP_PIN(3, 5),
>>>>> +
>>>>> +   RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
>>>>> +   RCAR_GP_PIN(5, 17), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(5, 23),
>>>>> +   RCAR_GP_PIN(3, 12),
>>>>> +};
>>>>> +static const unsigned int avb_mii_mux[] = {
>>>>> +   AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
>>>>> +   AVB_TXD3_MARK,
>>>>> +
>>>>> +   AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
>>>>> +   AVB_RXD3_MARK,
>>>>> +
>>>>> +   AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
>>>>> +   AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
>>>>> +   AVB_TX_CLK_MARK,
>>>>
>>>> You forgot AVB_COL, which is GP5_18?
>>>
>>> GP5_18 is shred between the signals AVB_COL and VI0_CLK. As per the RZ/G1C 
>>> board schematic /hardware user guide
>>> Ethernet Phy collision pin(AVB_COL) pin  is not populated on this board by 
>>> default. It is populated only for
>>> Video Input Channel0 pixel clock.
>>>
>>> Since it is initial submission, I thought of adding only board specific 
>>> pins first and later
>>> add this collision pin alone as a separate pin entry  in the avb group. 
>>> That way we can support existing board
>>> as well as any future RZ/G1C board which populates this pin. Are you ok for 
>>> this approach?
> 
>> Oops. That means our grouping is suboptimal. Perhaps we should revisit
>> (for all SoCs, while keeping backwards compatibility)?
> 
> 
>> After reading some wikipedia, I came up with:
>>
>> mii_tx
>> mii_tx_er (optional)
>> mii_rx
> 
>I don't see why we should have the separate TX/RX subgroups just because 
> they're
> described separately in the Wikipedia. Or did you have some special reason to 
> do it? 
> 
>> mii_col_crs (optional, half duplex)
>>
>> However, given your board uses AVB_CRS without AVB_COL, that would still
>> not be sufficient, so the last group should be split to cover your use case?
> 
>> BTW, how does it work with AVB_COL not wired to anything by default, and thus
>> floating? Do you enable pull-up/down for that pin in the PFC, or is the pin
>> just ignored in full-duplex mode?
> 
>Well, I'm seeing the strong possibility the half-duplex mode just doesn't 
> work as
> the collision indication isn't available.

   And indeed, the manuals tell me that RZ/G (and R-Car gen2) EtherAVB only 
supports
the full-duplex mode.

> [...]
> 
>> Gr{oetje,eeting}s,
>>
>> Geert

MBR, Sergei

Re: [PATCH v2 1/2] pinctrl: sh-pfc: Add r8a77470 PFC support

2018-04-28 Thread Sergei Shtylyov 
Hello!

On 04/17/2018 04:23 PM, Geert Uytterhoeven wrote:

> + Sergei

   Sorry for a delay replying, I seem to have ignored large private message and
then it got buried in other mail...
>>> Subject: Re: [PATCH v2 1/2] pinctrl: sh-pfc: Add r8a77470 PFC support
>>> On Wed, Apr 4, 2018 at 5:22 PM, Biju Das <biju@bp.renesas.com> wrote:
>>>> Add PFC support for the R8A77470 SoC including pin groups for some
>>>> on-chip devices such as SCIF, AVB and MMC.
>>>>
>>>> Signed-off-by: Biju Das <biju@bp.renesas.com>
>>>> Reviewed-by: Fabrizio Castro <fabrizio.cas...@bp.renesas.com>
> 
>>>> --- /dev/null
>>>> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
> 
>>>> +/* - AVB
>>>> + */ 
>>>> static const
>>> unsigned int avb_link_pins[] = {
>>>> +   RCAR_GP_PIN(5, 14),
>>>> +};
>>>> +static const unsigned int avb_link_mux[] = {
>>>> +   AVB_LINK_MARK,
>>>> +};
>>>> +static const unsigned int avb_magic_pins[] = {
>>>> +   RCAR_GP_PIN(5, 15),
>>>> +};
>>>> +static const unsigned int avb_magic_mux[] = {
>>>> +   AVB_MAGIC_MARK,
>>>> +};
>>>> +static const unsigned int avb_phy_int_pins[] = {
>>>> +   RCAR_GP_PIN(5, 16),
>>>> +};
>>>> +static const unsigned int avb_phy_int_mux[] = {
>>>> +   AVB_PHY_INT_MARK,
>>>> +};
>>>> +static const unsigned int avb_mdio_pins[] = {
>>>> +   RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), }; static const
>>>> +unsigned int avb_mdio_mux[] = {
>>>> +   AVB_MDC_MARK, AVB_MDIO_MARK,
>>>> +};
>>>> +static const unsigned int avb_mii_pins[] = {
>>>> +   RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
>>>> +   RCAR_GP_PIN(3, 27),
>>>> +
>>>> +   RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
>>>> +   RCAR_GP_PIN(3, 5),
>>>> +
>>>> +   RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
>>>> +   RCAR_GP_PIN(5, 17), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(5, 23),
>>>> +   RCAR_GP_PIN(3, 12),
>>>> +};
>>>> +static const unsigned int avb_mii_mux[] = {
>>>> +   AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
>>>> +   AVB_TXD3_MARK,
>>>> +
>>>> +   AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
>>>> +   AVB_RXD3_MARK,
>>>> +
>>>> +   AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
>>>> +   AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
>>>> +   AVB_TX_CLK_MARK,
>>>
>>> You forgot AVB_COL, which is GP5_18?
>>
>> GP5_18 is shred between the signals AVB_COL and VI0_CLK. As per the RZ/G1C 
>> board schematic /hardware user guide
>> Ethernet Phy collision pin(AVB_COL) pin  is not populated on this board by 
>> default. It is populated only for
>> Video Input Channel0 pixel clock.
>>
>> Since it is initial submission, I thought of adding only board specific pins 
>> first and later
>> add this collision pin alone as a separate pin entry  in the avb group. That 
>> way we can support existing board
>> as well as any future RZ/G1C board which populates this pin. Are you ok for 
>> this approach?

> Oops. That means our grouping is suboptimal. Perhaps we should revisit
> (for all SoCs, while keeping backwards compatibility)?


> After reading some wikipedia, I came up with:
> 
> mii_tx
> mii_tx_er (optional)
> mii_rx

   I don't see why we should have the separate TX/RX subgroups just because 
they're described separately in the Wikipedia. Or did you have some special 
reason to do it? 

> mii_col_crs (optional, half duplex)
> 
> However, given your board uses AVB_CRS without AVB_COL, that would still
> not be sufficient, so the last group should be split to cover your use case?

> BTW, how does it work with AVB_COL not wired to anything by default, and thus
> floating? Do you enable pull-up/down for that pin in the PFC, or is the pin
> just ignored in full-duplex mode?

   Well, I'm seeing the strong possibility the half-duplex mode just doesn't 
work as
the collision indication isn't available.

>>>> +};
>>>> +static const unsigned int avb_gmii_pins[] = {
>>>> +   RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
>>>> +   RCAR_GP_PIN(3, 27),

Re: [PATCH v2 1/2] pinctrl: sh-pfc: Add r8a77470 PFC support

2018-04-27 Thread Geert Uytterhoeven 
Hi Sergei,

Ping?

On Thu, Apr 19, 2018 at 3:56 PM, Geert Uytterhoeven
<ge...@linux-m68k.org> wrote:
> On Thu, Apr 19, 2018 at 3:48 PM, Biju Das <biju@bp.renesas.com> wrote:
>>> On Tue, Apr 17, 2018 at 11:07 AM, Biju Das <biju@bp.renesas.com>
>>> wrote:
>>> >> Subject: Re: [PATCH v2 1/2] pinctrl: sh-pfc: Add r8a77470 PFC support
>>> >> On Wed, Apr 4, 2018 at 5:22 PM, Biju Das <biju@bp.renesas.com>
>>> wrote:
>>> >> > Add PFC support for the R8A77470 SoC including pin groups for some
>>> >> > on-chip devices such as SCIF, AVB and MMC.
>>> >> >
>>> >> > Signed-off-by: Biju Das <biju@bp.renesas.com>
>>> >> > Reviewed-by: Fabrizio Castro <fabrizio.cas...@bp.renesas.com>
>>>
>>> >> > --- /dev/null
>>> >> > +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
>>>
>>> >> > +/* - AVB
>>> >> > +--
>>> >> > +-- */ static const
>>> >> unsigned int avb_link_pins[] = {
>>> >> > +   RCAR_GP_PIN(5, 14),
>>> >> > +};
>>> >> > +static const unsigned int avb_link_mux[] = {
>>> >> > +   AVB_LINK_MARK,
>>> >> > +};
>>> >> > +static const unsigned int avb_magic_pins[] = {
>>> >> > +   RCAR_GP_PIN(5, 15),
>>> >> > +};
>>> >> > +static const unsigned int avb_magic_mux[] = {
>>> >> > +   AVB_MAGIC_MARK,
>>> >> > +};
>>> >> > +static const unsigned int avb_phy_int_pins[] = {
>>> >> > +   RCAR_GP_PIN(5, 16),
>>> >> > +};
>>> >> > +static const unsigned int avb_phy_int_mux[] = {
>>> >> > +   AVB_PHY_INT_MARK,
>>> >> > +};
>>> >> > +static const unsigned int avb_mdio_pins[] = {
>>> >> > +   RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), }; static const
>>> >> > +unsigned int avb_mdio_mux[] = {
>>> >> > +   AVB_MDC_MARK, AVB_MDIO_MARK, }; static const unsigned int
>>> >> > +avb_mii_pins[] = {
>>> >> > +   RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
>>> >> > +   RCAR_GP_PIN(3, 27),
>>> >> > +
>>> >> > +   RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
>>> >> > +   RCAR_GP_PIN(3, 5),
>>> >> > +
>>> >> > +   RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
>>> >> > +   RCAR_GP_PIN(5, 17), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(5, 23),
>>> >> > +   RCAR_GP_PIN(3, 12),
>>> >> > +};
>>> >> > +static const unsigned int avb_mii_mux[] = {
>>> >> > +   AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
>>> >> > +   AVB_TXD3_MARK,
>>> >> > +
>>> >> > +   AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
>>> >> > +   AVB_RXD3_MARK,
>>> >> > +
>>> >> > +   AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
>>> >> > +   AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
>>> >> > +   AVB_TX_CLK_MARK,
>>> >>
>>> >> You forgot AVB_COL, which is GP5_18?
>>> >
>>> > GP5_18 is shred between the signals AVB_COL and VI0_CLK. As per the
>>> > RZ/G1C board schematic /hardware user guide Ethernet Phy collision
>>> > pin(AVB_COL) pin  is not populated on this board by default. It is 
>>> > populated
>>> only for Video Input Channel0 pixel clock.
>>> >
>>> > Since it is initial submission, I thought of adding only board
>>> > specific pins first and later add this collision pin alone as a
>>> > separate pin entry  in the avb group. That way we can support existing
>>> board as well as any future RZ/G1C board which populates this pin. Are you
>>> ok for this approach?
>>>
>>> Oops. That means our grouping is suboptimal. Perhaps we should revisit (for
>>> all SoCs, while keeping backwards compatibility)?
>>>
>>> After reading some wikipedia, I came up with:
>>>
>>> mii_tx
>>> mii_tx_er (optional)
>>> mii_rx
>>> mii_col_crs (optional, half duplex)
>>>
>>> However, given your

Re: [PATCH v2 1/2] pinctrl: sh-pfc: Add r8a77470 PFC support

2018-04-19 Thread Geert Uytterhoeven 
Hi Biju,

On Thu, Apr 19, 2018 at 3:48 PM, Biju Das <biju@bp.renesas.com> wrote:
>> On Tue, Apr 17, 2018 at 11:07 AM, Biju Das <biju@bp.renesas.com>
>> wrote:
>> >> Subject: Re: [PATCH v2 1/2] pinctrl: sh-pfc: Add r8a77470 PFC support
>> >> On Wed, Apr 4, 2018 at 5:22 PM, Biju Das <biju@bp.renesas.com>
>> wrote:
>> >> > Add PFC support for the R8A77470 SoC including pin groups for some
>> >> > on-chip devices such as SCIF, AVB and MMC.
>> >> >
>> >> > Signed-off-by: Biju Das <biju@bp.renesas.com>
>> >> > Reviewed-by: Fabrizio Castro <fabrizio.cas...@bp.renesas.com>
>>
>> >> > --- /dev/null
>> >> > +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
>>
>> >> > +/* - AVB
>> >> > +--
>> >> > +-- */ static const
>> >> unsigned int avb_link_pins[] = {
>> >> > +   RCAR_GP_PIN(5, 14),
>> >> > +};
>> >> > +static const unsigned int avb_link_mux[] = {
>> >> > +   AVB_LINK_MARK,
>> >> > +};
>> >> > +static const unsigned int avb_magic_pins[] = {
>> >> > +   RCAR_GP_PIN(5, 15),
>> >> > +};
>> >> > +static const unsigned int avb_magic_mux[] = {
>> >> > +   AVB_MAGIC_MARK,
>> >> > +};
>> >> > +static const unsigned int avb_phy_int_pins[] = {
>> >> > +   RCAR_GP_PIN(5, 16),
>> >> > +};
>> >> > +static const unsigned int avb_phy_int_mux[] = {
>> >> > +   AVB_PHY_INT_MARK,
>> >> > +};
>> >> > +static const unsigned int avb_mdio_pins[] = {
>> >> > +   RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), }; static const
>> >> > +unsigned int avb_mdio_mux[] = {
>> >> > +   AVB_MDC_MARK, AVB_MDIO_MARK, }; static const unsigned int
>> >> > +avb_mii_pins[] = {
>> >> > +   RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
>> >> > +   RCAR_GP_PIN(3, 27),
>> >> > +
>> >> > +   RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
>> >> > +   RCAR_GP_PIN(3, 5),
>> >> > +
>> >> > +   RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
>> >> > +   RCAR_GP_PIN(5, 17), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(5, 23),
>> >> > +   RCAR_GP_PIN(3, 12),
>> >> > +};
>> >> > +static const unsigned int avb_mii_mux[] = {
>> >> > +   AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
>> >> > +   AVB_TXD3_MARK,
>> >> > +
>> >> > +   AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
>> >> > +   AVB_RXD3_MARK,
>> >> > +
>> >> > +   AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
>> >> > +   AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
>> >> > +   AVB_TX_CLK_MARK,
>> >>
>> >> You forgot AVB_COL, which is GP5_18?
>> >
>> > GP5_18 is shred between the signals AVB_COL and VI0_CLK. As per the
>> > RZ/G1C board schematic /hardware user guide Ethernet Phy collision
>> > pin(AVB_COL) pin  is not populated on this board by default. It is 
>> > populated
>> only for Video Input Channel0 pixel clock.
>> >
>> > Since it is initial submission, I thought of adding only board
>> > specific pins first and later add this collision pin alone as a
>> > separate pin entry  in the avb group. That way we can support existing
>> board as well as any future RZ/G1C board which populates this pin. Are you
>> ok for this approach?
>>
>> Oops. That means our grouping is suboptimal. Perhaps we should revisit (for
>> all SoCs, while keeping backwards compatibility)?
>>
>> After reading some wikipedia, I came up with:
>>
>> mii_tx
>> mii_tx_er (optional)
>> mii_rx
>> mii_col_crs (optional, half duplex)
>>
>> However, given your board uses AVB_CRS without AVB_COL, that would still
>> not be sufficient, so the last group should be split to cover your use case?
>
> Ok I agree to your point. What about splitting the last group " mii_col_crs"  
> to "mii_col" and  "mii_crs" as separate groups .
> Since this pins are only meaning full in half duplex 
> mode(https://en.wikipedia.org/wiki/Media-independent_interface)

Sou

RE: [PATCH v2 1/2] pinctrl: sh-pfc: Add r8a77470 PFC support

2018-04-19 Thread Biju Das 
Hi Geert,

Thanks for the comment.

> Subject: Re: [PATCH v2 1/2] pinctrl: sh-pfc: Add r8a77470 PFC support
>
> Hi Biju,
>
> + Sergei
>
> On Tue, Apr 17, 2018 at 11:07 AM, Biju Das <biju@bp.renesas.com>
> wrote:
> >> Subject: Re: [PATCH v2 1/2] pinctrl: sh-pfc: Add r8a77470 PFC support
> >> On Wed, Apr 4, 2018 at 5:22 PM, Biju Das <biju@bp.renesas.com>
> wrote:
> >> > Add PFC support for the R8A77470 SoC including pin groups for some
> >> > on-chip devices such as SCIF, AVB and MMC.
> >> >
> >> > Signed-off-by: Biju Das <biju@bp.renesas.com>
> >> > Reviewed-by: Fabrizio Castro <fabrizio.cas...@bp.renesas.com>
>
> >> > --- /dev/null
> >> > +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
>
> >> > +/* - AVB
> >> > +--
> >> > +-- */ static const
> >> unsigned int avb_link_pins[] = {
> >> > +   RCAR_GP_PIN(5, 14),
> >> > +};
> >> > +static const unsigned int avb_link_mux[] = {
> >> > +   AVB_LINK_MARK,
> >> > +};
> >> > +static const unsigned int avb_magic_pins[] = {
> >> > +   RCAR_GP_PIN(5, 15),
> >> > +};
> >> > +static const unsigned int avb_magic_mux[] = {
> >> > +   AVB_MAGIC_MARK,
> >> > +};
> >> > +static const unsigned int avb_phy_int_pins[] = {
> >> > +   RCAR_GP_PIN(5, 16),
> >> > +};
> >> > +static const unsigned int avb_phy_int_mux[] = {
> >> > +   AVB_PHY_INT_MARK,
> >> > +};
> >> > +static const unsigned int avb_mdio_pins[] = {
> >> > +   RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), }; static const
> >> > +unsigned int avb_mdio_mux[] = {
> >> > +   AVB_MDC_MARK, AVB_MDIO_MARK, }; static const unsigned int
> >> > +avb_mii_pins[] = {
> >> > +   RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
> >> > +   RCAR_GP_PIN(3, 27),
> >> > +
> >> > +   RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
> >> > +   RCAR_GP_PIN(3, 5),
> >> > +
> >> > +   RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
> >> > +   RCAR_GP_PIN(5, 17), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(5, 23),
> >> > +   RCAR_GP_PIN(3, 12),
> >> > +};
> >> > +static const unsigned int avb_mii_mux[] = {
> >> > +   AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
> >> > +   AVB_TXD3_MARK,
> >> > +
> >> > +   AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
> >> > +   AVB_RXD3_MARK,
> >> > +
> >> > +   AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
> >> > +   AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
> >> > +   AVB_TX_CLK_MARK,
> >>
> >> You forgot AVB_COL, which is GP5_18?
> >
> > GP5_18 is shred between the signals AVB_COL and VI0_CLK. As per the
> > RZ/G1C board schematic /hardware user guide Ethernet Phy collision
> > pin(AVB_COL) pin  is not populated on this board by default. It is populated
> only for Video Input Channel0 pixel clock.
> >
> > Since it is initial submission, I thought of adding only board
> > specific pins first and later add this collision pin alone as a
> > separate pin entry  in the avb group. That way we can support existing
> board as well as any future RZ/G1C board which populates this pin. Are you
> ok for this approach?
>
> Oops. That means our grouping is suboptimal. Perhaps we should revisit (for
> all SoCs, while keeping backwards compatibility)?
>
> After reading some wikipedia, I came up with:
>
> mii_tx
> mii_tx_er (optional)
> mii_rx
> mii_col_crs (optional, half duplex)
>
> However, given your board uses AVB_CRS without AVB_COL, that would still
> not be sufficient, so the last group should be split to cover your use case?

Ok I agree to your point. What about splitting the last group " mii_col_crs"  
to "mii_col" and  "mii_crs" as separate groups .
Since this pins are only meaning full in half duplex 
mode(https://en.wikipedia.org/wiki/Media-independent_interface)

> BTW, how does it work with AVB_COL not wired to anything by default, and
> thus floating? Do you enable pull-up/down for that pin in the PFC, or is the
> pin just ignored in full-duplex mode?

Since it is unwired, the pin is in GPIO mode, high impedance state(ZU) with 
initial state is pull-up "o

Re: [PATCH v2 1/2] pinctrl: sh-pfc: Add r8a77470 PFC support

2018-04-17 Thread Geert Uytterhoeven 
Hi Biju,

+ Sergei

On Tue, Apr 17, 2018 at 11:07 AM, Biju Das <biju@bp.renesas.com> wrote:
>> Subject: Re: [PATCH v2 1/2] pinctrl: sh-pfc: Add r8a77470 PFC support
>> On Wed, Apr 4, 2018 at 5:22 PM, Biju Das <biju@bp.renesas.com> wrote:
>> > Add PFC support for the R8A77470 SoC including pin groups for some
>> > on-chip devices such as SCIF, AVB and MMC.
>> >
>> > Signed-off-by: Biju Das <biju@bp.renesas.com>
>> > Reviewed-by: Fabrizio Castro <fabrizio.cas...@bp.renesas.com>

>> > --- /dev/null
>> > +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c

>> > +/* - AVB
>> > + */ 
>> > static const
>> unsigned int avb_link_pins[] = {
>> > +   RCAR_GP_PIN(5, 14),
>> > +};
>> > +static const unsigned int avb_link_mux[] = {
>> > +   AVB_LINK_MARK,
>> > +};
>> > +static const unsigned int avb_magic_pins[] = {
>> > +   RCAR_GP_PIN(5, 15),
>> > +};
>> > +static const unsigned int avb_magic_mux[] = {
>> > +   AVB_MAGIC_MARK,
>> > +};
>> > +static const unsigned int avb_phy_int_pins[] = {
>> > +   RCAR_GP_PIN(5, 16),
>> > +};
>> > +static const unsigned int avb_phy_int_mux[] = {
>> > +   AVB_PHY_INT_MARK,
>> > +};
>> > +static const unsigned int avb_mdio_pins[] = {
>> > +   RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), }; static const
>> > +unsigned int avb_mdio_mux[] = {
>> > +   AVB_MDC_MARK, AVB_MDIO_MARK,
>> > +};
>> > +static const unsigned int avb_mii_pins[] = {
>> > +   RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
>> > +   RCAR_GP_PIN(3, 27),
>> > +
>> > +   RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
>> > +   RCAR_GP_PIN(3, 5),
>> > +
>> > +   RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
>> > +   RCAR_GP_PIN(5, 17), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(5, 23),
>> > +   RCAR_GP_PIN(3, 12),
>> > +};
>> > +static const unsigned int avb_mii_mux[] = {
>> > +   AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
>> > +   AVB_TXD3_MARK,
>> > +
>> > +   AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
>> > +   AVB_RXD3_MARK,
>> > +
>> > +   AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
>> > +   AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
>> > +   AVB_TX_CLK_MARK,
>>
>> You forgot AVB_COL, which is GP5_18?
>
> GP5_18 is shred between the signals AVB_COL and VI0_CLK. As per the RZ/G1C 
> board schematic /hardware user guide
> Ethernet Phy collision pin(AVB_COL) pin  is not populated on this board by 
> default. It is populated only for
> Video Input Channel0 pixel clock.
>
> Since it is initial submission, I thought of adding only board specific pins 
> first and later
> add this collision pin alone as a separate pin entry  in the avb group. That 
> way we can support existing board
> as well as any future RZ/G1C board which populates this pin. Are you ok for 
> this approach?

Oops. That means our grouping is suboptimal. Perhaps we should revisit
(for all SoCs, while keeping backwards compatibility)?

After reading some wikipedia, I came up with:

mii_tx
mii_tx_er (optional)
mii_rx
mii_col_crs (optional, half duplex)

However, given your board uses AVB_CRS without AVB_COL, that would still
not be sufficient, so the last group should be split to cover your use case?

BTW, how does it work with AVB_COL not wired to anything by default, and thus
floating? Do you enable pull-up/down for that pin in the PFC, or is the pin
just ignored in full-duplex mode?

>> > +};
>> > +static const unsigned int avb_gmii_pins[] = {
>> > +   RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
>> > +   RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
>> > +   RCAR_GP_PIN(4, 0), RCAR_GP_PIN(5, 22),
>> > +
>> > +   RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
>> > +   RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
>> > +   RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
>> > +
>> > +   RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
>> > +   RCAR_GP_PIN(5, 17), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(3, 11),
>> > +   RCAR_GP_PIN(3, 13), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(3, 12), };
>> > +static const unsigned int avb_gmii_mux[] = {
>> > +   AVB_TXD0_MARK, AVB_TXD1_MARK,

RE: [PATCH v2 1/2] pinctrl: sh-pfc: Add r8a77470 PFC support

2018-04-17 Thread Biju Das 
Hi Geert,

Thanks  for the comment.

> Subject: Re: [PATCH v2 1/2] pinctrl: sh-pfc: Add r8a77470 PFC support
> Hi Biju,
>
> On Wed, Apr 4, 2018 at 5:22 PM, Biju Das <biju@bp.renesas.com> wrote:
> > Add PFC support for the R8A77470 SoC including pin groups for some
> > on-chip devices such as SCIF, AVB and MMC.
> >
> > Signed-off-by: Biju Das <biju@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.cas...@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
> > @@ -0,0 +1,2156 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * R8A77470 processor support - PFC hardware block.
> > + *
> > + * Copyright (C) 2018 Renesas Electronics Corp.
> > + */
> > +
> > +#include 
> > +
> > +#include "sh_pfc.h"
> > +
> > +#define CPU_ALL_PORT(fn, sfx)  \
> > +   PORT_GP_23(0, fn, sfx), \
> > +   PORT_GP_23(1, fn, sfx), \
> > +   PORT_GP_32(2, fn, sfx), \
> > +   PORT_GP_17(3, fn, sfx), \
> > +   PORT_GP_1(3, 27, fn, sfx),  \
> > +   PORT_GP_1(3, 28, fn, sfx),  \
> > +   PORT_GP_1(3, 29, fn, sfx),  \
>
> (Oh, they have a hole in the GPIO range...)
Yes it is correct. There is a hole between GP3-16 to GP3-27.
>
> > +   PORT_GP_26(4, fn, sfx), \
> > +   PORT_GP_32(5, fn, sfx)
>
> > +/* - AVB
> > + */ 
> > static const
> unsigned int avb_link_pins[] = {
> > +   RCAR_GP_PIN(5, 14),
> > +};
> > +static const unsigned int avb_link_mux[] = {
> > +   AVB_LINK_MARK,
> > +};
> > +static const unsigned int avb_magic_pins[] = {
> > +   RCAR_GP_PIN(5, 15),
> > +};
> > +static const unsigned int avb_magic_mux[] = {
> > +   AVB_MAGIC_MARK,
> > +};
> > +static const unsigned int avb_phy_int_pins[] = {
> > +   RCAR_GP_PIN(5, 16),
> > +};
> > +static const unsigned int avb_phy_int_mux[] = {
> > +   AVB_PHY_INT_MARK,
> > +};
> > +static const unsigned int avb_mdio_pins[] = {
> > +   RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), }; static const
> > +unsigned int avb_mdio_mux[] = {
> > +   AVB_MDC_MARK, AVB_MDIO_MARK,
> > +};
> > +static const unsigned int avb_mii_pins[] = {
> > +   RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
> > +   RCAR_GP_PIN(3, 27),
> > +
> > +   RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
> > +   RCAR_GP_PIN(3, 5),
> > +
> > +   RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
> > +   RCAR_GP_PIN(5, 17), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(5, 23),
> > +   RCAR_GP_PIN(3, 12),
> > +};
> > +static const unsigned int avb_mii_mux[] = {
> > +   AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
> > +   AVB_TXD3_MARK,
> > +
> > +   AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
> > +   AVB_RXD3_MARK,
> > +
> > +   AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
> > +   AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
> > +   AVB_TX_CLK_MARK,
>
> You forgot AVB_COL, which is GP5_18?

GP5_18 is shred between the signals AVB_COL and VI0_CLK. As per the RZ/G1C 
board schematic /hardware user guide
Ethernet Phy collision pin(AVB_COL) pin  is not populated on this board by 
default. It is populated only for
Video Input Channel0 pixel clock.

Since it is initial submission, I thought of adding only board specific pins 
first and later
add this collision pin alone as a separate pin entry  in the avb group. That 
way we can support existing board
as well as any future RZ/G1C board which populates this pin. Are you ok for 
this approach?

> > +};
> > +static const unsigned int avb_gmii_pins[] = {
> > +   RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
> > +   RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
> > +   RCAR_GP_PIN(4, 0), RCAR_GP_PIN(5, 22),
> > +
> > +   RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
> > +   RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
> > +   RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
> > +
> > +   RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3,

Re: [PATCH v2 1/2] pinctrl: sh-pfc: Add r8a77470 PFC support

2018-04-16 Thread Geert Uytterhoeven 
Hi Biju,

On Wed, Apr 4, 2018 at 5:22 PM, Biju Das  wrote:
> Add PFC support for the R8A77470 SoC including pin groups for
> some on-chip devices such as SCIF, AVB and MMC.
>
> Signed-off-by: Biju Das 
> Reviewed-by: Fabrizio Castro 

Thanks for your patch!

> --- /dev/null
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
> @@ -0,0 +1,2156 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * R8A77470 processor support - PFC hardware block.
> + *
> + * Copyright (C) 2018 Renesas Electronics Corp.
> + */
> +
> +#include 
> +
> +#include "sh_pfc.h"
> +
> +#define CPU_ALL_PORT(fn, sfx)  \
> +   PORT_GP_23(0, fn, sfx), \
> +   PORT_GP_23(1, fn, sfx), \
> +   PORT_GP_32(2, fn, sfx), \
> +   PORT_GP_17(3, fn, sfx), \
> +   PORT_GP_1(3, 27, fn, sfx),  \
> +   PORT_GP_1(3, 28, fn, sfx),  \
> +   PORT_GP_1(3, 29, fn, sfx),  \

(Oh, they have a hole in the GPIO range...)

> +   PORT_GP_26(4, fn, sfx), \
> +   PORT_GP_32(5, fn, sfx)

> +/* - AVB 
>  */
> +static const unsigned int avb_link_pins[] = {
> +   RCAR_GP_PIN(5, 14),
> +};
> +static const unsigned int avb_link_mux[] = {
> +   AVB_LINK_MARK,
> +};
> +static const unsigned int avb_magic_pins[] = {
> +   RCAR_GP_PIN(5, 15),
> +};
> +static const unsigned int avb_magic_mux[] = {
> +   AVB_MAGIC_MARK,
> +};
> +static const unsigned int avb_phy_int_pins[] = {
> +   RCAR_GP_PIN(5, 16),
> +};
> +static const unsigned int avb_phy_int_mux[] = {
> +   AVB_PHY_INT_MARK,
> +};
> +static const unsigned int avb_mdio_pins[] = {
> +   RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
> +};
> +static const unsigned int avb_mdio_mux[] = {
> +   AVB_MDC_MARK, AVB_MDIO_MARK,
> +};
> +static const unsigned int avb_mii_pins[] = {
> +   RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
> +   RCAR_GP_PIN(3, 27),
> +
> +   RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
> +   RCAR_GP_PIN(3, 5),
> +
> +   RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
> +   RCAR_GP_PIN(5, 17), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(5, 23),
> +   RCAR_GP_PIN(3, 12),
> +};
> +static const unsigned int avb_mii_mux[] = {
> +   AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
> +   AVB_TXD3_MARK,
> +
> +   AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
> +   AVB_RXD3_MARK,
> +
> +   AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
> +   AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
> +   AVB_TX_CLK_MARK,

You forgot AVB_COL, which is GP5_18?

> +};
> +static const unsigned int avb_gmii_pins[] = {
> +   RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
> +   RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
> +   RCAR_GP_PIN(4, 0), RCAR_GP_PIN(5, 22),
> +
> +   RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
> +   RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
> +   RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
> +
> +   RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
> +   RCAR_GP_PIN(5, 17), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(3, 11),
> +   RCAR_GP_PIN(3, 13), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(3, 12),
> +};
> +static const unsigned int avb_gmii_mux[] = {
> +   AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
> +   AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
> +   AVB_TXD6_MARK, AVB_TXD7_MARK,
> +
> +   AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
> +   AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
> +   AVB_RXD6_MARK, AVB_RXD7_MARK,
> +
> +   AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
> +   AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
> +   AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,

You forgot AVB_COL, which is GP5_18?

> +};

Any specific reason you haven't added the avb_avtp_capture and
avb_avtp_match pins?

> +/* - SCIF1 
> -- */
> +static const unsigned int scif1_data_b_pins[] = {
> +   /* RX, TX */
> +   RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
> +};
> +static const unsigned int scif1_data_b_mux[] = {
> +   RX1_B_MARK, TX1_B_MARK,
> +};
> +/* - SCIF2 
> -- */
> +static const unsigned int scif2_data_b_pins[] = {
> +   /* RX, TX */
> +   RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26),
> +};
> +static const unsigned int scif2_data_b_mux[] = {
> +   RX2_B_MARK, TX2_B_MARK,
> +};
> +/* - SCIF4 
>