Ping Kukjin.
Can you please add this series to your tree?
On 16 April 2013 15:35, Sachin Kamat sachin.ka...@linaro.org wrote:
These symbols are used only in this file and hence should be
static.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
drivers/clk/samsung/clk-exynos4.c |
On 18 April 2013 22:29, Mike Turquette mturque...@linaro.org wrote:
Quoting Sachin Kamat (2013-04-18 04:15:15)
Add G2D clocks for Exynos4x12 SoC and sclk_fimg2d required by G2D
IP.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
Cc: Thomas Abraham thomas.abra...@linaro.org
Cc: Mike
On 22 April 2013 09:25, Sachin Kamat sachin.ka...@linaro.org wrote:
Added clock entries for thermal management unit (TMU) for
Exynos4 SoCs.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
Cc: Thomas Abraham thomas.abra...@linaro.org
Cc: Mike Turquette mturque...@linaro.org
---
Should
Exynos hdmi driver is using drm_display_mode for setting timing values
for a supported resolution. Conversion to fb_videomode and then comparing
with the mixer/hdmi/phy limits is not required. Instead, drm_display_mode
fields cane be directly compared.
v4:
1) Removed __func__ from DRM_DEBUG_KMS.
Hello Rahul,
I looks good to me.
On 2013년 04월 29일 20:14, Rahul Sharma wrote:
Exynos hdmi driver is using drm_display_mode for setting timing values
for a supported resolution. Conversion to fb_videomode and then comparing
with the mixer/hdmi/phy limits is not required. Instead,
Hi Shaik,
Thanks for the updated patch series.
On 04/24/2013 09:41 AM, Shaik Ameer Basha wrote:
Current fimc_pipeline is tightly coupled with exynos4-is media
device driver. And this will not allow to use the same pipeline
across different exynos series media device drivers.
This patch
The kernel crashes while resuming from AFTR idle mode. It happens
because L2 cache was not going into retention state.
This patch configures the USE_RETENTION bit of ARM_L2_OPTION register
so that it does not depend on MANUAL_L2RSTDISABLE_CONTROL of
ARM_COMMON_OPTION register for L2RSTDISABLE
On 29 April 2013 17:01, Inderpal Singh inderpal.si...@linaro.org wrote:
The kernel crashes while resuming from AFTR idle mode. It happens
because L2 cache was not going into retention state.
This patch configures the USE_RETENTION bit of ARM_L2_OPTION register
so that it does not depend on
On 04/24/2013 09:41 AM, Shaik Ameer Basha wrote:
This patch adds,
1] Exynos5 soc compatibility to the fimc-lite driver
2] Multiple dma output buffer support as from Exynos5 onwards,
fimc-lite h/w ip supports multiple dma buffers.
Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com
Right now hdmiphy operations and configs are kept inside hdmi driver. hdmiphy
related code is tightly coupled with hdmi ip driver. Physicaly they are
different devices and should be instantiated independently.
In terms of versions/mapping/configurations Hdmi and hdmiphy are independent
of each
Exynos hdmi sub-system consists of mixer, hdmi ip, hdmi-phy and hdmi-ddc
components. Currently, drivers for these components are getting registered
in exynos_drm_drv.c, which is meant for registration of drm sub-drivers.
In this patch, registration of drm hdmi sub-driver and device, drivers for
hdmiphy hardware block is a physically separate device. Hdmiphy driver
is glued inside hdmi driver and acessed through hdmi callbacks. With
increasing diversities in the hdmiphy mapping and configurations, hdmi
driver is expanding with un-related changes.
This patch registers hdmiphy as a
Hdmiphy callbacks are tighly coupled with hdmi IP callbacks inside
the hdmi driver. With increase in the support of different versions of
hdmiphys, hdmi ip driver expanding with lots of phy related information.
Above movement ensures that phy related code is present and maintained
within the
Hdmiphy clock flows from hdmiphy hw to hdmi ip and mixer. It is commonly
accessed among hdmi and hdmiphy driver. During power cycle, each of these
driver decrements the ref-count and ensures that last user disables the
clock. Setting parrent device to none ensure that both the drivers gets
access
On 04/24/2013 09:41 AM, Shaik Ameer Basha wrote:
FIMC-LITE supports multiple DMA shadow registers from Exynos5 onwards.
This patch adds the functionality of using shadow registers by
checking the driver data.
Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com
---
On 04/24/2013 09:41 AM, Shaik Ameer Basha wrote:
FIMC-IS firmware needs all the MIPI-CSIS interrupts to be enabled.
This patch enables all those MIPI interrupts and adds the Exynos5
compatible string.
Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com
---
On 04/24/2013 09:41 AM, Shaik Ameer Basha wrote:
This patch adds support for media device for EXYNOS5 SoCs.
The current media device supports the following ips to connect
through the media controller framework.
Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com
---
On Mon, Apr 29, 2013 at 7:14 AM, Rahul Sharma rahul.sha...@samsung.com wrote:
Exynos hdmi driver is using drm_display_mode for setting timing values
for a supported resolution. Conversion to fb_videomode and then comparing
with the mixer/hdmi/phy limits is not required. Instead,
On Mon, Apr 29, 2013 at 10:50 AM, Rahul Sharma rahul.sha...@samsung.com wrote:
Exynos hdmi sub-system consists of mixer, hdmi ip, hdmi-phy and hdmi-ddc
components. Currently, drivers for these components are getting registered
in exynos_drm_drv.c, which is meant for registration of drm
Quoting Sachin Kamat (2013-04-21 20:55:46)
Added clock entries for thermal management unit (TMU) for
Exynos4 SoCs.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
Cc: Thomas Abraham thomas.abra...@linaro.org
Cc: Mike Turquette mturque...@linaro.org
This has my Ack if you plan to take
On Mon, Apr 29, 2013 at 10:50 AM, Rahul Sharma rahul.sha...@samsung.com wrote:
Hdmiphy clock flows from hdmiphy hw to hdmi ip and mixer. It is commonly
accessed among hdmi and hdmiphy driver. During power cycle, each of these
driver decrements the ref-count and ensures that last user disables
Hi,
On 04/29/2013 07:04 PM, Sean Paul wrote:
On Mon, Apr 29, 2013 at 10:50 AM, Rahul Sharma rahul.sha...@samsung.com
wrote:
Hdmiphy clock flows from hdmiphy hw to hdmi ip and mixer. It is commonly
accessed among hdmi and hdmiphy driver. During power cycle, each of these
driver decrements
On Mon, Apr 29, 2013 at 11:07 PM, Sylwester Nawrocki
s.nawro...@samsung.com wrote:
Hi,
On 04/29/2013 07:04 PM, Sean Paul wrote:
On Mon, Apr 29, 2013 at 10:50 AM, Rahul Sharma rahul.sha...@samsung.com
wrote:
Hdmiphy clock flows from hdmiphy hw to hdmi ip and mixer. It is commonly
accessed
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