On Mon, Apr 29, 2013 at 10:06 PM, Sean Paul seanp...@google.com wrote:
On Mon, Apr 29, 2013 at 10:50 AM, Rahul Sharma rahul.sha...@samsung.com
wrote:
Exynos hdmi sub-system consists of mixer, hdmi ip, hdmi-phy and hdmi-ddc
components. Currently, drivers for these components are getting
The s3c24xx pins follow a similar pattern as the other Samsung SoCs and
can therefore reuse the already introduced infrastructure.
The s3c24xx SoCs have one design oddity in that the first 4 external
interrupts do not reside in the eint pending register but in the main
interrupt controller
On Fri, May 3, 2013 at 2:04 AM, Rahul Sharma r.sh.o...@gmail.com wrote:
On Mon, Apr 29, 2013 at 10:06 PM, Sean Paul seanp...@google.com wrote:
On Mon, Apr 29, 2013 at 10:50 AM, Rahul Sharma rahul.sha...@samsung.com
wrote:
Exynos hdmi sub-system consists of mixer, hdmi ip, hdmi-phy and
On Fri, May 3, 2013 at 4:25 AM, Rahul Sharma r.sh.o...@gmail.com wrote:
Hi Sean,
On Mon, Apr 29, 2013 at 10:28 PM, Sean Paul seanp...@chromium.org wrote:
On Mon, Apr 29, 2013 at 10:50 AM, Rahul Sharma rahul.sha...@samsung.com
wrote:
hdmiphy hardware block is a physically separate device.