On 17 May 2013 15:40, Naveen Krishna Chatradhi ch.nav...@samsung.com wrote:
Adds support for High Speed I2C driver found in Exynos5 and
later SoCs from Samsung.
Driver only supports Device Tree method.
Changes since v1:
1. Added FIFO functionality
2. Added High speed mode functionality
3.
Hi Kukjin,
On Thursday 23 of May 2013 10:11:17 Kukjin Kim wrote:
Kukjin Kim wrote:
Tomasz Figa wrote:
Hi Kukjin,
Hi,
On Wednesday 15 of May 2013 17:08:04 Tomasz Figa wrote:
This patch extends exynos_init_time() function to handle Exynos4210
rev0
SoC, which differs
NAK
In testing we have seen that, when sysmmu of mfc/gscl is used,
the respective IP clock has to be ON, or else it was malfunctioning.
So for smmu_mfcl and smmu_mfcr, the parent should be mfc
so that we make sure the parent is turned on every time sysmmu is accessed.
Same thing applies to gscl
This patch fixes software reset logic. Software reset applies only to
powered-on domains in SOC because software reset to all domains causes
reboot failure.
Signed-off-by: Jungseok Lee jays@samsung.com
---
arch/arm/mach-exynos/common.c |6 +-
1 file changed, 5 insertions(+), 1
On 05/18/2013 10:30 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 16:57 Sat 18 May , Tomasz Figa wrote:
...
Personally I'd prefer a solution with separate property for each
parameter, because it's much more flexible and allows shorter lines,
making device tree sources more readable.
On 05/19/2013 03:17 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
...
how a pin can not have mux?
Well, if that's the way HW is designed, that's just the way it is.
There are certainly pins on Tegra which don't have a mux in HW, but have
some configuration options such as drive strength that can
On Wed, 15 May 2013 17:16:08 +0200 Tomasz Figa t.f...@samsung.com wrote:
Currently the driver can crash with a NULL pointer dereference if no pdata
is provided, despite of successful registration of MFD part. This patch
fixes the problem by adding a NULL check before dereferencing the pdata
Hi Tomasz,
Thanks for your review.
+ DIV(aclk_400_g3d, aclk_400_g3d, mout_aclk400, DIV_TOP0, 24,
3),
Do you need to export this div clock? If it's a parent of a gate clock,
then you can simply add CLK_SET_RATE_PARENT flag to the gate clock and
calling set_rate on it will reconfigure
Hi Doug,
Thanks for the review.
But as per Tomasz Figa's comment, I will remove the exporting of aclk_400_g3d
to the driver.
Regards
Arun
On Wed, May 22, 2013 at 4:13 AM, Doug Anderson diand...@chromium.org wrote:
Arun,
On Tue, May 21, 2013 at 5:36 AM, Arun Kumar K arun...@samsung.com wrote:
This patch series does the following:
1) Factors out possible common code, unifies the clk strutures used
for PLL35XX PLL36XX and usues clk-base instead of clk-con0
2) Defines a common rate_table which will contain recommended p, m, s and k
values for supported rates that needs to be
From: Yadwinder Singh Brar yadi.b...@samsung.com
Adds set_rate() and round_rate() clk_ops for PLL35XX
The round_rate() implemenation as of now is dummy, it returns the same rate
which is passed as input.
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
This patch adds set_rate and round_rate clk_ops for PLL36XX.
The round_rate() implementation as of now is dummy, it returns the same rate
which is passed as input.
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
drivers/clk/samsung/clk-pll.c | 67
Adds the EPLL and VPLL freq table for exynos5250 SoC.
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
drivers/clk/samsung/clk-exynos5250.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5250.c
This patch series does the following:
1) Factors out possible common code, unifies the clk strutures used
for PLL35XX PLL36XX and usues clk-base instead of clk-con0
2) Defines a common rate_table which will contain recommended p, m, s and k
values for supported rates that needs to be
From: Yadwinder Singh Brar yadi.b...@samsung.com
This patch defines a common rate_table which will contain recommended p, m, s
and k values for supported rates that needs to be changed for changing
corresponding PLL's rate.
It also sorts the rate table while registering the PLL rate table.
So
From: Yadwinder Singh Brar yadi.b...@samsung.com
Adds set_rate() and round_rate() clk_ops for PLL35xx
The round_rate() implemenation as of now is dummy, it returns the same rate
which is passed as input.
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
This patch adds set_rate and round_rate clk_ops for PLL36xx
The round_rate() implementation as of now is dummy, it returns the same rate
which is passed as input.
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
drivers/clk/samsung/clk-pll.c | 67
Adds the EPLL and VPLL freq table for exynos5250 SoC.
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
drivers/clk/samsung/clk-exynos5250.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5250.c
From: Yadwinder Singh Brar yadi.b...@samsung.com
To factor out possible common code, this patch unifies the clk strutures used
for PLL35xx PLL36xx and usues clk-base instead of clk-con0.
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c| 10
19 matches
Mail list logo
