Up till now Exynos5250 and Exynos4412 had the same definitions for TMU
data. Following commit changes that, by introducing separate
exynos4412_default_tmu_data structure.
Since Exynos4412 was chronologically first, the corresponding name for
TMU registers and default data was renamed.
Additionall
The commit 4de0bdaa9677d11406c9becb70c60887c957e1f0
("thermal: exynos: Add support for instance based register/unregister")
broke check for presence of therm_dev at global thermal zone in
exynos_report_trigger().
The resulting wrong test prevents thermal_zone_device_update() call, which
calls hand
The commit d0a0ce3e77c795258d47f9163e92d5031d0c5221 ("thermal: exynos: Add
missing definations and code cleanup") has removed setting of test MUX address
value at TMU configuration setting.
This field is not present on Exynos4210 and Exynos5 SoCs. However on Exynos4412
SoC it is required to set th
The TMU device tree node definition for Exynos4x12 family of SoCs.
Signed-off-by: Lukasz Majewski
Reviewed-by: Bartlomiej Zolnierkiewicz
Reviewed-by: Tomasz Figa
---
Changes for v2:
- None
arch/arm/boot/dts/exynos4x12.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arc
This patch enables support for TMU at Exynos4412 based Trats2 board.
Signed-off-by: Lukasz Majewski
Reviewed-by: Bartlomiej Zolnierkiewicz
Reviewed-by: Tomasz Figa
---
Changes for v2:
- None
arch/arm/boot/dts/exynos4412-trats2.dts |5 +
1 file changed, 5 insertions(+)
diff --git a/a
This patch series is divided into two parts:
1. Device tree node definition and enabelement for TMU at Exynos4412 (Trats2)
2. Exynos thermal subsystem regressions for v3.12-rc4. Several commits were
necessary to properly fix regression for TMU test MUX address setting after
reset.
Test HW:
On Tuesday, October 08, 2013 3:23 PM, Kishon Vijay Abraham I wrote:
> On Friday 06 September 2013 12:24 PM, Jingoo Han wrote:
> > This patch adds support for Message Signaled Interrupt in the
> > Exynos PCIe diver using Synopsys designware PCIe core IP.
> >
> > Signed-off-by: Siva Reddy Kallam
> >
Hi Doug,
On Tue, Oct 8, 2013 at 9:39 PM, Doug Anderson wrote:
> Arun,
>
> On Mon, Oct 7, 2013 at 11:56 PM, Arun Kumar K wrote:
>> PLL35XX lock factor is 250 as per the manual whereas its
>> wrongly set as 270 now.
>>
>> Signed-off-by: Arun Kumar K
>> ---
>> drivers/clk/samsung/clk-pll.c |4
[Adding Tony, who reported a mainline booting issue, and Sean who
helped me track this down]
On Mon, Sep 23, 2013 at 7:15 AM, Mark Rutland wrote:
> On Sat, Sep 21, 2013 at 04:24:59PM +0100, Tomasz Figa wrote:
>> Hi Yuvaraj,
>>
>> On Wednesday 18 of September 2013 15:41:53 Yuvaraj Kumar C D wrote:
We had some issues with deferred probing in the I2C subsystem. This series
attempts to fix a part of it. From the patch description:
===
Subsystems like pinctrl and gpio rightfully make use of deferred probing at
core level. Now, deferred drivers won't be retried if they don't have a .probe
funct
Subsystems like pinctrl and gpio rightfully make use of deferred probing at
core level. Now, deferred drivers won't be retried if they don't have a .probe
function specified in the driver struct. Fix this driver to have that, so the
devices it supports won't get lost in a deferred probe.
Signed-of
Hi,
On Wed, Sep 18, 2013 at 12:20 PM, Heiko Stübner wrote:
> This includes defining the mapping for the request sources.
>
> Signed-off-by: Heiko Stuebner
> Acked-by: Linus Walleij
> ---
> changes since v1:
> - follow new pdata definition
This showed up in -next today, and introduced:
arch/ar
Hi Mike and Kukjin,
Any decisions regarding this patchset? I believe all comments have
been addressed.
Thanks,
Andrew
On Wed, Sep 25, 2013 at 2:12 PM, Andrew Bresticker
wrote:
> The Exynos AudioSS clock controller will later be modified to allow
> input clocks to be specified via device-tree i
Arun,
On Mon, Oct 7, 2013 at 11:56 PM, Arun Kumar K wrote:
> PLL35XX lock factor is 250 as per the manual whereas its
> wrongly set as 270 now.
>
> Signed-off-by: Arun Kumar K
> ---
> drivers/clk/samsung/clk-pll.c |4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
I don't think thi
Hi,
On 10/08/2013 02:44 PM, Yuvaraj Kumar wrote:
> On Fri, Oct 4, 2013 at 6:03 AM, Jingoo Han wrote:
>> On Thursday, October 03, 2013 8:32 PM, Bartlomiej Zolnierkiewicz wrote:
>>> On Tuesday, October 01, 2013 12:03:01 PM Yuvaraj Kumar C D wrote:
Exynos5250 contains one Synopsys AHCI SATA con
On Fri, Oct 4, 2013 at 6:03 AM, Jingoo Han wrote:
> On Thursday, October 03, 2013 8:32 PM, Bartlomiej Zolnierkiewicz wrote:
>> On Tuesday, October 01, 2013 12:03:01 PM Yuvaraj Kumar C D wrote:
>> > Exynos5250 contains one Synopsys AHCI SATA controller.The avalaible
>> > ahci_platform driver is not
From: Mark Brown
Ensure that unused I2C controllers are not activated, causing problems due
to inappropriate pinmuxing or similar, by marking the controllers as
disabled by default and requiring boards to explicitly enable those that
are in use.
Signed-off-by: Mark Brown
Acked-by: Tomasz Figa
From: Mark Brown
There is a 16.934MHz fixed rate clock connected to MCLK1 on the CODEC, add
this to the device tree bindings.
Signed-off-by: Mark Brown
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-smdk52
From: Mark Brown
Make it easier to notice the common file for ChromeOS devices based on
the Exynos5250 by giving it the exynos5250 prefix that the boards have.
Signed-off-by: Mark Brown
Acked-by: Tomasz Figa
---
arch/arm/boot/dts/cros5250-common.dtsi| 313 --
a
From: Mark Brown
Rather than requiring each board to explicitly disable the I2S controllers
it is not using instead require boards to enable those that they are using.
This is required for audio operation on Arndale, one of the unused I2S
controllers is pinmuxed with the LDO enable GPIOs for the
From: Mark Brown
Rather than requiring each board to explicitly disable the SPI controllers
it is not using instead require boards to enable those that they are using.
This is less work overall since normally at most one of the controllers is
in use and avoids issues caused by inappropriate pinmu
On Thu, Aug 29, 2013 at 8:12 AM, Mike Turquette wrote:
> Quoting Vikas Sajjan (2013-08-28 06:39:56)
>> Adds GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and
>> exynos5250.
>>
>> changes since v1:
>> - addressed comments from Tomasz Figa
>>
>> is rebased on Mike's
>> https://
Hi Mike,
On Monday 07 of October 2013 22:57:30 Mike Turquette wrote:
> Quoting Tomasz Figa (2013-08-30 06:51:20)
>
> > Hi Mike,
> >
> > On Monday 26 of August 2013 19:08:55 Tomasz Figa wrote:
> > > This series fixes various functional and non-functional (e.g. stylistic)
> > > issues in Common Cl
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