On 15 October 2013 11:36, Heiko Schocher h...@denx.de wrote:
Hello Naveen,
Am 15.10.2013 07:12, schrieb Naveen Krishna Chatradhi:
The Exynos5 i2c driver does not handle NACKs properly. This change:
- fixes the NACK processing problem (do not continue transaction if
address cycle was
Hello Naveen,
Am 15.10.2013 07:12, schrieb Naveen Krishna Chatradhi:
The Exynos5 i2c driver does not handle NACKs properly. This change:
- fixes the NACK processing problem (do not continue transaction if
address cycle was NACKed)
- eliminates a fair amount of duplicate code
Hi Eduardo,
On 14-10-2013 15:13, Eduardo Valentin wrote:
On 14-10-2013 01:52, Zhang, Rui wrote:
Eduardo,
What's your opinion on this patch set?
BTW, please send me all the urgent fixes for thermal soc drivers
that
you think should go to 3.12.
I will be sending these + one
Hi Kukjin,
The TMU device tree node definition for Exynos4x12 family of SoCs.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
Reviewed-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
Changes for v2:
- None
Hi Kukjin,
This patch enables support for TMU at Exynos4412 based Trats2 board.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
Reviewed-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
Changes for v2:
- None
On Tue, Oct 15, 2013 at 3:23 PM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
For Exynos4 and Exynos5 SoCs from Samsung the i2c clock is based
on a fixed 66 MHz peripheral clock, and therefore is completely
independent of the cpu frequency.
Thus, registering for a CPU freq notifier is
Hi Seung-Woo,
On 14/10/13 06:43, Seung-Woo Kim wrote:
For hdr parse error, it can return false without any assignments
which cause following build warning.
drivers/media/platform/s5p-jpeg/jpeg-core.c: In function 's5p_jpeg_parse_hdr':
drivers/media/platform/s5p-jpeg/jpeg-core.c:432:
This patchset adds clock entries to gsc power domain and gsc device
nodes to DT file
Note: This pathcset is rebased and tested on Kgene's for-next branch.
Leela Krishna Amudala (2):
ARM: dts: Exynos5420: add clock entries to gsc power domain
ARM: dts: Exynos5420: Add dt support for gscaler
Adds G-Scaler devices to the DT device list
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index
On 14 October 2013 21:31, Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com wrote:
On Monday, October 14, 2013 10:18:03 AM Eduardo Valentin wrote:
On 11-10-2013 11:57, Bartlomiej Zolnierkiewicz wrote:
Hi,
On Friday, October 11, 2013 11:10:38 AM Eduardo Valentin wrote:
Hi Naveen,
On 15-10-2013 02:27, Lukasz Majewski wrote:
Hi Kukjin,
The TMU device tree node definition for Exynos4x12 family of SoCs.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
Reviewed-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
BTW,
Hi,
On Mon, Oct 14, 2013 at 11:56 PM, Kyungmin Park kmp...@infradead.org wrote:
On Tue, Oct 15, 2013 at 3:23 PM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
For Exynos4 and Exynos5 SoCs from Samsung the i2c clock is based
on a fixed 66 MHz peripheral clock, and therefore is
This patch restores the ability to receive wake-up events from internal
GIC interrupts, e.g. RTC tick or alarm interrupts.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/include/mach/pm-core.h | 1 -
On Mon, Oct 14, 2013 at 9:08 PM, Doug Anderson diand...@chromium.org wrote:
Tomasz,
On Fri, Oct 11, 2013 at 7:06 PM, Tomasz Figa t.f...@samsung.com wrote:
Well, it's some kind of difference indeed. However, how often can
a frequency transition happen?
I believe that ondemand allows minimum
This patch adds mout_aclk333_sub mux clock and updates gate clocks from
MFC domain to have it as their parent as specified in SoC documentation.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/clk/samsung/clk-exynos5250.c | 8
This patch renames all mux clocks to start with mout_ prefix and all div
clocks to start with div_ prefix for consistency with other clocks
already defined this way.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
This is a clean-up series for the Exynos 5250 clock driver. It consists
mostly of stylistical fixes and also changes making the clock tree defined
by the driver represent more closely the real clock tree of the SoC.
On Exynos 5250 based Arndale board:
Tested-by: Tomasz Figa t.f...@samsung.com
This patch adds mux_aclk_200_disp1_sub mux clock, which according to SoC
documentation is the correct parent of DISP1 gate clocks.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/clk/samsung/clk-exynos5250.c | 14 --
1
This patch updates mux parent arrays with unpopulated mux inputs, as all
inputs need to be specified in parent arrays passed to
clk_register_mux(), otherwise clk_set_parent() can generate out of bound
accesses to the array.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin
This patch adds mout_aclk266_gscl_sub mux clock and adjusts definitions
of GSCL domain gate clocks to use it as their parent, as specified in
SoC documentation.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
This patch reorders clock definitions, so they are sorted by register
addresses and bitfield shifts. When at it, blank lines are added to
separate definitions of clocks from different registers.
Overall this should make the driver more readable and reduce the number
of potential conflicts when
According to SoC documentation, input 5 of mout_audio muxes is connected
to xxti (named fin_pll in the driver). This patch corrects defined
parent arrays to match SoC documentation.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Hi Leela,
On Tuesday 15 of October 2013 16:50:53 Leela Krishna Amudala wrote:
Add clock nodes for oscillator clock, input clocks and parents of input
clocks to gsc power domain so that we can set/restore the input
clocks while powering on and powering off a domain.
Signed-off-by: Prathyush
Hi Leela,
On Tuesday 15 of October 2013 16:50:54 Leela Krishna Amudala wrote:
Adds G-Scaler devices to the DT device list
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 20
1 file changed, 20 insertions(+)
diff
The following changes since commit 272b98c6455f00884f0350f775c5342358ebb73f:
Linux 3.12-rc1 (2013-09-16 16:17:51 -0400)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
tags/samsung-fixes-v2
for you to fetch changes up to
On 10/14/13 03:11, Heiko Stübner wrote:
Am Sonntag, 13. Oktober 2013, 16:56:42 schrieb Vinod Koul:
On Fri, Oct 11, 2013 at 10:59:19AM +0200, Heiko Stübner wrote:
[I messed up the linux-arm-kernel list address yesterday, so I resend it
with a fixed address, sorry for the noise]
When Olof
без зубрежки так же тягомотных упражнений http://www.talkiiz.kz/tmp/iswjj.htm
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On Exynos5250, the FALL interrupt related en, status and clear bits are
available at an offset of
16 on INTEN, INTSTAT registers and at an offset of
12 on INTCLEAR register.
On Exynos5420, the FALL interrupt related en, status and clear bits are
available at an offset of
16 on INTEN, INTSTAT and
On Exynos5440 and Exynos5420 there are registers common
across the TMU channels.
To support that, we introduced a ADDRESS_MULTIPLE flag in the
driver and the 2nd set of register base and size are provided
in the reg property of the node.
As per Amit's suggestion, this patch changes the
This patch adds the neccessary register changes and arch information
to support Exynos5420 SoCs
Exynos5420 has 5 TMU channels one for each CPU 0, 1, 2 and 3 and GPU
Also updated the Documentation at
Documentation/devicetree/bindings/thermal/exynos-thermal.txt
Note: The platform data structure
On Wed, Oct 16, 2013 at 07:32:20AM +0900, Kukjin Kim wrote:
On 10/14/13 03:11, Heiko Stübner wrote:
Am Sonntag, 13. Oktober 2013, 16:56:42 schrieb Vinod Koul:
On Fri, Oct 11, 2013 at 10:59:19AM +0200, Heiko Stübner wrote:
[I messed up the linux-arm-kernel list address yesterday, so I resend it
On Fri, Oct 11, 2013 at 11:01:04AM +0200, Heiko Stübner wrote:
The earliest variants of the dma controller did not contain support for
controlling clocks.
Acked-by: Vinod Koul vinod.k...@intel.com
Signed-off-by: Heiko Stuebner he...@sntech.de
---
drivers/dma/s3c24xx-dma.c | 10
Adds support for High Speed I2C driver found in Exynos5 and
later SoCs from Samsung.
Driver only supports Device Tree method.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Signed-off-by: Taekgyun Ko taeggyun...@samsung.com
Reviewed-by: Simon Glass s...@google.com
Tested-by:
On 26 September 2013 14:36, Chander Kashyap chander.kash...@linaro.org wrote:
Fixes cpll control and lock register offset values for Exynos5420 SoC.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Acked-by: Kukjin Kim kgene@samsung.com
---
Changes Since v1:
- Fixed
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