Tushar Behera wrote:
No need to maintain Exynos specific codes for legacy files as they
are not compiled for Exynos platforms. Remove any reference to Exynos
from those files.
Tushar Behera (3):
ARM: SAMSUNG: Remove Exynos specific code from devs.c
ARM: SAMSUNG: Remove Exynos
Tushar Behera wrote:
plat-samsung/include/plat/regs-serial.h only includes linux/serial_s3c.h.
Including linux/serial_s3c.h directly would reduce platform dependency
while working towards multi-platform kernel.
Tested on top of Kukjin's for-next branch.
Commit 8109c47 Merge branch
Tushar Behera wrote:
plat/devs.h is not required in this file.
Signed-off-by: Tushar Behera tushar.beh...@linaro.org
---
Based on top of next-20131224.
arch/arm/mach-exynos/pm_domains.c |2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/mach-exynos/pm_domains.c
Heiko Stübner wrote:
Commit 48cf83dc12f2 (ARM: samsung: remove unused tick.h) removed some
occurences of tick.h. tick.h itself and s3c24xx_ostimer_pending was only
used by the old timer driver and is not used anymore.
Therefore remove the last 3 occurences.
Signed-off-by: Heiko Stuebner
Heiko Stübner wrote:
Next try, this time with less time between submissions.
Tested on both non-dt and dt s3c2416.
Changes since v3:
- address comments from Tomasz Figa (binding documentation, etc)
- prevent conflicts with unconverted s3c24xx socs
Changes since v2
- address comments
On 08/01/14 05:44, Sachin Kamat wrote:
Hi Sylwester,
On 7 January 2014 17:33, Sylwester Nawrocki s.nawro...@samsung.com wrote:
Ensure clk-kref is dereferenced only when clk is not NULL.
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
Hi Sachin,
please try if this patch
Hi Thomas,
The Exynos4210 specific cpufreq driver performs read/write operations
of clock controller registers bypassing the Exynos common clock
framework driver. This could lead to potential issues if CCF and
cpufreq driver modify the clock registers independently of each other.
In addition
Hi Thomas,
In order to use the cpufreq-cpu0 driver on Exynos4 based platforms,
statically add the platform device for cpufreq-cpu0 platform driver.
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
arch/arm/mach-exynos/mach-exynos4-dt.c |6 ++
1 files changed, 6
Hi Thomas,
Add CPU nodes for Exynos4210 SoC and also properties required by the
cpufreq-cpu0 driver.
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
arch/arm/boot/dts/exynos4210-origen.dts |6 ++
arch/arm/boot/dts/exynos4210-trats.dts |6 ++
Hi Thomas,
I've investigated the topic for a while, so if you don't mind I will
share my thoughts :-)
The patch series removes the use of Exynos4210 specific cpufreq driver
and enables to use the cpufreq-cpu0 driver for Exynos4210 based
platforms. This is being done for few reasons.
(a)
SSS module on Exynos4210, Exynos5250 and Exynos5420 SoCs has added
features to the one on S5PV210. However minor changes to the s5p-sss.c
driver are required to support SSS modules on Exynos4 and 5 SoCs.
This patch set
1. Adds device tree support to the s5p-sss.c driver and Documentation
2. Adds
From: Naveen Krishna Ch ch.nav...@samsung.com
This patch uses the platform_get_irq() instead of the
platform_get_irq_byname(). Making feeder control interrupt
as resource 0 and hash interrupt as 1.
reasons for this change.
1. Cannot find any Arch which is currently using this driver
2. Samsung
This patch adds new compatible and variant struct to support the SSS
module on Exynos4 (Exynos4210), Exynos5 (Exynos5420 and Exynos5250)
for which
1. AES register are at an offset of 0x200 and
2. hash interrupt is not available
Signed-off-by: Naveen Krishna Ch ch.nav...@samsung.com
CC: Herbert Xu
This patch adds device tree support to the s5p-sss.c crypto driver.
Also, Documentation under devicetree/bindings added.
Signed-off-by: Naveen Krishna Ch ch.nav...@samsung.com
CC: Herbert Xu herb...@gondor.apana.org.au
CC: David S. Miller da...@davemloft.net
CC: Vladimir Zapolskiy
This patch adds gating clock for SSS(Security SubSystem)
module on Exynos5250.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
Changes since v2:
This is a new change to support SSS on Exynos5250
drivers/clk/samsung/clk-exynos5250.c |3 ++-
1 file changed, 2 insertions(+),
From: Naveen Krishna Ch ch.nav...@samsung.com
This patch modifies Kconfig such that ARCH_EXYNOS SoCs
which includes (Exynos4210, Exynos5250 and Exynos5420)
can also select Samsung SSS(Security SubSystem) driver.
Signed-off-by: Naveen Krishna Ch ch.nav...@samsung.com
CC: Herbert Xu
This patch adds code to validate iv buffer before trying to
memcpy the contents
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
Changes since v2:
None
drivers/crypto/s5p-sss.c |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/crypto/s5p-sss.c
This patch adds the device tree node for SSS module
found on Exynos5420 and Exynos5250
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
TO: linux-samsung-soc@vger.kernel.org
CC: Kukjin Kim kgene@samsung.com
CC: linux-cry...@vger.kernel.org
---
Changes since v2:
1. Added device
This patch set adds use of clk_prepare/clk_unprepare as
required by generic clock framework.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
Changes since v2:
New change to fix a WARN_ON during the bootup
drivers/crypto/s5p-sss.c |6 +++---
1 file changed, 3 insertions(+),
Hi Lukasz,
On Fri, Jan 10, 2014 at 4:02 PM, Lukasz Majewski l.majew...@samsung.com wrote:
Hi Thomas,
I've investigated the topic for a while, so if you don't mind I will
share my thoughts :-)
Sure. Thanks for having a look at this patch series.
The patch series removes the use of
Hi Thomas,
Add a new clock provider for ARM clock domain. This clock provider
is composed of multiple components which include mux_core, div_core,
div_core2, div_corem0, div_corem1, div_periph, div_atb, div_pclk_dbg,
div_copy and div_hpm. This composition of mutiple components into
a single
Hi Thomas,
On some platforms such as the Samsung Exynos, changing the frequency
of the CPU clock requires changing the frequency of the PLL that is
supplying the CPU clock. To change the frequency of the PLL, the CPU
clock is temporarily reparented to another parent clock.
Please look into
Hi Thomas,
The CPU clock provider supplies the clock to the CPU clock domain. The
composition and organization of the CPU clock provider could vary
among Exynos SoCs. A CPU clock provider can be composed of clock mux,
dividers and gates. This patch defines a new clock type for CPU clock
Hi Lukasz,
On Fri, Jan 10, 2014 at 4:02 PM, Lukasz Majewski l.majew...@samsung.com wrote:
Hi Thomas,
Add CPU nodes for Exynos4210 SoC and also properties required by the
cpufreq-cpu0 driver.
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
arch/arm/boot/dts/exynos4210-origen.dts
Hi Lukasz,
On Fri, Jan 10, 2014 at 5:34 PM, Lukasz Majewski l.majew...@samsung.com wrote:
Hi Thomas,
The CPU clock provider supplies the clock to the CPU clock domain. The
composition and organization of the CPU clock provider could vary
among Exynos SoCs. A CPU clock provider can be
Hi Lukasz,
On Fri, Jan 10, 2014 at 5:34 PM, Lukasz Majewski l.majew...@samsung.com wrote:
Hi Thomas,
Add a new clock provider for ARM clock domain. This clock provider
is composed of multiple components which include mux_core, div_core,
div_core2, div_corem0, div_corem1, div_periph, div_atb,
Hi Thomas,
Hi Lukasz,
On Fri, Jan 10, 2014 at 5:34 PM, Lukasz Majewski
l.majew...@samsung.com wrote:
Hi Thomas,
The CPU clock provider supplies the clock to the CPU clock domain.
The composition and organization of the CPU clock provider could
vary among Exynos SoCs. A CPU clock
Hi Naveen,
On 10.01.2014 07:07, Naveen Krishna Ch wrote:
Hello Tomasz,
Thanks for time and review comments they are really helping me a lot
in getting the patches merged.
Secondly, accept my apologies for not giving proper writeup of why i
din't address
few of your comments on v1 of this
Hi Thomas,
Hi Lukasz,
On Fri, Jan 10, 2014 at 5:34 PM, Lukasz Majewski
l.majew...@samsung.com wrote:
Hi Thomas,
Add a new clock provider for ARM clock domain. This clock provider
is composed of multiple components which include mux_core,
div_core, div_core2, div_corem0, div_corem1,
Hi Naveen,
On 10.01.2014 12:41, Naveen Krishna Chatradhi wrote:
From: Naveen Krishna Ch ch.nav...@samsung.com
This patch uses the platform_get_irq() instead of the
platform_get_irq_byname(). Making feeder control interrupt
as resource 0 and hash interrupt as 1.
reasons for this change.
1.
Hi Naveen,
On 10.01.2014 12:43, Naveen Krishna Chatradhi wrote:
From: Naveen Krishna Ch ch.nav...@samsung.com
This patch modifies Kconfig such that ARCH_EXYNOS SoCs
which includes (Exynos4210, Exynos5250 and Exynos5420)
can also select Samsung SSS(Security SubSystem) driver.
Signed-off-by:
Hi Naveen,
Please see my comments inline.
On 10.01.2014 12:42, Naveen Krishna Chatradhi wrote:
This patch adds new compatible and variant struct to support the SSS
module on Exynos4 (Exynos4210), Exynos5 (Exynos5420 and Exynos5250)
for which
1. AES register are at an offset of 0x200 and
2.
Hi Naveen,
On 10.01.2014 12:44, Naveen Krishna Chatradhi wrote:
This patch adds the device tree node for SSS module
found on Exynos5420 and Exynos5250
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
TO: linux-samsung-soc@vger.kernel.org
CC: Kukjin Kim kgene@samsung.com
CC:
Hi Naveen,
On 10.01.2014 12:45, Naveen Krishna Chatradhi wrote:
This patch set adds use of clk_prepare/clk_unprepare as
required by generic clock framework.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
Changes since v2:
New change to fix a WARN_ON during the bootup
Hi Naveen,
On 10.01.2014 12:45, Naveen Krishna Chatradhi wrote:
This patch adds code to validate iv buffer before trying to
memcpy the contents
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
Changes since v2:
None
drivers/crypto/s5p-sss.c |5 +++--
1 file changed, 3
Hi,
On 09.01.2014 13:52, Bartlomiej Zolnierkiewicz wrote:
added linux-samsung-soc to cc:,
it is a better suited list for this question
On Thursday, January 09, 2014 10:30:56 AM Mj Embd wrote:
I am a bit confused on the interrupt number for CNTVIRQ..CNTHPIRQ. Can
you please help here.
As per
Hi,
On 08.01.2014 17:21, Doug Anderson wrote:
WIll,
Thanks for your comments!
On Wed, Jan 8, 2014 at 6:35 AM, Will Deacon will.dea...@arm.com wrote:
On Wed, Jan 08, 2014 at 01:33:11PM +, Vivek Gautam wrote:
The erratum-773769 occurs on Arm Coretex-A15 (rev r2p0),
when L2 Data Ram
Hello.
On 01/10/2014 06:04 AM, Pankaj Dubey wrote:
If used 64 bit compiler GCC warns that:
drivers/net/ethernet/smsc/smc91x.c:1897:7:
warning: cast from pointer to integer of different
size [-Wpointer-to-int-cast]
This patch fixes this by changing typecase from unsigned int to unsigned
On Fri, Jan 10, 2014 at 6:55 PM, Lukasz Majewski l.majew...@samsung.com wrote:
Hi Thomas,
Hi Lukasz,
On Fri, Jan 10, 2014 at 5:34 PM, Lukasz Majewski
l.majew...@samsung.com wrote:
Hi Thomas,
The CPU clock provider supplies the clock to the CPU clock domain.
The composition and
On Fri, Jan 10, 2014 at 7:48 PM, Lukasz Majewski l.majew...@samsung.com wrote:
Hi Thomas,
Hi Lukasz,
On Fri, Jan 10, 2014 at 5:34 PM, Lukasz Majewski
l.majew...@samsung.com wrote:
Hi Thomas,
Add a new clock provider for ARM clock domain. This clock provider
is composed of multiple
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