Hello Chanwoo,
On 18 June 2014 07:51, Chanwoo Choi cw00.c...@samsung.com wrote:
This patch add DT binding documentation for Exynos3250 ADC IP. Exynos3250 has
special clock ('sclk_tsadc') for ADC which provide clock to internal ADC.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by:
On 06/17/2014 07:49 AM, Rahul Sharma wrote:
Hi All,
Please review this patch.
Regards,
Rahul Sharma
On 9 June 2014 16:58, Rahul Sharma rahul.sha...@samsung.com wrote:
Display domain is removed due to instability issues. Explaining
the problem below:
exynos_init_late triggers the
Hi Naveen,
On 06/18/2014 03:12 PM, Naveen Krishna Ch wrote:
Hello Chanwoo,
On 18 June 2014 07:51, Chanwoo Choi cw00.c...@samsung.com wrote:
This patch add DT binding documentation for Exynos3250 ADC IP. Exynos3250 has
special clock ('sclk_tsadc') for ADC which provide clock to internal ADC.
Hi Andrej,
On 18 June 2014 11:46, Andrzej Hajda a.ha...@samsung.com wrote:
On 06/17/2014 07:49 AM, Rahul Sharma wrote:
Hi All,
Please review this patch.
Regards,
Rahul Sharma
On 9 June 2014 16:58, Rahul Sharma rahul.sha...@samsung.com wrote:
Display domain is removed due to instability
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
When communicating with the EC, the cmd_xfer() function should return the
number of bytes it received from the EC, or negative on error.
Signed-off-by: Bill Richardson wfric...@chromium.org
On Tue, 17 Jun 2014, Doug Anderson wrote:
Simon,
On Tue, Jun 17, 2014 at 8:43 PM, Simon Glass s...@chromium.org wrote:
diff --git a/drivers/mfd/cros_ec_spi.c b/drivers/mfd/cros_ec_spi.c
index 09ca789..4d34f1c 100644
--- a/drivers/mfd/cros_ec_spi.c
+++ b/drivers/mfd/cros_ec_spi.c
@@
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
struct cros_ec_device has a superfluous name field. We can get all the
debugging info we need from the existing ec_name and phys_name fields, so
let's take out the extra field.
Signed-off-by: Bill
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
This is some internal structure reorganization / renaming to prepare
for future patches that will add a userspace API to cros_ec. There
should be no visible changes.
Signed-off-by: Bill Richardson
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Simon Glass s...@chromium.org
Some commands take a while to execute. Use -EAGAIN to signal this to the
caller.
Signed-off-by: Simon Glass s...@chromium.org
Signed-off-by: Doug Anderson diand...@chromium.org
---
drivers/mfd/cros_ec_spi.c
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
The members of struct cros_ec_device were improperly commented, and
intermixed the private and public sections. This is just cleanup to make it
more obvious what goes with what.
[dianders: left lock in
On 17 June 2014 20:55, Thomas Abraham thomas...@samsung.com wrote:
Changes since v5:
- Configuration data for cpu clock block is embedded with the code. The cpu
clock
logic can later to extended to obtain this data from DT.
- Excluded the support for Exynos4x12 SoC since the work on boost
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
The lower-level driver may want to provide its own buffers. If so,
there's no need to allocate new ones. This already happens to work
just fine (since we check for size of 0 and use devm allocation), but
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
Preparing the way for the LPC device, which is just a plaform_device without
interrupts.
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Doug Anderson diand...@chromium.org
---
Hi Chanwoo,
On 18.06.2014 04:20, Chanwoo Choi wrote:
This patchset add 'exynos_adc_ops' structure which includes some functions
to control ADC operation according to ADC version (v1 or v2).
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
This comment was incorrect, so update it.
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Simon Glass s...@chromium.org
How many people did it take to write this patch? ;)
Acked-by:
On Tue, 17 Jun 2014, Tomasz Figa wrote:
On 17.06.2014 17:42, Arnd Bergmann wrote:
On Tuesday 17 June 2014 17:32:44 Tomasz Figa wrote:
Currently a syscon entity can be only registered directly through a
platform device that binds to a dedicated driver. However in certain use
cases it is
+config MFD_MAX77802
+ tristate Maxim Integrated MAX77802 PMIC Support
+ depends on I2C=y
+ select MFD_CORE
+ select REGMAP_I2C
+ select REGMAP_IRQ
+ select IRQ_DOMAIN
+ help
+Say yes here to support for Maxim Integrated MAX77802.
+This is a Power Management IC
Hi Chanwoo,
On 18.06.2014 04:21, Chanwoo Choi wrote:
This patch add DT binding documentation for Exynos3250 ADC IP. Exynos3250 has
special clock ('sclk_tsadc') for ADC which provide clock to internal ADC.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park
Hi Chanwoo,
On 18.06.2014 04:21, Chanwoo Choi wrote:
This patchset fix wrong compatible string for Exynos3250 ADC. Exynos3250 SoC
need to control only special clock for ADC. Exynos SoC except for Exynos3250
has not included special clock for ADC. The exynos ADC driver can control
special
This patch add support for a new clock type for Exynos3250 CPU clock provider
and modify little difference of DIV_CPU0 between Exynos4 and Exynos3250.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/clk/samsung/clk-cpu.c | 31
This patch add cpu clock table (CPU clock and voltage) to support generic
cpufreq-cpu0 driver for Exynos3250.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos3250.dtsi | 15 +++
1 file changed, 15
This patchset use cpufreq-cpu0 driver to support Exynos3250 cpufreq. So, this
patchset is based on following patchset[1] by Thomas Abraham.
[1] http://www.spinics.net/lists/arm-kernel/msg339392.html
Changes from v1:
- Rebased on new patchset[1] by Thomas Abraham
- Modify clk-cpu.c to support
Hi Tomasz,
On 06/18/2014 05:37 PM, Tomasz Figa wrote:
Hi Chanwoo,
On 18.06.2014 04:21, Chanwoo Choi wrote:
This patchset fix wrong compatible string for Exynos3250 ADC. Exynos3250 SoC
need to control only special clock for ADC. Exynos SoC except for Exynos3250
has not included special
Hi Tomasz,
On 06/18/2014 05:35 PM, Tomasz Figa wrote:
Hi Chanwoo,
On 18.06.2014 04:21, Chanwoo Choi wrote:
This patch add DT binding documentation for Exynos3250 ADC IP. Exynos3250 has
special clock ('sclk_tsadc') for ADC which provide clock to internal ADC.
Signed-off-by: Chanwoo Choi
From: Prathyush K prathyus...@samsung.com
Set the device as wakeup capable and register the wakeup source.
Note: Though it makes more sense to have the SPI framework do this,
(either via device tree or by board_info)
this change is as per an existing mail chain:
Hello Doug,
On 06/17/2014 10:57 PM, Doug Anderson wrote:
Javier,
On Mon, Jun 16, 2014 at 11:02 AM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
@@ -127,15 +175,48 @@ static int max77686_i2c_probe(struct i2c_client *i2c,
}
i2c_set_clientdata(max77686-rtc,
On Tue, Jun 17, 2014 at 03:50:25PM +0100, Stuart Yoder wrote:
I think for simple masters (i.e. those that have all their StreamIDs
under control of one driver), then setting something during attach (or
add?) based on the DT could work pretty well. The other case is when we
have masters
In the move to this clock driver the hookups for the SPI clocks were
dropped, which causes my system Cragganmore (s3c6410 based) to be unable
to locate any spibus clocks. This patch adds them back in.
When taking the clock from the epll clock (SCLK) the rates on the SPI
bus are incorrect, this
Hi Jaehoon,
I get the below crash on Exyos5250 based Arndale board with linux-next
(20140618) kernel.
Looks like the following patch is causing it
Commit da118915cc72 mmc: dw_mmc: replace disable-wp from slot's
quirk to host's quirk
Reverting the above patch fixes the issue.
The below changes
Hi Mike,
Do you have any comments about this patch?
The patch is needed to provide a clean fix for recently
broken support for HDMI on Exynos4210 SoC in mainline.
Regards,
Tomasz Stanislawski
On 05/01/2014 12:19 AM, Tomasz Figa wrote:
Mike,
On 08.04.2014 17:45, Tomasz Figa wrote:
Hi,
On
On Wed, Jun 18, 2014 at 12:37:16AM +0100, Thierry Reding wrote:
On Tue, Jun 17, 2014 at 01:18:11PM +0100, Will Deacon wrote:
On Tue, Jun 17, 2014 at 12:58:30PM +0100, Thierry Reding wrote:
On Mon, Jun 16, 2014 at 01:57:04PM +0100, Will Deacon wrote:
On Wed, Jun 04, 2014 at 10:12:38PM
Hi Jaehoon,
On Wed, Jun 18, 2014 at 3:50 PM, Jaehoon Chung jh80.ch...@samsung.com wrote:
Hi, Sachin.
Did you check the below patch?
https://patchwork.kernel.org/patch/4346781/
Thanks for the patch. But even with this patch, I continue to get the
aforementioned crash.
I will resend the
On 18 June 2014 13:10, Sachin Kamat sachin.ka...@samsung.com wrote:
Hi Jaehoon,
On Wed, Jun 18, 2014 at 3:50 PM, Jaehoon Chung jh80.ch...@samsung.com wrote:
Hi, Sachin.
Did you check the below patch?
https://patchwork.kernel.org/patch/4346781/
Thanks for the patch. But even with this
Hi Ulf,
On Wed, Jun 18, 2014 at 4:43 PM, Ulf Hansson ulf.hans...@linaro.org wrote:
On 18 June 2014 13:10, Sachin Kamat sachin.ka...@samsung.com wrote:
Hi Jaehoon,
On Wed, Jun 18, 2014 at 3:50 PM, Jaehoon Chung jh80.ch...@samsung.com
wrote:
Hi, Sachin.
Did you check the below patch?
This patch register the exynos mct clocksource as the current timer
as it has constant clock rate. This will generate correct udelay for the
exynos platform and avoid using unnecessary calibrated jiffies. This change
have been tested on exynos5420 based board.
Signed-off-by: Amit Daniel Kachhap
Hi Tim,
I see the below error on Exynos4210 based Origen board with linux-next
(20140618).
Reverting the below commit works fine.
Commit: 8d02e775a6 mmc: sdhci: Use mmc core regulator infrastucture
Any ideas?
***
-- [2.068992] sdhci: Secure Digital Host Controller Interface
Fixes for various issues which are to Power On/Off sequence,
Layer update, waiting for vblank in exynos mixer driver.
This series is based on exynos-drm-fixes branch in Inki dae's tree.
Rahul Sharma (5):
drm/exynos: set power state variable after enabling clocks and power
drm/exynos: stop
Power state variable holds the state of the mixer device.
Power on and power off functions are toggling these variable
at wrong place.
State variable should be changed to true only after Runtime
PM and clocks are enabled. Else it may result to a situation
where mixer registers are accessed with
Mixer should be power gated only after it is gracefully stopped.
The recommended sequence is to Stop the mixer and wait till
it enters to IDLE state before gating the clocks and power to
the mixer.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
drivers/gpu/drm/exynos/exynos_mixer.c |
Allowing only one layer update per vsync can cause issues
while there are update available for both layers. There is
a good amount of possibility to loose updates if we allow
single update per vsync.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
drivers/gpu/drm/exynos/exynos_mixer.c |
Mixer soft reset is a recommended step before reconfiguring
the mixer after power on. Mixer looses the previous state of
DMAs if soft reset. This is the recommendation from the
hardware team.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
drivers/gpu/drm/exynos/exynos_mixer.c |2 ++
mixer_wait_for_vblank function expects that the upcoming
vsync interrupt handler routine will clear the
wait_vsync_event atomic variable.
For this to happen, interrupts should be enabled and
disabled properly.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
On Tuesday 17 June 2014 23:26:22 Tomasz Figa wrote:
On 17.06.2014 17:42, Arnd Bergmann wrote:
This seems like a reasonable way of solving the problem, but I think
there is an even better one that we have about in the past: if we
promote syscon from a platform driver into a a drivers/base/
HDMI probe proceeds with dummy regulators when the regulators
are not provided in DT node or regulator provider has not get
probed or failed to register the regulators.
This patch modify hdmi driver to defer the probe in case the
regulators are not available.
Signed-off-by: Rahul Sharma
Adding regulators for hdmi for peach-pit board.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
Based on for-next branch in Kukjin's tree.
Dependent on:
1) PMIC DT patch at http://www.gossamer-threads.com/lists/linux/kernel/1945703
2) tps65090 DT patch at
On Wed, 18 Jun 2014, Javier Martinez Canillas wrote:
Hello Lee,
Thanks a lot for your feedback.
On 06/17/2014 11:17 PM, Lee Jones wrote:
The MAX77802 PMIC has 10 high-efficiency Buck and 32 Low-dropout
(LDO) regulators. This patch adds support for all these regulators
found on the
On Wed, Jun 18, 2014 at 4:33 AM, Sachin Kamat spk.li...@gmail.com wrote:
Hi Tim,
I see the below error on Exynos4210 based Origen board with linux-next
(20140618).
Reverting the below commit works fine.
Commit: 8d02e775a6 mmc: sdhci: Use mmc core regulator infrastucture
Any ideas
polling the cluster power
status register.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
The patch is based on Linux-next 20140618. It has been tested on an
exynos5420-based chromebook using the /dev/bL_switcher interface as
well as the script provided by Nicolas Pitre and Dave Martin [1
On Wed, 18 Jun 2014, Abhilash Kesavan wrote:
Turning off a cluster when all 4 cores of the cluster are powered off
saves power significantly. Powering off the A15 L2 alone gives around
100mW in savings. Add support for powering off the A15/A7 clusters on
exynos5420/5800.
The patch enables
Ensure the clock provider is not registered until after all its related
clocks were created and are ready to use. Currently there are races
possible and any (of_)clk_get() call right after a clock provider's
clk_init_cb callback call may fail.
Signed-off-by: Sylwester Nawrocki
Hi Tomasz,
On Tue, May 20, 2014 at 5:43 PM, Tomasz Figa t.f...@samsung.com wrote:
Since the block responsible for handling the pin is PMU, not CMU,
a separate driver, that binds to PMU node is required and acquires
all input clocks by standard DT clock look-up. This way we don't need
any
This series adds basic sound support for the Odroid X2/U3 boards.
It relies on specific Exynos Audio Subsystem clock parent and
frequencies being pre-configured.
My full testing git branch has been pushed to:
git://linuxtv.org/snawrocki/samsung.git v3.16-rc1-odroid-sound-clk
It can be browsed
This patch adds the sound subsystem driver for Odroid-X2 and
Odroid-U3 boards. The codec works in I2S master mode; there are
2 separate audio routing paths defined as there are differences
in the signal routing between the X2 and U3 boards, i.e. U3 uses
single jack for headphones and microphone.
Lee,
On Wed, Jun 18, 2014 at 12:55 AM, Lee Jones lee.jo...@linaro.org wrote:
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
Preparing the way for the LPC device, which is just a plaform_device without
interrupts.
Signed-off-by: Bill Richardson
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
.../bindings/sound/samsung,odroidx2-max98090.txt | 35
1 file changed, 35 insertions(+)
create mode 100644
Documentation/devicetree/bindings/sound/samsung,odroidx2-max98090.txt
diff --git
Lee,
On Wed, Jun 18, 2014 at 12:57 AM, Lee Jones lee.jo...@linaro.org wrote:
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
This comment was incorrect, so update it.
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Simon Glass
Lee,
On Wed, Jun 18, 2014 at 12:53 AM, Lee Jones lee.jo...@linaro.org wrote:
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
The lower-level driver may want to provide its own buffers. If so,
there's no need to allocate new ones. This already happens
On Wed, 18 Jun 2014, Doug Anderson wrote:
Lee,
On Wed, Jun 18, 2014 at 12:57 AM, Lee Jones lee.jo...@linaro.org wrote:
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
This comment was incorrect, so update it.
Signed-off-by: Bill Richardson
On Wed, 18 Jun 2014, Doug Anderson wrote:
Lee,
On Wed, Jun 18, 2014 at 12:55 AM, Lee Jones lee.jo...@linaro.org wrote:
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
Preparing the way for the LPC device, which is just a plaform_device
Lee,
On Wed, Jun 18, 2014 at 9:46 AM, Lee Jones lee.jo...@linaro.org wrote:
On Wed, 18 Jun 2014, Doug Anderson wrote:
Lee,
On Wed, Jun 18, 2014 at 12:55 AM, Lee Jones lee.jo...@linaro.org wrote:
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
From: Bill Richardson wfric...@chromium.org
The members of struct cros_ec_device were improperly commented, and
intermixed the private and public sections. This is just cleanup to make it
more obvious what goes with what.
[dianders: left lock in the structure but gave it the name that will
This is a batch of cleanup patches picked from the ChromeOS 3.8 kernel
tree and applied to ToT. Most of these patches were authored by Bill
Richardson (CCed). Where appropriate I've squashed patches together,
though I have erred on the side of keeping patches logically distinct
rather than
From: Bill Richardson wfric...@chromium.org
When communicating with the EC, the cmd_xfer() function should return the
number of bytes it received from the EC, or negative on error.
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Doug Anderson diand...@chromium.org
Acked-by:
From: Andrew Bresticker abres...@chromium.org
If we receive EC interrupts after the cros_ec driver has probed, but
before the cros_ec_keyb driver has probed, the cros_ec IRQ handler
will not run the cros_ec_keyb notifier and the EC will leave the IRQ
line asserted. The cros_ec IRQ handler then
From: Bill Richardson wfric...@chromium.org
Just because the host was able to talk to the EC doesn't mean that the EC
was happy with what it was told. Errors in communincation are not the same
as error messages from the EC itself.
This change lets the EC report its errors separately.
[dianders:
From: Simon Glass s...@chromium.org
Some commands take a while to execute. Use -EAGAIN to signal this to the
caller.
Signed-off-by: Simon Glass s...@chromium.org
Signed-off-by: Doug Anderson diand...@chromium.org
Acked-by: Lee Jones lee.jo...@linaro.org
---
Changes in v2: None
From: Bill Richardson wfric...@chromium.org
The lower-level driver may want to provide its own buffers. If so,
there's no need to allocate new ones. This already happens to work
just fine (since we check for size of 0 and use devm allocation), but
it's good to document it.
[dianders: Resolved
From: Bill Richardson wfric...@chromium.org
This is some internal structure reorganization / renaming to prepare
for future patches that will add a userspace API to cros_ec. There
should be no visible changes.
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Doug Anderson
From: Bill Richardson wfric...@chromium.org
Remove the three wrapper functions that talk to the EC without passing all
the desired arguments and just use the underlying communication function
that passes everything in a struct intead.
This is internal code refactoring only. Nothing should
From: Bill Richardson wfric...@chromium.org
This comment was incorrect, so update it.
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Simon Glass s...@chromium.org
Signed-off-by: Doug Anderson diand...@chromium.org
Acked-by: Lee Jones lee.jo...@linaro.org
---
Changes in v2:
From: Bill Richardson wfric...@chromium.org
struct cros_ec_device has a superfluous name field. We can get all the
debugging info we need from the existing ec_name and phys_name fields, so
let's take out the extra field.
The printout also has sufficient info in it without explicitly adding
the
Amit,
Thanks for posting!
On Wed, Jun 18, 2014 at 4:31 AM, Amit Daniel Kachhap
amit.dan...@samsung.com wrote:
This patch register the exynos mct clocksource as the current timer
as it has constant clock rate. This will generate correct udelay for the
exynos platform and avoid using
Hi,
On 06/18/2014 02:57 PM, Arnd Bergmann wrote:
On Tuesday 17 June 2014 23:26:22 Tomasz Figa wrote:
On 17.06.2014 17:42, Arnd Bergmann wrote:
This seems like a reasonable way of solving the problem, but I think
there is an even better one that we have about in the past: if we
promote syscon
pwm-cells should be 3. Third cell is optional PWM flags. And This flag
supported by this binding is PWM_POLARITY_INVERTED.
Signed-off-by: Jaewon Kim jaewon02@samsung.com
---
Changes in v2:
- Remove unnecessary handle.
arch/arm/boot/dts/exynos4.dtsi |2 +-
1 file changed, 1
Hi, all.
On 06/18/2014 08:22 PM, Sachin Kamat wrote:
Hi Ulf,
On Wed, Jun 18, 2014 at 4:43 PM, Ulf Hansson ulf.hans...@linaro.org wrote:
On 18 June 2014 13:10, Sachin Kamat sachin.ka...@samsung.com wrote:
Hi Jaehoon,
On Wed, Jun 18, 2014 at 3:50 PM, Jaehoon Chung jh80.ch...@samsung.com
On Wed, Jun 18, 2014 at 7:41 PM, Tim Kryger tim.kry...@gmail.com wrote:
On Wed, Jun 18, 2014 at 4:33 AM, Sachin Kamat spk.li...@gmail.com wrote:
Hi Tim,
I see the below error on Exynos4210 based Origen board with linux-next
(20140618).
Reverting the below commit works fine.
Commit
On 2014년 06월 18일 22:42, Rahul Sharma wrote:
HDMI probe proceeds with dummy regulators when the regulators
are not provided in DT node or regulator provider has not get
probed or failed to register the regulators.
This patch modify hdmi driver to defer the probe in case the
regulators are
On Wed, Jun 18, 2014 at 1:21 PM, Viresh Kumar viresh.ku...@linaro.org wrote:
On 17 June 2014 20:55, Thomas Abraham thomas...@samsung.com wrote:
Changes since v5:
- Configuration data for cpu clock block is embedded with the code. The cpu
clock
logic can later to extended to obtain this
On Wed, Jun 18, 2014 at 2:09 PM, Chanwoo Choi cw00.c...@samsung.com wrote:
This patchset use cpufreq-cpu0 driver to support Exynos3250 cpufreq. So, this
patchset is based on following patchset[1] by Thomas Abraham.
[1] http://www.spinics.net/lists/arm-kernel/msg339392.html
Changes from v1:
Hi Thomas,
On 06/19/2014 01:21 PM, Thomas Abraham wrote:
On Wed, Jun 18, 2014 at 2:09 PM, Chanwoo Choi cw00.c...@samsung.com wrote:
This patchset use cpufreq-cpu0 driver to support Exynos3250 cpufreq. So, this
patchset is based on following patchset[1] by Thomas Abraham.
[1]
Thanks Inki,
On 19 June 2014 09:34, Inki Dae inki@samsung.com wrote:
On 2014년 06월 18일 22:42, Rahul Sharma wrote:
HDMI probe proceeds with dummy regulators when the regulators
are not provided in DT node or regulator provider has not get
probed or failed to register the regulators.
This
From: Vincent Palatin vpala...@chromium.org
When the wake-up is triggered by the PMIC RTC, the RTC driver is trying
to read the PMIC interrupt status over I2C and fails because the I2C
controller is not resumed yet.
Let's resume the I2C controller earlier in the _noirq phase
(as other hardwares
The original code for the exynos i2c controller registered for the
noirq variants. However during review feedback it was moved to
SIMPLE_DEV_PM_OPS without anyone noticing that it meant we were no
longer actually noirq (despite functions named
exynos5_i2c_suspend_noirq and
Hi,
On Wed, Jun 18, 2014 at 9:54 PM, Doug Anderson diand...@chromium.org wrote:
From: Vincent Palatin vpala...@chromium.org
When the wake-up is triggered by the PMIC RTC, the RTC driver is trying
to read the PMIC interrupt status over I2C and fails because the I2C
controller is not resumed
Change bit from 2 to 9 for tv (mixer) sysmmu clock.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
Based on Kukjin's for-next branch.
drivers/clk/samsung/clk-exynos5250.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5250.c
85 matches
Mail list logo
