On 27 August 2014 17:52, Doug Anderson diand...@google.com wrote:
Ulf,
On Wed, Aug 27, 2014 at 4:17 AM, Ulf Hansson ulf.hans...@linaro.org wrote:
Now, we've got MMC_CAP_NEEDS_POLL, so dw_mmc will periodically be
called to check the card detect line, but with vmmc and vqmmc off. It
will be
This USB 3.0 PHY controller is also present on Exynos7
platform, so adding the dependency on ARCH_EXYNOS7 for this driver.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/phy/Kconfig |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/Kconfig
Some Exynos SoCs have a separate regulator controlling a
Boost 5V supply which goes as input for VBUS regulator.
So adding a control for the same in driver, to enable
vbus supply on the port.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/phy/phy-exynos5-usbdrd.c | 27
Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the same.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/dwc3/dwc3-exynos.c | 16
1 file changed, 16 insertions(+)
diff --git
Exynos7 SoC has now separate gate control for 125MHz pipe3 phy
clock, as well as 60MHz utmi phy clock.
So get the same and control in the phy-exynos5-usbdrd driver.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
.../devicetree/bindings/phy/samsung-phy.txt|4
The Exynos-DWC3 USB 3.0 DRD controller is also present on
Exynos7 platform, so adding the dependency on ARCH_EXYNOS7
for this driver.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/dwc3/Kconfig |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Adding required support for clocks and additional VBUS regulators
to enable USB 3.0 support on Exynos7 SoC.
This series depends for ACRH_EXYNOS7 support on following series:
[PATCH 00/14] Support 64bit Cortex A57 based Exynos7 SoC
On Thu, Aug 28, 2014 at 12:44:18AM +0200, Javier Martinez Canillas wrote:
On Wed, Aug 27, 2014 at 11:03 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
This is the case for Chromebooks as well but the solution implemented
in the downstream Chrome OS 3.8 kernel is what Tomasz suggested
*sigh*
On 28/08/14 04:56, Olof Johansson wrote:
Hi,
On Wed, Aug 27, 2014 at 03:14:18PM +0530, Naveen Krishna Chatradhi wrote:
Add initial device tree nodes for EXYNOS7 SoC.
Also, includes the dt-binding definitions for clock ids.
Uh, no -- it just adds the dtsi.
Signed-off-by: Naveen Krishna
On pon, 2014-08-18 at 10:34 +0200, Javier Martinez Canillas wrote:
If devm_rtc_device_register() fails a dev_err() is already
reported so there is no need to do an additional dev_info().
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Reviewed-by: Krzysztof Kozlowski
From: Tomasz Figa t.f...@samsung.com
This patch moves Exynos power domain code to use the new generic power
domain look-up framework introduced in previous patches, thus also
allowing the new code to be compiled with CONFIG_ARCH_EXYNOS as well.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Cc:
On 08/28/2014 12:49 AM, Doug Anderson wrote:
Jaehoon,
On Tue, Aug 26, 2014 at 9:47 PM, Jaehoon Chung jh80.ch...@samsung.com wrote:
Doug,
On 08/27/2014 01:14 PM, Doug Anderson wrote:
Jaehoon,
On Tue, Aug 26, 2014 at 8:48 PM, Jaehoon Chung jh80.ch...@samsung.com
wrote:
Hi, Doug,
On
This patch add support for RTC of Exynos3250 SoC. The Exynos3250 needs source
clock(32.768KHz) for RTC block. If source clock of RTC is registerd on clock
list of common clk framework, Exynos RTC drvier have to control this clock.
Clock list for s3c-rtc device:
- rtc : CLK_RTC of
This patch add s3c_rtc_data structure to variant data according to SoC type.
The s3c_rtc_data structure includes some functions to control RTC operation
and specific data dependent on SoC type.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Cc:
This patchset clean up codes to improve readability as following and support
the RTC of Exynos3250 SoC.
- Remove global variables and then use new s3c_rtc structure
- Remove warn message with checking checkpatch script
- Use variant structure according to SoC type instead of legacy enum
This patch remove warning message when checking codeing style with checkpatch
script and reduce un-necessary i2c read operation on s3c_rtc_enable.
WARNING: line over 80 characters
#406: FILE: drivers/rtc/rtc-s3c.c:406:
+ if ((readw(info-base + S3C2410_RTCCON)
This patch define s3c_rtc structure including necessary variables for S3C RTC
device instead of global variables. This patch improves the readability by
removing global variables.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Alessandro
This patch fix wrong compatible string of Exynos3250 RTC (Real-Time Clock) dt
node. The RTC of Exynos3250 must need additional source clock (XrtcXTI).
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Alessandro Zummo a.zu...@towertech.it
Cc:
Command node should contain file reference to distinguish commands
created by different processes.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
Reviewed-by: Joonyoung Shim jy0922.s...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_ipp.c | 5 ++---
drivers/gpu/drm/exynos/exynos_drm_ipp.h |
This set of patches contains various improvement and fixes
for exynos_drm ipp framework.
The patchset is based on exynos-drm-next branch.
IPP framework was tested for regressions on exynos4210-trats target.
In the 2nd version of the series I have included changes proposed by Joonyoung
Shim.
I
Memory shouldn't be freed when hardware is still running.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
Reviewed-by: Joonyoung Shim jy0922.s...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_ipp.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git
Since file pointer is preserved in c_node passing it
as argument in node functions is redundant.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_ipp.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git
The patch removes redundant checks, redundant HW reads
and simplifies code.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
Reviewed-by: Joonyoung Shim jy0922.s...@samsung.com
---
v2:
- fixed bit cleaning operation
---
drivers/gpu/drm/exynos/exynos_drm_fimc.c | 64
Events were removed only during stop command, as a result
there were memory leaks if program prematurely exited.
This patch fixes it.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
Reviewed-by: Joonyoung Shim jy0922.s...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_ipp.c | 155
On file close driver should remove only command nodes created
via this file.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
Reviewed-by: Joonyoung Shim jy0922.s...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_ipp.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git
FIMC in default mode of operation uses only one input buffer,
but the driver used also second buffer, as a result only the
first frame was processed correctly. The patch fixes it.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
Reviewed-by: Joonyoung Shim jy0922.s...@samsung.com
---
Overflow bits shall be cleared by H/W.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
Reviewed-by: Joonyoung Shim jy0922.s...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_fimc.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c
In case of allocation errors some already allocated buffers
were not freed. The patch fixes it.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
Reviewed-by: Joonyoung Shim jy0922.s...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_ipp.c | 67 -
1 file changed,
PM callbacks in ipp core do nothing, so the patch removes it.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
Reviewed-by: Joonyoung Shim jy0922.s...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_ipp.c | 51 -
1 file changed, 51 deletions(-)
diff --git
The patch introduces ipp_clean_mem_nodes function which replaces
redundant code. Additionally memory node function definitions
are moved up to increase its visibility.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
Reviewed-by: Joonyoung Shim jy0922.s...@samsung.com
---
Type casting should be avoided if possible. In case of
work_struct it can be simply replaced by reference to member field.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
Reviewed-by: Joonyoung Shim jy0922.s...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_fimc.c| 2 +-
The nodes should be removed before removing command node.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
Reviewed-by: Joonyoung Shim jy0922.s...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_ipp.c | 5 +
1 file changed, 5 insertions(+)
diff --git
Since command node have file pointer dev field became useless.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
Reviewed-by: Joonyoung Shim jy0922.s...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_ipp.c | 1 -
drivers/gpu/drm/exynos/exynos_drm_ipp.h | 2 --
2 files changed, 3 deletions(-)
All pending works should be canceled prior to its removal.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
Reviewed-by: Joonyoung Shim jy0922.s...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_ipp.c | 5 +
1 file changed, 5 insertions(+)
diff --git
The patch removes redundant H/W activation.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
Reviewed-by: Joonyoung Shim jy0922.s...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_fimc.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git
On Thu, Aug 28, 2014 at 06:34:33AM +0100, Ajay kumar wrote:
On Wed, Aug 27, 2014 at 8:31 PM, Mark Rutland mark.rutl...@arm.com wrote:
On Wed, Aug 27, 2014 at 03:48:27PM +0100, Ajay Kumar wrote:
Add DT nodes for ptn3460 bridge chip and panel.
Add backlight enable pin and backlight power
On pon, 2014-08-18 at 10:34 +0200, Javier Martinez Canillas wrote:
The max77686 mfd driver adds a regmap IRQ chip which creates an
IRQ domain that is used to map the virtual RTC alarm1 interrupt.
The RTC driver assumes that this will always be true since the
PMIC IRQ is a required property
On Thu, Aug 28, 2014 at 2:45 PM, Mark Rutland mark.rutl...@arm.com wrote:
On Thu, Aug 28, 2014 at 06:34:33AM +0100, Ajay kumar wrote:
On Wed, Aug 27, 2014 at 8:31 PM, Mark Rutland mark.rutl...@arm.com wrote:
On Wed, Aug 27, 2014 at 03:48:27PM +0100, Ajay Kumar wrote:
Add DT nodes for ptn3460
Hi,
+ cpus {
+ #address-cells = 2;
+ #size-cells = 0;
Why size-cells=2? Can you not fit a cpuid in 32 bits?
As of commit 72aea393a2e7 (arm64: smp: honour #address-size when parsing
CPU reg property) Linux can handle single-cell cpu node reg entries
where
On Thu, Aug 28, 2014 at 10:34:32AM +0100, Ajay kumar wrote:
On Thu, Aug 28, 2014 at 2:45 PM, Mark Rutland mark.rutl...@arm.com wrote:
On Thu, Aug 28, 2014 at 06:34:33AM +0100, Ajay kumar wrote:
On Wed, Aug 27, 2014 at 8:31 PM, Mark Rutland mark.rutl...@arm.com wrote:
On Wed, Aug 27, 2014
Hello Mark,
On 28/08/2014, at 10:28, Mark Brown broo...@kernel.org wrote:
Yes, AFAIK the bootloader (none of them because Chromebooks use two
chained U-boots) change the regulators default opmode so once is set
to OFF on .disable, that value is preserved on warm reboot. This made
sense with
On Thu, Aug 28, 2014 at 11:59:16AM +0200, Javier Martinez Canillas wrote:
On 28/08/2014, at 10:28, Mark Brown broo...@kernel.org wrote:
Yes, AFAIK the bootloader (none of them because Chromebooks use two
chained U-boots) change the regulators default opmode so once is set
to OFF on
drivers/usb/phy/phy-samsung-usb[2,3] drivers got replaced by
drivers/phy/phy-samsung-usb[2,3] ones and the old common Samsung
USB PHY code is no longer used.
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Reviewed-by: Vivek
On Thu, Aug 28, 2014 at 03:04:32PM +0530, Ajay kumar wrote:
On Thu, Aug 28, 2014 at 2:45 PM, Mark Rutland mark.rutl...@arm.com wrote:
On Thu, Aug 28, 2014 at 06:34:33AM +0100, Ajay kumar wrote:
On Wed, Aug 27, 2014 at 8:31 PM, Mark Rutland mark.rutl...@arm.com wrote:
On Wed, Aug 27, 2014
From: Abhilash Kesavan a.kesa...@samsung.com
The Exynos7 has a DWMMC controller (v2.70a) which is different from
prior versions. This patch adds new compatible strings for exynos7.
This patch also fixes the CLKSEL register offset on exynos7.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
On Thu, Aug 28, 2014 at 02:10:18PM +0100, Thierry Reding wrote:
On Thu, Aug 28, 2014 at 03:04:32PM +0530, Ajay kumar wrote:
On Thu, Aug 28, 2014 at 2:45 PM, Mark Rutland mark.rutl...@arm.com wrote:
On Thu, Aug 28, 2014 at 06:34:33AM +0100, Ajay kumar wrote:
On Wed, Aug 27, 2014 at 8:31
Amit,
On Thu, Jul 31, 2014 at 07:10:58PM +0200, Bartlomiej Zolnierkiewicz wrote:
Hi,
This patch series contains various cleanups for EXYNOS thermal
driver. Overall it decreases driver's LOC by 9%. It is based
on next-20140731 kernel. It should not cause any functionality
changes.
Did
On Thu, Aug 28, 2014 at 01:25:14PM +0900, Chanwoo Choi wrote:
Dear Eduardo,
This patch is wrong. It is my mistake.
Please ignore only this patch because
the offset calculation of 'case 0' is different from 'case 2'.
Do patches 1 - 3 are still correct? Patch 1, from Barlomiej, seams to be
2014-08-28 10:02 GMT+02:00 Vivek Gautam:
This USB 3.0 PHY controller is also present on Exynos7
platform, so adding the dependency on ARCH_EXYNOS7 for this driver.
+++ b/drivers/phy/Kconfig
@@ -186,7 +186,7 @@ config PHY_EXYNOS5250_USB2
config PHY_EXYNOS5_USBDRD
tristate Exynos5
Ulf,
On Thu, Aug 28, 2014 at 12:25 AM, Ulf Hansson ulf.hans...@linaro.org wrote:
On 27 August 2014 17:52, Doug Anderson diand...@google.com wrote:
Ulf,
On Wed, Aug 27, 2014 at 4:17 AM, Ulf Hansson ulf.hans...@linaro.org wrote:
Now, we've got MMC_CAP_NEEDS_POLL, so dw_mmc will periodically be
Jaehoon,
On Thu, Aug 28, 2014 at 1:43 AM, Jaehoon Chung jh80.ch...@samsung.com wrote:
On 08/28/2014 12:49 AM, Doug Anderson wrote:
Jaehoon,
On Tue, Aug 26, 2014 at 9:47 PM, Jaehoon Chung jh80.ch...@samsung.com
wrote:
Doug,
On 08/27/2014 01:14 PM, Doug Anderson wrote:
Jaehoon,
On Tue,
On Thu, Aug 28, 2014 at 2:48 AM, Mark Rutland mark.rutl...@arm.com wrote:
Hi,
+ cpus {
+ #address-cells = 2;
+ #size-cells = 0;
Why size-cells=2? Can you not fit a cpuid in 32 bits?
As of commit 72aea393a2e7 (arm64: smp: honour #address-size when parsing
CPU reg
On Thu, Aug 28, 2014 at 05:28:22PM +0100, Olof Johansson wrote:
On Thu, Aug 28, 2014 at 2:48 AM, Mark Rutland mark.rutl...@arm.com wrote:
Hi,
+ cpus {
+ #address-cells = 2;
+ #size-cells = 0;
Why size-cells=2? Can you not fit a cpuid in 32 bits?
As of
On Thu, Aug 28, 2014 at 10:03 AM, Mark Rutland mark.rutl...@arm.com wrote:
On Thu, Aug 28, 2014 at 05:28:22PM +0100, Olof Johansson wrote:
On Thu, Aug 28, 2014 at 2:48 AM, Mark Rutland mark.rutl...@arm.com wrote:
Hi,
+ cpus {
+ #address-cells = 2;
+ #size-cells
On 28/08/14 18:03, Mark Rutland wrote:
From 67104ad5a56e4c18f9c41f06af028b7561740afd Mon Sep 17 00:00:00 2001
From: Mark Rutland mark.rutl...@arm.com
Date: Thu, 28 Aug 2014 17:41:03 +0100
Subject: [PATCH] Doc: dt: arch_timer: discourage clock-frequency use
The ARM Generic Timer (AKA the
On Thu, Aug 28, 2014 at 06:27:04PM +0100, Marc Zyngier wrote:
On 28/08/14 18:03, Mark Rutland wrote:
From 67104ad5a56e4c18f9c41f06af028b7561740afd Mon Sep 17 00:00:00 2001
From: Mark Rutland mark.rutl...@arm.com
Date: Thu, 28 Aug 2014 17:41:03 +0100
Subject: [PATCH] Doc: dt: arch_timer:
On Thu, Aug 28, 2014 at 12:27 PM, Marc Zyngier marc.zyng...@arm.com wrote:
On 28/08/14 18:03, Mark Rutland wrote:
From 67104ad5a56e4c18f9c41f06af028b7561740afd Mon Sep 17 00:00:00 2001
From: Mark Rutland mark.rutl...@arm.com
Date: Thu, 28 Aug 2014 17:41:03 +0100
Subject: [PATCH] Doc: dt:
On 28/08/14 18:30, Mark Rutland wrote:
On Thu, Aug 28, 2014 at 06:27:04PM +0100, Marc Zyngier wrote:
On 28/08/14 18:03, Mark Rutland wrote:
From 67104ad5a56e4c18f9c41f06af028b7561740afd Mon Sep 17 00:00:00 2001
From: Mark Rutland mark.rutl...@arm.com
Date: Thu, 28 Aug 2014 17:41:03 +0100
On Thu, Aug 28, 2014 at 06:19:00PM +0100, Olof Johansson wrote:
On Thu, Aug 28, 2014 at 10:03 AM, Mark Rutland mark.rutl...@arm.com wrote:
On Thu, Aug 28, 2014 at 05:28:22PM +0100, Olof Johansson wrote:
On Thu, Aug 28, 2014 at 2:48 AM, Mark Rutland mark.rutl...@arm.com wrote:
Hi,
+
On Thu, Aug 28, 2014 at 06:33:13PM +0100, Rob Herring wrote:
On Thu, Aug 28, 2014 at 12:27 PM, Marc Zyngier marc.zyng...@arm.com wrote:
On 28/08/14 18:03, Mark Rutland wrote:
From 67104ad5a56e4c18f9c41f06af028b7561740afd Mon Sep 17 00:00:00 2001
From: Mark Rutland mark.rutl...@arm.com
On Thu, Aug 28, 2014 at 06:37:19PM +0100, Marc Zyngier wrote:
On 28/08/14 18:30, Mark Rutland wrote:
On Thu, Aug 28, 2014 at 06:27:04PM +0100, Marc Zyngier wrote:
On 28/08/14 18:03, Mark Rutland wrote:
From 67104ad5a56e4c18f9c41f06af028b7561740afd Mon Sep 17 00:00:00 2001
From: Mark
Hi Mark,
On Thu, Aug 28, 2014 at 7:39 PM, Mark Rutland mark.rutl...@arm.com wrote:
Ok. If address-cells is kept at 2 the unit address needs to be changed
to 0,0. So one or the other has to be changed.
I'm happy either way.
I'm not sure the rest of the tree had 0, prefixes on all of
On Thu, Aug 28, 2014 at 8:50 AM, Doug Anderson diand...@google.com wrote:
Ulf,
On Thu, Aug 28, 2014 at 12:25 AM, Ulf Hansson ulf.hans...@linaro.org wrote:
On 27 August 2014 17:52, Doug Anderson diand...@google.com wrote:
Ulf,
On Wed, Aug 27, 2014 at 4:17 AM, Ulf Hansson
On Thu, Aug 28, 2014 at 12:19 PM, Olof Johansson o...@lixom.net wrote:
On Thu, Aug 28, 2014 at 10:03 AM, Mark Rutland mark.rutl...@arm.com wrote:
On Thu, Aug 28, 2014 at 05:28:22PM +0100, Olof Johansson wrote:
On Thu, Aug 28, 2014 at 2:48 AM, Mark Rutland mark.rutl...@arm.com wrote:
Hi,
[ added Alan and Greg to cc: ]
Hi,
On Wednesday, August 27, 2014 11:42:25 PM Vivek Gautam wrote:
Hi Baltlomiej,
On Wed, Aug 27, 2014 at 1:22 PM, Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com wrote:
dwc3 driver is using the new Exynos5 SoC series USB DRD PHY driver
On Thu, Aug 28, 2014 at 06:47:00PM +0100, Geert Uytterhoeven wrote:
Hi Mark,
On Thu, Aug 28, 2014 at 7:39 PM, Mark Rutland mark.rutl...@arm.com wrote:
Ok. If address-cells is kept at 2 the unit address needs to be changed
to 0,0. So one or the other has to be changed.
I'm happy
On Thu, Aug 28, 2014 at 09:01:57AM +0100, Vivek Gautam wrote:
Exynos7 SoC has now separate gate control for 125MHz pipe3 phy
clock, as well as 60MHz utmi phy clock.
So get the same and control in the phy-exynos5-usbdrd driver.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
On Thu, Aug 28, 2014 at 09:01:56AM +0100, Vivek Gautam wrote:
Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the same.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/dwc3/dwc3-exynos.c | 16
hi,
On Thu, Aug 28, 2014 at 01:31:58PM +0530, Vivek Gautam wrote:
@@ -457,11 +458,19 @@ static int exynos5_usbdrd_phy_power_on(struct phy *phy)
clk_prepare_enable(phy_drd-ref_clk);
/* Enable VBUS supply */
+ if (phy_drd-vbus_boost) {
+ ret =
On Thu, Aug 28, 2014 at 01:31:59PM +0530, Vivek Gautam wrote:
The Exynos-DWC3 USB 3.0 DRD controller is also present on
Exynos7 platform, so adding the dependency on ARCH_EXYNOS7
for this driver.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/dwc3/Kconfig |2 +-
On Thu, Aug 28, 2014 at 08:11:04PM +0200, Bartlomiej Zolnierkiewicz wrote:
[ added Alan and Greg to cc: ]
Hi,
On Wednesday, August 27, 2014 11:42:25 PM Vivek Gautam wrote:
Hi Baltlomiej,
On Wed, Aug 27, 2014 at 1:22 PM, Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com wrote:
On Thu, Aug 28, 2014 at 10:54 AM, Rob Herring r...@kernel.org wrote:
On Thu, Aug 28, 2014 at 12:19 PM, Olof Johansson o...@lixom.net wrote:
On Thu, Aug 28, 2014 at 10:03 AM, Mark Rutland mark.rutl...@arm.com wrote:
On Thu, Aug 28, 2014 at 05:28:22PM +0100, Olof Johansson wrote:
On Thu, Aug 28,
On Thu, Aug 28, 2014 at 03:23:49PM -0700, Olof Johansson wrote:
On Thu, Aug 28, 2014 at 10:54 AM, Rob Herring r...@kernel.org wrote:
On Thu, Aug 28, 2014 at 12:19 PM, Olof Johansson o...@lixom.net wrote:
On Thu, Aug 28, 2014 at 10:03 AM, Mark Rutland mark.rutl...@arm.com
wrote:
On Thu,
Dear Eduardo,
On 08/28/2014 11:53 PM, Eduardo Valentin wrote:
On Thu, Aug 28, 2014 at 01:25:14PM +0900, Chanwoo Choi wrote:
Dear Eduardo,
This patch is wrong. It is my mistake.
Please ignore only this patch because
the offset calculation of 'case 0' is different from 'case 2'.
Do
Hi,
On Thu, Aug 28, 2014 at 10:50 AM, Sonny Rao sonny...@chromium.org wrote:
On Thu, Aug 28, 2014 at 8:50 AM, Doug Anderson diand...@google.com wrote:
Ulf,
On Thu, Aug 28, 2014 at 12:25 AM, Ulf Hansson ulf.hans...@linaro.org wrote:
On 27 August 2014 17:52, Doug Anderson diand...@google.com
Hello Tomasz,
On 27 August 2014 16:44, Tomasz Figa t.f...@samsung.com wrote:
Hi Naveen,
Please see my comments inline.
On 27.08.2014 11:44, Naveen Krishna Chatradhi wrote:
Add the required pin configuration support to EXYNOS7
[snip]
+/ {
+ /* ALIVE block @1058 */
+
76 matches
Mail list logo
