On Mon, 01 Sep 2014, Arnd Bergmann wrote:
On Monday 01 September 2014 17:04:26 Lee Jones wrote:
On Mon, 01 Sep 2014, Arnd Bergmann wrote:
Maybe I'm misreading the patch, but I don't see how it creates a
migration path. What I want to end up with is infrastructure that
lets anybody
On Tuesday 02 September 2014 09:05:16 Lee Jones wrote:
On Mon, 01 Sep 2014, Arnd Bergmann wrote:
On Monday 01 September 2014 17:04:26 Lee Jones wrote:
On Mon, 01 Sep 2014, Arnd Bergmann wrote:
Maybe I'm misreading the patch, but I don't see how it creates a
migration path. What I
-Original Message-
From: Arnd Bergmann [mailto:a...@arndb.de]
Sent: Tuesday, September 02, 2014 1:45 PM
To: linux-arm-ker...@lists.infradead.org
Cc: Lee Jones; kgene@samsung.com; li...@arm.linux.org.uk;
naus...@samsung.com; Pankaj Dubey; Tomasz Figa;
On Tue, 02 Sep 2014, Arnd Bergmann wrote:
On Tuesday 02 September 2014 09:05:16 Lee Jones wrote:
On Mon, 01 Sep 2014, Arnd Bergmann wrote:
On Monday 01 September 2014 17:04:26 Lee Jones wrote:
On Mon, 01 Sep 2014, Arnd Bergmann wrote:
Maybe I'm misreading the patch, but I don't
Hi,
On Fri, Aug 29, 2014 at 12:18 AM, Mark Rutland mark.rutl...@arm.com wrote:
On Thu, Aug 28, 2014 at 09:01:56AM +0100, Vivek Gautam wrote:
Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the same.
Signed-off-by: Vivek
On Tue, Sep 02, 2014 at 11:39:08AM +0100, Vivek Gautam wrote:
Hi,
On Fri, Aug 29, 2014 at 12:18 AM, Mark Rutland mark.rutl...@arm.com wrote:
On Thu, Aug 28, 2014 at 09:01:56AM +0100, Vivek Gautam wrote:
Exynos7 also has a separate special gate clock going to the IP
apart from the usual
Some PHY controllers may need to calibrate certain
PHY settings after initialization of the controller and
sometimes even after initializing the PHY-consumer too.
Add support for the same in order to let consumers do so in need.
Signed-off-by: vivek Gautam gautam.vi...@samsung.com
---
Adding phy calibrate callback, which facilitates setting certain
PHY settings post initialization of the PHY controller.
Exynos5420 and Exynos5800 have 28nm USB 3.0 DRD PHY for which
the Loss-of-Signal (LOS) Detector Threshold Level as well as
Tx-Vboost-Level should be controlled for Super-Speed
Some quirky PHYs may require to be calibrated post the
hcd initialization.
The USB 3.0 DRD PHY on Exynos5420/5800 systems, coming along
with Synopsys's DWC3 controller, is one such PHY which needs
to be calibrated post xhci's reset at initialization time and
at resume time, to get the controller
The host controller by itself may sometimes need to handle PHY
and/or calibrate some of the PHY settings to get full support out
of the PHY controller. The PHY core provides a calibration
funtionality now to do so.
Therefore, facilitate getting the two possible PHYs, viz.
USB 2.0 type (UTMI+) and
This series is based on Heikki's patches for simpliefied phy lookup table:
[PATCHv3 0/6] phy: simplified phy lookup [1], applied against 'usb-next' branch
alongwith Sergei's patch for adding generic phy support to usb hcd [2].
NOTE: We need to get above dependencies merged first in order to merge
Process should not have access to ipp nodes created by another
process. The patch adds necessary checks.
It also simplifies lookup for command node.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
---
v3:
- added file check from previous commit
- simplified c_node lookup
---
This patch introduces callbacks to route interrupts to or away
from the FIQ signal. It also causes these callbacks to be registered
with the FIQ infrastructure.
This patch enable FIQ support for mach-versatile whilst mach-ep93xx,
mach-netx, mach-s3c64xx and plat-samsung are unmodified (and can
Document the new compatible for clock in DMC (Dynamic Memory
Controller) domain of Exynos3250 Clock Management Unit (CMU).
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
Documentation/devicetree/bindings/clock/exynos3250-clock.txt | 10 +-
1 file changed, 9 insertions(+),
Add clock provider for clocks in DMC domain including EPLL and BPLL. The
DMC clocks are necessary for Exynos3 devfreq driver.
The DMC clock domain uses different address space (0x105C) than
standard clock domain (0x1003 - 0x1005). The difference is huge
enough to add new DT node for
Add CMU (Clock Management Unit) node for DMC (Dynamic Memory Controller)
domain clocks on Exynos3250.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
arch/arm/boot/dts/exynos3250.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
On 27/08/14 15:22, Javier Martinez Canillas wrote:
If there was a BTN_NONE or KEY_UNUSED it would had been better but I think
that making a distinction between these two cases (reserved pin vs GPIO
available but not used) is useful.
Maybe Nick can comment here.
Yes, this is probably useful
On Tue, Sep 2, 2014 at 3:59 AM, Mike Turquette mturque...@linaro.org wrote:
Quoting Thomas Abraham (2014-07-30 01:07:38)
The CPU clock provider supplies the clock to the CPU clock domain. The
composition and organization of the CPU clock provider could vary among
Exynos SoCs. A CPU clock
Hi,
On Tue, Sep 02, 2014 at 04:42:18PM +0530, Vivek Gautam wrote:
Adding phy calibrate callback, which facilitates setting certain
PHY settings post initialization of the PHY controller.
Exynos5420 and Exynos5800 have 28nm USB 3.0 DRD PHY for which
the Loss-of-Signal (LOS) Detector Threshold
On Tue, Sep 02, 2014 at 04:09:08PM +0530, Vivek Gautam wrote:
Hi,
On Fri, Aug 29, 2014 at 12:18 AM, Mark Rutland mark.rutl...@arm.com wrote:
On Thu, Aug 28, 2014 at 09:01:56AM +0100, Vivek Gautam wrote:
Exynos7 also has a separate special gate clock going to the IP
apart from the usual
On Mon, Sep 01, 2014 at 07:05:27AM -0400, edubez...@gmail.com wrote:
Amit
On Mon, Sep 1, 2014 at 6:53 AM, amit daniel kachhap
amit.dan...@samsung.com wrote:
On Thu, Aug 28, 2014 at 8:19 PM, Eduardo Valentin edubez...@gmail.com
wrote:
Amit,
On Thu, Jul 31, 2014 at 07:10:58PM +0200,
Currently a syscon entity can only be registered directly through a
platform device that binds to a dedicated syscon driver. However in
certain cases it is required to bind a device with it's dedicated
driver rather than binding with syscon driver.
For example, certain SoCs (e.g. Exynos) contain
Chanwoo,
On Fri, Aug 29, 2014 at 08:50:41AM +0900, Chanwoo Choi wrote:
Dear Eduardo,
On 08/28/2014 11:53 PM, Eduardo Valentin wrote:
On Thu, Aug 28, 2014 at 01:25:14PM +0900, Chanwoo Choi wrote:
Dear Eduardo,
This patch is wrong. It is my mistake.
Please ignore only this patch
On 02.09.2014 16:42, Pankaj Dubey wrote:
Currently a syscon entity can only be registered directly through a
platform device that binds to a dedicated syscon driver. However in
certain cases it is required to bind a device with it's dedicated
driver rather than binding with syscon driver.
On Tuesday 02 September 2014 20:12:15 Pankaj Dubey wrote:
Currently a syscon entity can only be registered directly through a
platform device that binds to a dedicated syscon driver. However in
certain cases it is required to bind a device with it's dedicated
driver rather than binding with
From: Pankaj Dubey pankaj.du...@samsung.com
Make the config symbols SERIAL_SAMSUNG_UARTS_4 and
SERIAL_SAMSUNG_UARTS depend on SERIAL_SAMSUNG rather than
PLAT_SAMSUNG.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Greg
The following compilation error occurs on 64-bit Exynos7 SoC:
drivers/irqchip/exynos-combiner.c: In function ‘combiner_irq_domain_map’:
drivers/irqchip/exynos-combiner.c:162:2: error: implicit declaration of
function ‘set_irq_flags’ [-Werror=implicit-function-declaration]
set_irq_flags(irq,
Changes since v1:
- Reduced the number of features targetted for the initial platform support.
This patchset supports new Exynos7 Samsung SoC based on Cortex-A57.
Exynos7 is a System-On-Chip (SoC) that is based on 64-bit
ARMv8 RISC processor.
NOTE:
We tested these patches with the
arm64: dts:
PLL145xx is similar to PLL35xx and PLL1460x is almost similar
to PLL46xx with minor differences in bit positions. Hence,
reuse the functions defined for pll_35xx and pll_46xx to
support 145xx and 1460x PLLs respectively.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Tomasz
Add the fields fixed_factor_clks and nr_fixed_factor_clks to
struct exynos_cmu_info to allow registering of fixed factor
clocks as well with exynos_cmu_register_one().
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Tomasz Figa t.f...@samsung.com
Cc: Mike Turquette
While adding clock support for Exynos5260, the infrastructure to
register multiple clock controllers was introduced. Factor out the
support for registering multiple clock controller from Exynos5260
clock code to common samsung clock code so that it can be used by
other Exynos SoC which have
Add initial device tree nodes for EXYNOS7 SoC and board dts file
to support Espresso board based on Exynos7 SoC.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm64/boot/dts/Makefile
From: Alim Akhtar alim.akh...@samsung.com
This patch adds the necessary Kconfig entries to enable
support for the ARMv8 based Exynos7 SoC.
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin
Add initial clock support for Exynos7 SoC which is required
to bring up platforms based on Exynos7.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Tomasz Figa t.f...@samsung.com
Cc: Mike Turquette mturque...@linaro.org
---
.../devicetree/bindings/clock/exynos7-clock.txt|
Tue, 02 Sep 2014 17:20:03 +0200 от Arnd Bergmann a...@arndb.de:
On Tuesday 02 September 2014 20:12:15 Pankaj Dubey wrote:
Currently a syscon entity can only be registered directly through a
platform device that binds to a dedicated syscon driver. However in
certain cases it is required to
On 02/09/14 16:24, Naveen Krishna Chatradhi wrote:
The following compilation error occurs on 64-bit Exynos7 SoC:
drivers/irqchip/exynos-combiner.c: In function ‘combiner_irq_domain_map’:
drivers/irqchip/exynos-combiner.c:162:2: error: implicit declaration of
function ‘set_irq_flags’
Hi Naveen,
On 02.09.2014 17:35, Naveen Krishna Chatradhi wrote:
Changes since v1:
- Reduced the number of features targetted for the initial platform support.
Are you going to reply to my comments to previous version?
Btw. My @samsung.com e-mail is no longer valid. Please use my private
one
On Tuesday 02 September 2014 19:42:52 Alexander Shiyan wrote:
-struct regmap *syscon_regmap_lookup_by_pdevname(const char *s)
-{
- struct device *dev;
- struct syscon *syscon;
-
- dev = driver_find_device(syscon_driver.driver, NULL, (void *)s,
-
Naveen,
On Tue, Sep 02, 2014 at 08:54:52PM +0530, Naveen Krishna Chatradhi wrote:
The following compilation error occurs on 64-bit Exynos7 SoC:
drivers/irqchip/exynos-combiner.c: In function ‘combiner_irq_domain_map’:
drivers/irqchip/exynos-combiner.c:162:2: error: implicit declaration of
HI Thomas,
Thomas Abraham ta.oma...@gmail.com writes:
On Fri, Aug 29, 2014 at 8:33 PM, Kevin Hilman khil...@kernel.org wrote:
Hi Thomas,
On Fri, Aug 29, 2014 at 5:52 AM, Thomas Abraham ta.oma...@gmail.com wrote:
Hi Kevin,
On Wed, Aug 27, 2014 at 3:55 AM, Kevin Hilman khil...@linaro.org
On Tue, Sep 02, 2014 at 02:00:45PM +0100, Daniel Thompson wrote:
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index bda5a91..8821160 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -502,13 +502,17 @@ static void __init gic_init_fiq(struct
On 09/02/2014 09:55 PM, Andrzej Hajda wrote:
Since file pointer is preserved in c_node passing it
as argument in node functions is redundant.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
---
v3:
- file check moved to next patch
---
drivers/gpu/drm/exynos/exynos_drm_ipp.c | 12
Dear Eduardo,
On 08/30/2014 04:28 AM, Eduardo Valentin wrote:
Chanwoo,
On Fri, Aug 29, 2014 at 08:50:41AM +0900, Chanwoo Choi wrote:
Dear Eduardo,
On 08/28/2014 11:53 PM, Eduardo Valentin wrote:
On Thu, Aug 28, 2014 at 01:25:14PM +0900, Chanwoo Choi wrote:
Dear Eduardo,
This patch is
This patchset add the support of TRIMINFO_RELOAD feature for Exynos3250.
But Exynos3250 has two TRIMINFO_CTRL register instead other Exynos has only one
TRIMINFO_CTRL register. So, this patchset support the some Exynos SoC which
has more than one TRIMINF_CTRL.
Also, this patchset fix wrong value
This patch add support for TRIM_RELOAD feature at Exynos3250. The TMu of
Exynos3250 has two TRIMINFO_CON register and must need to set RELOAD bit
before reading TRIMINFO register.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Zhang Rui
On Tue, Sep 2, 2014 at 8:12 PM, Pankaj Dubey pankaj.du...@samsung.com wrote:
Currently a syscon entity can only be registered directly through a
platform device that binds to a dedicated syscon driver. However in
certain cases it is required to bind a device with it's dedicated
driver rather
On Fri, Aug 29, 2014 at 12:58 AM, Felipe Balbi ba...@ti.com wrote:
On Thu, Aug 28, 2014 at 01:31:59PM +0530, Vivek Gautam wrote:
The Exynos-DWC3 USB 3.0 DRD controller is also present on
Exynos7 platform, so adding the dependency on ARCH_EXYNOS7
for this driver.
Signed-off-by: Vivek Gautam
On Tue, Sep 2, 2014 at 8:07 PM, Felipe Balbi ba...@ti.com wrote:
On Mon, Sep 01, 2014 at 01:30:21PM +0530, Vivek Gautam wrote:
On Thu, Aug 28, 2014 at 8:36 PM, Daniele Forsi dfo...@gmail.com wrote:
2014-08-28 10:02 GMT+02:00 Vivek Gautam:
This USB 3.0 PHY controller is also present on
Hi Kevin,
On Wed, Sep 3, 2014 at 1:02 AM, Kevin Hilman khil...@kernel.org wrote:
HI Thomas,
Thomas Abraham ta.oma...@gmail.com writes:
On Fri, Aug 29, 2014 at 8:33 PM, Kevin Hilman khil...@kernel.org wrote:
Hi Thomas,
On Fri, Aug 29, 2014 at 5:52 AM, Thomas Abraham ta.oma...@gmail.com
The following compilation error occurs on 64-bit Exynos7 SoC:
drivers/irqchip/exynos-combiner.c: In function ‘combiner_irq_domain_map’:
drivers/irqchip/exynos-combiner.c:162:2: error: implicit declaration of
function ‘set_irq_flags’ [-Werror=implicit-function-declaration]
set_irq_flags(irq,
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