On Thu, Dec 4, 2014 at 9:09 PM, Ulf Hansson ulf.hans...@linaro.org wrote:
On 1 December 2014 at 12:41, Amit Daniel Kachhap
amit.dan...@samsung.com wrote:
This function looks up a PM domain form the provider. This will be
useful to add parent/child domain relationship from the SoC specific
Hello,
On 2014-12-02 10:59, Sjoerd Simons wrote:
Hey Marek, Inki,
On Wed, 2014-11-19 at 12:15 +0100, Marek Szyprowski wrote:
Hello Everyone,
This is another attempt to finally make Exynos SYSMMU driver fully
integrated with DMA-mapping subsystem. The main change from previous
version is a
Audio subsystem clocks are located in separate block. If clock for this
block (from main clock domain) 'mau_epll' is gated then any read or
write to audss registers will block.
This was observed on Exynos 5420 platforms (Arndale Octa and Peach
Pi/Pit) after introducing runtime PM to pl330 DMA
The audio subsystem on Exynos 5420 has separate clocks and GPIO. To
operate properly on GPIOs the main block clock 'mau_epll' must be
enabled.
This was observed on Peach Pi/Pit and Arndale Octa (after enabling i2s0)
after introducing runtime PM to pl330 DMA driver. After that commit the
Hi,
Changes since v3
1. Patch 1/3: Fix issues pointed by Sylwester.
2. Add Javier's tested-by [1]
Changes since v2
1. Patch 1 applied (clk: samsung: Fix double add of syscore ops after
driver rebind), remove it.
2. Squash patch 5 with clk: samsung: Fix clock
The pinctrl for audio subsystem needs 'mau_epll' clock to be enabled in
order to properly access memory during GPIO setup.
After introducing runtime PM to pl330 DMA driver the 'mau_epll' was
gated, because the amba clock was disabled and there were no more
users of mau_epll.
This lead to system
Javier,
On 05/12/14 12:00, Krzysztof Kozlowski wrote:
Audio subsystem clocks are located in separate block. If clock for this
block (from main clock domain) 'mau_epll' is gated then any read or
write to audss registers will block.
This was observed on Exynos 5420 platforms (Arndale Octa and
Hi Mike,
This includes a few bug fix and cleanup patches for clk/samsung.
Please pull for 3.19 if it looks OK.
The following changes since commit 2e41b9fc11f2d242f39b36ceba833471629ba3d5:
clk: samsung: Spelling s/bwtween/between/ (2014-12-02 12:28:20 +0100)
are available in the git
Hello Sylwester,
On 12/05/2014 12:22 PM, Sylwester Nawrocki wrote:
Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Can you confirm sound works with this patch on exynos5420 ? Or does
your Tested-by refer only to successful booting ?
I tested latest linux-next + clk:
Hi Krzysztof,
On 05/12/14 12:00, Krzysztof Kozlowski wrote:
Audio subsystem clocks are located in separate block. If clock for this
block (from main clock domain) 'mau_epll' is gated then any read or
write to audss registers will block.
This was observed on Exynos 5420 platforms (Arndale
On 05/12/14 13:34, Javier Martinez Canillas wrote:
Hello Sylwester,
On 12/05/2014 12:22 PM, Sylwester Nawrocki wrote:
Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Can you confirm sound works with this patch on exynos5420 ? Or does
your Tested-by refer only to
Disable the Exynos IOMMU on ARMv8-A architecture so the build won't fail.
The Exynos7 is not supported yet by Exynos IOMMU driver.
This fixes following build errors on ARMv8 (allmodconfig, allyesconfig):
drivers/iommu/exynos-iommu.c: In function ‘pgtable_flush’:
Audio subsystem clocks are located in separate block. On Exynos 5420 if
clock for this block (from main clock domain) 'mau_epll' is gated then
any read or write to audss registers will block.
This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit
after introducing runtime PM to
On Tue, Dec 02, 2014 at 06:25:49PM +0100, Lars-Peter Clausen wrote:
On 12/02/2014 06:38 AM, Padma Venkat wrote:
Well it doesn't break audio, but I don't think it has the correct
haviour for all cases yet.
Again, the semantics are that it should return the progress of the
transfer for
On Wed, Dec 03, 2014 at 01:21:37PM +0530, Jassi Brar wrote:
On 3 December 2014 at 10:17, Padma Venkat padma@gmail.com wrote:
Hi Lars,
[snip]
+
+ ret = dma_cookie_status(chan, cookie, txstate);
+ if (ret == DMA_COMPLETE || !txstate)
+ return ret;
+
+ used =
On Wed, Dec 03, 2014 at 01:21:37PM +0530, Jassi Brar wrote:
because the reasoning above seems incorrect considering the following
documentation...
Documentation/crypto/async-tx-api.txt says
async-tx-api is not the DMA slave API.
Once a
On 12/05/2014 10:10 AM, Nishanth Menon wrote:
next-20141204 fails to boot, but next-20141203 boots fine with
omap2plus_defconfig.
Panda-ES(4460):
https://github.com/nmenon/kernel-test-logs/blob/next-20141204/omap2plus_defconfig/pandaboard-es.txt
Panda(4430):
On Fri, Dec 05, 2014 at 10:13:51AM -0600, Nishanth Menon wrote:
On 12/05/2014 10:10 AM, Nishanth Menon wrote:
Case #2: Reverting the following allows boot.
From next-20141204
10df7d5 ARM: 8211/1: l2c: Add support for overriding prefetch settings
revert this - boot still fails
Add new devfreq driver for Exynos3250. The driver utilizes existing PPMU
helpers and is multiplatform safe. Currently it does not support ASV
(Adaptive Supply Voltage).
Driver creates two devices:
- Dynamic Memory Controller (DMC) and memory bus,
- peripheral (left/right) buses.
For memory it
Hi,
The aim of patchset is to gather feedback about adding new devfreq driver for
Exynos 3250, along with the bindings.
Chanwoo,
You were the author of our initial exynos3_bus.c driver so do you
want me to add your Signed-off-by?
Best regards,
Krzysztof
Krzysztof Kozlowski (3):
devfreq:
On 4 December 2014 at 23:17, Olof Johansson o...@lixom.net wrote:
On Thu, Dec 04, 2014 at 01:24:24PM -0800, Tyler Baker wrote:
This patch enables the MAX77686 PMIC drivers in the multi_v7_defconfig used
on exynos4412-prime family of SoCs [1]. The exynos4412-prime based boards
are producing the
On Fri, Dec 05, 2014 at 04:46:26PM +, Krzysztof Kozlowski wrote:
Add documentation for bindings used by Exynos3250 devfreq driver.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
.../bindings/arm/samsung/exynos3250-devfreq.txt| 66
++
1 file
Add devfreq to Exynos3250 common file and enable it for Rinato board.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
arch/arm/boot/dts/exynos3250-rinato.dts | 10 ++
arch/arm/boot/dts/exynos3250.dtsi | 32
2 files changed, 42
Add documentation for bindings used by Exynos3250 devfreq driver.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
.../bindings/arm/samsung/exynos3250-devfreq.txt| 66 ++
1 file changed, 66 insertions(+)
create mode 100644
On 2 December 2014 at 22:38, Gustavo Padovan gust...@padovan.org wrote:
Hi Inki,
Can you please review this? I also have sent other two patch sets that sits on
top of this one. Thanks.
Inki, any plans on when you can get to looking at this?
I think cleaning up exynos so we can get atomic
The device already asks the core to hold a runtime PM reference while it
is active so it is redundant to open code that in the driver itself.
Signed-off-by: Mark Brown broo...@kernel.org
---
drivers/spi/spi-s3c64xx.c | 9 -
1 file changed, 9 deletions(-)
diff --git
On 5 December 2014 at 20:48, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Wed, Dec 03, 2014 at 01:21:37PM +0530, Jassi Brar wrote:
because the reasoning above seems incorrect considering the following
documentation...
Documentation/crypto/async-tx-api.txt says
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