On 1 February 2015 at 00:29, Eduardo Valentin edubez...@gmail.com wrote:
From: Arnd Bergmann a...@arndb.de
The exynos cpufreq driver code recently gained a dependency on the
cooling code, which may be a loadable module. This breaks an ARM
allmodconfig build:
drivers/built-in.o: In function
Hi Lukasz,
On Fri, Jan 30, 2015 at 8:36 PM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Hi Lukasz,
On Fri, Jan 30, 2015 at 1:44 PM, Lukasz Majewski l.majew...@samsung.com
wrote:
Hi Eduardo, Abhilash,
On Thu, Jan 22, 2015 at 06:02:07PM +0530, Abhilash Kesavan wrote:
Hi Lukasz,
On 01/30/2015 11:36 PM, Gustavo Padovan wrote:
2015-01-30 Joonyoung Shim jy0922.s...@samsung.com:
+Cc Inki,
Hi,
On 01/23/2015 09:42 PM, Gustavo Padovan wrote:
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
exynos_plane_dpms(DRM_MODE_DPMS_ON) calls the win_enable()'s callback
Hi,
On 01/30/2015 11:42 PM, Gustavo Padovan wrote:
Hi Joonyoung,
2015-01-30 Joonyoung Shim jy0922.s...@samsung.com:
+Cc Inki,
Hi,
On 01/23/2015 09:42 PM, Gustavo Padovan wrote:
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
struct {fimd,mixer,vidi}_win_data was just keeping
Hi,
On 01/30/2015 11:44 PM, Gustavo Padovan wrote:
Hi Joonyoung,
2015-01-30 Joonyoung Shim jy0922.s...@samsung.com:
Hi,
On 01/23/2015 09:43 PM, Gustavo Padovan wrote:
From: Daniel Kurtz djku...@chromium.org
The 'mode' is the modeline information which specifies the ideal mode
Hi Eduardo,
On Sun, Feb 1, 2015 at 12:54 AM, Eduardo Valentin edubez...@gmail.com wrote:
On Tue, Jan 27, 2015 at 11:18:22AM +0530, Abhilash Kesavan wrote:
Add registers, bit fields and compatible strings for Exynos7 TMU
(Thermal Management Unit). Following are a few of the differences
in the
On 01/31/2015 02:17 AM, Gustavo Padovan wrote:
2015-01-30 Daniel Vetter dan...@ffwll.ch:
On Fri, Jan 30, 2015 at 03:57:53PM +, Daniel Stone wrote:
Hi,
On 30 January 2015 at 14:30, Gustavo Padovan gust...@padovan.org wrote:
2015-01-30 Joonyoung Shim jy0922.s...@samsung.com:
We will
+Cc dri-devel ML,
Hi,
On 01/31/2015 06:45 AM, Gustavo Padovan wrote:
From: Prathyush K prathyus...@samsung.com
When VPLL clock of less than 140 MHz was used and all the three
clocks - hdmiphy, hdmi, sclk_hdmi are disabled, the system hangs
during S2R when HDMI is connected. Since we want
