2015-04-03 10:12 GMT+02:00 Andrzej Hajda a.ha...@samsung.com:
On 04/02/2015 02:44 PM, Krzysztof Kozlowski wrote:
2015-04-02 14:29 GMT+02:00 Javier Martinez Canillas
javier.marti...@collabora.co.uk:
Hello Krzysztof,
On 04/02/2015 10:06 AM, Krzysztof Kozlowski wrote:
Using a fixed (by DTS)
Extend the S3C RTC node with rtc_src clock so it could be operational.
The rtc_src clock is provided by MAX77686 (Trats2) or S2MPS11 (Arndale
Octa).
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Patch depends
Hi,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
index e71e331..e0b085b 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
@@ -275,9 +275,6 @@ int exynos_drm_fbdev_init(struct
On 04/02/2015 02:44 PM, Krzysztof Kozlowski wrote:
2015-04-02 14:29 GMT+02:00 Javier Martinez Canillas
javier.marti...@collabora.co.uk:
Hello Krzysztof,
On 04/02/2015 10:06 AM, Krzysztof Kozlowski wrote:
Using a fixed (by DTS) parent for clocks when turning on the power domain
may introduce
Use a define instead of raw number as a ID for rtc_src clock.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Patch depends on new file dt-bindings/clock/samsung,s2mps11.h from:
1. ARM: dts: Add bindings for
Replace fixed parent with last parent (obtained with clk_get_parent())
of clocks for devices in mfc and disp power domains. This should improve
behavior if such clocks were reparented by the drivers and new parents
are different than those specified in DTS.
Signed-off-by: Krzysztof Kozlowski
Using a fixed (by DTS) parent for clocks when turning on the power domain
may introduce issues in other drivers. For example when such driver
changes the parent during runtime and expects that he is the only place
of such change.
Do not rely on DTS providing the fixed parent for such clocks.
On 2015년 04월 02일 01:02, Gustavo Padovan wrote:
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
We already set each plane zpos at init, after that changes to zpos are
not expected. This patch turns zpos into a read-only property so now it is
impossible to set zpos.
Signed-off-by:
Hi Joonyoung,
2015-04-03 Joonyoung Shim jy0922.s...@samsung.com:
Hi,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
index e71e331..e0b085b 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
+++
Hi Inki,
2015-04-03 Inki Dae inki@samsung.com:
On 2015년 04월 02일 01:02, Gustavo Padovan wrote:
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
We already set each plane zpos at init, after that changes to zpos are
not expected. This patch turns zpos into a read-only property so
From: Thomas Abraham thomas...@samsung.com
Exynos4210 based platforms have switched over to use generic
cpufreq driver for cpufreq functionality. So the Exynos
specific cpufreq support for these platforms can be removed.
Changes by Bartlomiej:
- dropped Exynos5250 support removal for now
-
From: Thomas Abraham thomas...@samsung.com
The new CPU clock type allows the use of generic CPUfreq driver.
Switch Exynos4210 to using generic cpufreq driver.
Changes by Bartlomiej:
- removed non-Exynos4210 support for now
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Kukjin Kim
This flag is needed to fix the issue with wrong dividers being setup
by Common Clock Framework when using the new Exynos cpu clock support.
The issue happens because clk_core_set_rate_nolock() calls
clk_calc_new_rates(clk, rate) before both pre/post clock notifiers have
a chance to run. In case
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Hi,
Here goes the full support for atomic modesetting on exynos. I've
split the patches in the various phases of atomic support.
These patches sits on top of the clean up patches I've sent yesterday
to this mailing list[1].
v2: fixes
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
PageFlips now use the atomic helper to work through the atomic modesetting
API. Async page flips are not supported yet.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 63
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Now that no one is using the functions exported by exynos_drm_plane due
to the atomic conversion we can make remove some of the them or make them
static.
v2: remove unused exynos_drm_crtc
Signed-off-by: Gustavo Padovan
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Run dpms operations through the atomic intefaces. This basically removes
the .dpms() callback from econders and crtcs and use .disable() and
.enable() to turn the crtc on and off.
v2: Address comments by Joonyoung:
- make hdmi code
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Now that phase 1 and 2 are complete switch .set_config helper to
use the atomic one.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 2 +-
1 file changed, 1 insertion(+), 1
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
The new atomic infrastructure needs the .mode_set_nofb() callback to
update CRTC timings before setting any plane.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 60
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Set CRTC, planes and connectors to use the default implementations from
the atomic helper library. The helpers will work to keep track of state
for each DRM object.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Rip out the check from exynos_update_plane() and create
exynos_check_plane() for the check phase enabling use to use
the atomic helpers to call our check and update phases when updating
planes.
Update all users of exynos_update_plane()
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
The atomic helper to disable planes also uses the optional
.atomic_disable() helper. The unique operation it does is calling
.win_disable()
exynos_drm_fb_get_buf_cnt() needs a fb check too to avoid a null pointer.
Signed-off-by: Gustavo
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Use drm_atomic_set_fb_for_plane() in the legacy page_flip path to keep
track of the framebuffer pointer and reference.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 3 +++
1
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Now that phase 1 and 2 are complete we can switch the update/disable_plane
callbacks to their atomic version.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_fb.c| 3 +++
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Everything starts disabled so we don't really need to disable anything.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_fbdev.c | 3 ---
1 file changed, 3 deletions(-)
diff --git
From: Thomas Abraham thomas...@samsung.com
For Exynos4210 platforms, add CPU operating points and CPU
regulator supply properties for migrating from Exynos specific
cpufreq driver to using generic cpufreq driver.
Changes by Bartlomiej:
- removed Exynos5250 and Exynos5420 support for now
Cc:
From: Thomas Abraham thomas...@samsung.com
The CPU clock provider supplies the clock to the CPU clock domain. The
composition and organization of the CPU clock provider could vary among
Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers
and gates. This patch defines a new
Hi,
This patch series removes the use of Exynos4210 specific support
from cpufreq-exynos driver and enables the use of cpufreq-dt driver
for this platform.
It consists of a modified [PATCH v12 0/6] cpufreq: use generic
cpufreq drivers for exynos platforms [1] patch series from Thomas
Abraham.
From: Thomas Abraham thomas...@samsung.com
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos4210.
Changes by Bartlomiej:
- fixed issue with wrong
On Thu, Apr 02, 2015 at 03:17:33AM +0900, Kukjin Kim wrote:
The following changes since commit c517d838eb7d07bbe9507871fab3931deccff539:
Linux 4.0-rc1 (2015-02-22 18:21:14 -0800)
are available in the git repository at:
On Thu, Apr 02, 2015 at 02:23:55AM +0900, Kukjin Kim wrote:
Hi Arnd, Olof, Kevin,
Here is 2nd Samsung fixes for v4.0 and it fixes arm allmodconfig build
breakage and exynos5250-spring lid, power-pin and mmc nodes dt updates.
Please pull and sorry for pretty late pull-request for v4.0.
On Thu, Apr 02, 2015 at 03:15:54AM +0900, Kukjin Kim wrote:
The following changes since commit c517d838eb7d07bbe9507871fab3931deccff539:
Linux 4.0-rc1 (2015-02-22 18:21:14 -0800)
are available in the git repository at:
On Thu, Apr 02, 2015 at 03:16:55AM +0900, Kukjin Kim wrote:
The following changes since commit c517d838eb7d07bbe9507871fab3931deccff539:
Linux 4.0-rc1 (2015-02-22 18:21:14 -0800)
are available in the git repository at:
On Thu, Apr 02, 2015 at 03:16:22AM +0900, Kukjin Kim wrote:
The following changes since commit c517d838eb7d07bbe9507871fab3931deccff539:
Linux 4.0-rc1 (2015-02-22 18:21:14 -0800)
are available in the git repository at:
On Thu, Apr 02, 2015 at 03:16:38AM +0900, Kukjin Kim wrote:
The following changes since commit c517d838eb7d07bbe9507871fab3931deccff539:
Linux 4.0-rc1 (2015-02-22 18:21:14 -0800)
are available in the git repository at:
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