On Thu, 02 Apr 2015, Krzysztof Kozlowski wrote:
The RTC on S2MPS11 is the same as S2MPS14. However interrupt numbers of
RTC alarms 0 and 1 were inversed between these two devices. So when
rtc-s5m driver requested S2MPS14_IRQ_RTCA0 interrupt, it matched to
S2MPS11_IRQ_RTCA1, not RTCA0.
Fix
On 2015년 04월 07일 00:44, Inki Dae wrote:
2015-04-06 19:46 GMT+09:00 Inki Dae inki@samsung.com:
On 2015년 04월 04일 03:09, Gustavo Padovan wrote:
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Hi,
Here goes the full support for atomic modesetting on exynos. I've
split the patches in
Hi,
On 04/07/2015 03:26 AM, Gustavo Padovan wrote:
Hi Inki,
2015-04-05 Inki Dae inki@samsung.com:
Hi,
2015-04-04 3:09 GMT+09:00 Gustavo Padovan gust...@padovan.org:
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Run dpms operations through the atomic intefaces. This
Hi,
On 04/07/2015 08:14 AM, Tobias Jakobi wrote:
The messages are redundant since 'check_fb_gem_memory_type'
already prints out exactly the same string when it fails.
Reviewed-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
Signed-off-by: Tobias Jakobi tjak...@math.uni-bielefeld.de
---
Hi,
On 04/07/2015 08:14 AM, Tobias Jakobi wrote:
Use the correct spelling for 'progressive'.
Reviewed-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
Signed-off-by: Tobias Jakobi tjak...@math.uni-bielefeld.de
---
drivers/gpu/drm/exynos/exynos_hdmi.c | 2 +-
Hi,
On 04/07/2015 08:14 AM, Tobias Jakobi wrote:
While the VP (video processor) supports arbitrary scaling
of its input, the mixer just supports a simple 2x (line
doubling) scaling. Expose this functionality and exit
early when an unsupported scaling configuration is
encountered.
This was
Hello Krzysztof,
On 04/03/2015 11:33 AM, Krzysztof Kozlowski wrote:
Using a fixed (by DTS) parent for clocks when turning on the power domain
may introduce issues in other drivers. For example when such driver
changes the parent during runtime and expects that he is the only place
of such
I'm very worried about adding a DT that's known broken, especially when
we have no idea as to if/when the FW will be fixed judging from prior
replies.
As I replied, I can not fix the FW because I don't have any code of FW.
Surely you are able to contact those who do?
I don't
On 2015년 04월 07일 16:06, Inki Dae wrote:
On 2015년 04월 07일 00:44, Inki Dae wrote:
2015-04-06 19:46 GMT+09:00 Inki Dae inki@samsung.com:
On 2015년 04월 04일 03:09, Gustavo Padovan wrote:
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Hi,
Here goes the full support for atomic
Hello Abhilash,
On 04/02/2015 02:22 PM, Abhilash Kesavan wrote:
Hi,
On Thu, Apr 2, 2015 at 4:01 AM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Hello Sylwester,
On 04/01/2015 07:31 PM, Sylwester Nawrocki wrote:
On 01/04/15 13:44, Javier Martinez Canillas wrote:
On
On 2015년 03월 04일 23:02, Marek Szyprowski wrote:
From: Beata Michalska b.michal...@samsung.com
As for now there is no validation of incoming buffer
enqueue request as far as the gem buffers are being
concerned. This might lead to some undesired cases
when the driver tries to operate on
On 04/07/2015 12:59 PM, Javier Martinez Canillas wrote:
So IIUC the CG_STATUS0 bits were a red herring and the real problem
is that the aclk266_g2d needs to be enabled during suspend (although
we still don't know why).
It seems were are at a dead end now. Without being able to ask the HW
2015-04-07 13:56 GMT+02:00 Javier Martinez Canillas
javier.marti...@collabora.co.uk:
So I disabled the sss clock before trying a S2R:
# devmem 0x10018800 32 0xFFFB
(CLK_SSS in CLK_GATE_IP_G2D is gated)
and S2R worked anyways but I see that CLK_GATE_IP_G2D is reset to
its default value
On 2015년 03월 28일 01:08, Krzysztof Kozlowski wrote:
After adding display power domain for Exynos5250 in commit
2d2c9a8d0a4f (ARM: dts: add display power domain for exynos5250) the
display on Chromebook Snow and others stopped working after boot.
The reason for this suggested Andrzej Hajda:
Hello Tomasz,
On 04/07/2015 02:46 PM, Tomasz Figa wrote:
2015-04-07 13:56 GMT+02:00 Javier Martinez Canillas
javier.marti...@collabora.co.uk:
So I disabled the sss clock before trying a S2R:
# devmem 0x10018800 32 0xFFFB
(CLK_SSS in CLK_GATE_IP_G2D is gated)
and S2R worked anyways but
Hello Abhilash,
On 04/07/2015 04:11 PM, Abhilash Kesavan wrote:
Yes, though it increasingly looks like aclk266_g2d needs to stay ON
and we should use your patch that keeps it enabled prior to suspend.
Indeed, could you please give me some feedback on the latest RFC patch
I shared [0] on
Javier,
On Tue, Apr 7, 2015 at 6:03 AM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
The Marvell mwifiex driver prevents the system to enter into a suspend
state if the card power is not preserved during a suspend/resume cycle.
So Suspend-to-RAM and Suspend-to-idle is
Hi Javier,
On Tue, Apr 7, 2015 at 7:41 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Hello Tomasz,
On 04/07/2015 02:46 PM, Tomasz Figa wrote:
2015-04-07 13:56 GMT+02:00 Javier Martinez Canillas
javier.marti...@collabora.co.uk:
So I disabled the sss clock before trying
The Marvell mwifiex driver prevents the system to enter into a suspend
state if the card power is not preserved during a suspend/resume cycle.
So Suspend-to-RAM and Suspend-to-idle is failing on Exynos5800 Peach Pi
and Exynos5420 Peach Pit Chromebooks.
Add the keep-power-in-suspend Power
Hello Abhilash,
On 04/07/2015 04:38 PM, Abhilash Kesavan wrote:
[0]
From 78aa551ebcb9a4a7ae9d5581c33e0c0f19fe5ad6 Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas javier.marti...@collabora.co.uk
Date: Tue, 7 Apr 2015 15:53:27 +0200
Subject: [RFC PATCH] clk: exynos5420: Restore
On 2015년 04월 07일 08:14, Tobias Jakobi wrote:
Use the correct spelling for 'progressive'.
1 through 3, Applied.
Thanks,
Inki Dae
Reviewed-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
Signed-off-by: Tobias Jakobi tjak...@math.uni-bielefeld.de
---
Hi Javier,
On Tue, Apr 7, 2015 at 4:29 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Hello Abhilash,
On 04/02/2015 02:22 PM, Abhilash Kesavan wrote:
Hi,
On Thu, Apr 2, 2015 at 4:01 AM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Hello Sylwester,
Hi,
the base patch in [0] has been applied now.
My patch was meanwhile
Tested-by: Anand Moon linux.am...@gmail.com
Am 31.03.2015 um 14:27 schrieb Markus Reichl:
Am 30.03.2015 um 17:51 schrieb Markus Reichl:
HS400 timing values are added for exynos5422-odroidxu3 board.
---
This patch is
Javier Martinez Canillas javier.marti...@collabora.co.uk writes:
[...]
Yes, the following patch [0] is enough to make S2R working. If you think
that is correct then I'll post it as a proper patch then.
[...]
[0]
From 78aa551ebcb9a4a7ae9d5581c33e0c0f19fe5ad6 Mon Sep 17 00:00:00 2001
From:
Hi Inki,
2015-04-07 Inki Dae inki@samsung.com:
On 2015년 04월 07일 16:06, Inki Dae wrote:
On 2015년 04월 07일 00:44, Inki Dae wrote:
2015-04-06 19:46 GMT+09:00 Inki Dae inki@samsung.com:
On 2015년 04월 04일 03:09, Gustavo Padovan wrote:
From: Gustavo Padovan
Hi Inki,
2015-04-07 Inki Dae inki@samsung.com:
On 2015년 04월 07일 00:44, Inki Dae wrote:
2015-04-06 19:46 GMT+09:00 Inki Dae inki@samsung.com:
On 2015년 04월 04일 03:09, Gustavo Padovan wrote:
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Hi,
Here goes the full support
I don't know if I can really help with this, but I'm going to try to
reproduce this on my board tomorrow.
With best wishes,
Tobias
Gustavo Padovan wrote:
Hi Inki,
2015-04-07 Inki Dae inki@samsung.com:
On 2015년 04월 07일 00:44, Inki Dae wrote:
2015-04-06 19:46 GMT+09:00 Inki Dae
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Run dpms operations through the atomic intefaces. This basically removes
the .dpms() callback from econders and crtcs and use .disable() and
.enable() to turn the crtc on and off.
v2: Address comments by Joonyoung:
- make hdmi code
2015-04-07 16:11 GMT+02:00 Javier Martinez Canillas
javier.marti...@collabora.co.uk:
From 78aa551ebcb9a4a7ae9d5581c33e0c0f19fe5ad6 Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas javier.marti...@collabora.co.uk
Date: Tue, 7 Apr 2015 15:53:27 +0200
Subject: [RFC PATCH] clk: exynos5420:
Hi, Markus.
I have also tested on Odroid-xu3 board.
Acked-by: Jaehoon Chung jh80.ch...@samsung.com
Best Regards,
Jaehoon Chung
On 04/08/2015 12:33 AM, Markus Reichl wrote:
Hi,
the base patch in [0] has been applied now.
My patch was meanwhile
Tested-by: Anand Moon
Hi Javier,
On Tue, Apr 7, 2015 at 8:30 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Hello Abhilash,
On 04/07/2015 04:38 PM, Abhilash Kesavan wrote:
[0]
From 78aa551ebcb9a4a7ae9d5581c33e0c0f19fe5ad6 Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas
Commit ae43b3289186 (ARM: 8202/1: dmaengine: pl330: Add runtime Power
Management support v12) added pm support for the pl330 dma driver but
it makes the clock for the Exynos5420 MDMA0 DMA controller to be gated
during suspend and this in turn makes its parent clock aclk266_g2d to
be gated. But the
Hello Tomasz,
On 04/07/2015 11:28 PM, Tomasz Figa wrote:
Looks good to me. You can consider this Acked-by, as long as Sylwester
is not opposed to this approach.
Thanks a lot, I've posted it as a proper patch now.
Best regards,
Tomasz
Best regards,
Javier
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