Hello Krzysztof,
On Tue, Aug 25, 2015 at 12:35 PM, Krzysztof Kozlowski
k.kozlow...@samsung.com wrote:
On 24.08.2015 20:05, Alim Akhtar wrote:
This updates CMU TOP1 block clock as per latest UM.
I think description is not entirely correct. Some of the changes here
were present in the first
Gentle ping!
On 2015-08-18 00:51, Tobias Jakobi wrote:
The cases of the switch statement ensure that reg_type
can never be REG_TYPE_NONE here.
Signed-off-by: Tobias Jakobi tjak...@math.uni-bielefeld.de
---
drivers/gpu/drm/exynos/exynos_drm_g2d.c | 8
1 file changed, 8 deletions(-)
Gentle ping!
Also please note that this is a critical fix. With the
incomplete check pagefaults can happen when the engine
accesses a invalid buffer position.
With best wishes,
Tobias
On 2015-08-18 00:51, Tobias Jakobi wrote:
The size check was incomplete. It only computed the
size of area
Hello Krzysztof,
On Tue, Aug 25, 2015 at 12:46 PM, Krzysztof Kozlowski
k.kozlow...@samsung.com wrote:
On 24.08.2015 20:05, Alim Akhtar wrote:
This patch correct the nr_clk_ids for fsys0 block
s/correct/corrects/
which is wrongly set to TOP1 clk numbers.
This also adjust the a gate clock
Hi Thierry,
在 2015/8/25 22:16, Thierry Reding 写道:
On Tue, Aug 25, 2015 at 09:48:01PM +0800, Yakir Yang wrote:
Hi Thierry Rob,
在 2015/8/25 21:27, Rob Herring 写道:
On Tue, Aug 25, 2015 at 4:15 AM, Thierry Reding tred...@nvidia.com wrote:
On Sun, Aug 23, 2015 at 06:23:14PM -0500, Rob Herring
Hi Thierry,
在 2015/8/25 17:58, Thierry Reding 写道:
On Wed, Aug 19, 2015 at 09:50:34AM -0500, Yakir Yang wrote:
[...]
+ -analogix,color-space:
+ input video data format.
+ COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
I don't think DT is an
[ added Lorenzo and linux-pm to Cc: ]
Hi,
On Tuesday, August 25, 2015 11:43:38 AM Javier Martinez Canillas wrote:
[adding Kevin Hilman as cc who was also interested in CPUidle for Exynos]
Hello Krzysztof,
On 08/23/2015 03:26 AM, Krzysztof Kozlowski wrote:
[snip]
2015-08-21 16:21
On Tue, Aug 25, 2015 at 10:03:52PM +0800, Yakir Yang wrote:
Hi Thierry,
在 2015/8/25 17:58, Thierry Reding 写道:
On Wed, Aug 19, 2015 at 09:50:34AM -0500, Yakir Yang wrote:
[...]
+ -analogix,color-space:
+ input video data format.
+ COLOR_RGB = 0, COLOR_YCBCR422
Hi Thierry,
在 2015/8/25 18:06, Thierry Reding 写道:
On Tue, Aug 25, 2015 at 05:41:19PM +0800, Yakir Yang wrote:
Hi Thierry,
在 2015/8/25 17:12, Thierry Reding 写道:
On Mon, Aug 24, 2015 at 09:48:27AM -0500, Rob Herring wrote:
On Mon, Aug 24, 2015 at 7:57 AM, Russell King - ARM Linux
Hello Krzysztof,
On Tue, Aug 25, 2015 at 12:48 PM, Krzysztof Kozlowski
k.kozlow...@samsung.com wrote:
On 24.08.2015 20:05, Alim Akhtar wrote:
nr_clk_ids for FSYS1 block is wrongly set as TOP1 block,
this patch correct the same.
s/correct the same/corrects it/
will update
Reviewed-by:
On Tue, Aug 25, 2015 at 03:35:29PM +0100, Bartlomiej Zolnierkiewicz wrote:
[ added Lorenzo and linux-pm to Cc: ]
Hi,
On Tuesday, August 25, 2015 11:43:38 AM Javier Martinez Canillas wrote:
[adding Kevin Hilman as cc who was also interested in CPUidle for Exynos]
Hello Krzysztof,
On Tue, Aug 25, 2015 at 04:21:51PM +0200, Thierry Reding wrote:
You cited code from dw_hdmi.c earlier, it looks like it might be correct
even though it doesn't cite a reference for why this was done. Perhaps
someone on this thread, or someone involved with dw_hdmi can answer
where that code
Hello Krzysztof,
On Tue, Aug 25, 2015 at 12:32 PM, Krzysztof Kozlowski
k.kozlow...@samsung.com wrote:
On 24.08.2015 20:05, Alim Akhtar wrote:
This patch fixes some of the bit field and
update the TOPC block clock as per the latest UM.
Description is not entirely correct. The
On Tue, Aug 25, 2015 at 09:48:01PM +0800, Yakir Yang wrote:
Hi Thierry Rob,
在 2015/8/25 21:27, Rob Herring 写道:
On Tue, Aug 25, 2015 at 4:15 AM, Thierry Reding tred...@nvidia.com wrote:
On Sun, Aug 23, 2015 at 06:23:14PM -0500, Rob Herring wrote:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang
boot
failures in next-20150825[1] only when using exynos_defconfig.
I noticed the issue too but I fought it was a temporary network problem.
Apparently it's not temporary. :)
I thought the same as well :)
I went
ahead and bisected[2] the failure and found this patch was the
offender
Corrects the bit width of DIV_TOPC3 register.
These are worngly set to 3 which should be 4 bit wide as per UM.
This also adjusts the MUX clock order.
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
---
drivers/clk/samsung/clk-exynos7.c | 12 ++--
1 file changed, 6 insertions(+), 6
This patch corrects the nr_clk_ids for fsys0 block
which is wrongly set to TOP1 clk numbers.
This also adjusts the gate clock order.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
This patch series are minor improvement over the current
exynos7 clock file. This fix some bugs and update the clock
bits as per user manual.
Changes from v1:
* Fix review comments by Krzysztof [1].
* Added Padmavathi's Singed-of-by for patch# 3 and 4,
as I see [2] which are similar, looks
nr_clk_ids for FSYS1 block is wrongly set as TOP1 block,
this patch corrects it.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
drivers/clk/samsung/clk-exynos7.c |2 +-
1 file
As per UM, sclk_mmc2 is bit 16 of SEL_TOP1_FSYS0. Also the DIV
and the GATE clocks are at bit 16 in their respective registers.
For mmc1 and mmc0 clock MUXs are in TOP1_FSYS11 instead of TOP1_FSYS1.
And their DIV and GATE clks are in xxx_TOP1_FSYS11 instead of TOP1_FSYS1.
This patch corrects it.
On 26.08.2015 12:30, Alim Akhtar wrote:
Corrects the bit width of DIV_TOPC3 register.
These are worngly set to 3 which should be 4 bit wide as per UM.
This also adjusts the MUX clock order.
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
---
drivers/clk/samsung/clk-exynos7.c | 12
On 26.08.2015 12:30, Alim Akhtar wrote:
As per UM, sclk_mmc2 is bit 16 of SEL_TOP1_FSYS0. Also the DIV
and the GATE clocks are at bit 16 in their respective registers.
For mmc1 and mmc0 clock MUXs are in TOP1_FSYS11 instead of TOP1_FSYS1.
And their DIV and GATE clks are in xxx_TOP1_FSYS11
On 24.08.2015 20:05, Alim Akhtar wrote:
nr_clk_ids for FSYS1 block is wrongly set as TOP1 block,
this patch correct the same.
s/correct the same/corrects it/
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Best regards,
Krzysztof
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
On 24.08.2015 20:05, Alim Akhtar wrote:
This patch correct the nr_clk_ids for fsys0 block
s/correct/corrects/
which is wrongly set to TOP1 clk numbers.
This also adjust the a gate clock order.
s/adjust the a/adjusts the/
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Best regards,
The exynos5_i2c_message_start enables interrupts while holding the i2c
lock which is sought by the irq handler. If an IRQ is received before
this lock is released then a deadlock occurs.
This is only seen on an RT patched kernel, due to the transformation of
spinlocks into sleeping locks. By
On 25.08.2015 14:47, Marek Szyprowski wrote:
Hello,
On 2015-08-21 14:44, Kishon Vijay Abraham I wrote:
On Friday 21 August 2015 06:08 PM, Marek Szyprowski wrote:
Exynos USB2 PHY has separate power supply, which is usually provided by
VBUS regulator. This patch adds support for it. VBUS
On 24.08.2015 20:05, Alim Akhtar wrote:
This patch fixes some of the bit field and
update the TOPC block clock as per the latest UM.
Description is not entirely correct. The ENABLE_ACLK_TOPC1 register
was present already both in driver and in first user manual. That means
it was just forgotten
On 08/23/2015 02:17 PM, Mauro Carvalho Chehab wrote:
Now that a link can be either between two different graph
objects, we'll need to add more functions to create links.
Is this an incomplete sentence. Should it read: either between
two different graph objects or two pads ?
So, rename the
Hi Thierry,
在 2015/8/25 17:12, Thierry Reding 写道:
On Mon, Aug 24, 2015 at 09:48:27AM -0500, Rob Herring wrote:
On Mon, Aug 24, 2015 at 7:57 AM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Sun, Aug 23, 2015 at 06:23:14PM -0500, Rob Herring wrote:
On Wed, Aug 19, 2015 at 9:50 AM,
On Mon, Aug 24, 2015 at 09:48:27AM -0500, Rob Herring wrote:
On Mon, Aug 24, 2015 at 7:57 AM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Sun, Aug 23, 2015 at 06:23:14PM -0500, Rob Herring wrote:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang y...@rock-chips.com wrote:
+
On Wed, Aug 19, 2015 at 09:50:34AM -0500, Yakir Yang wrote:
[...]
+ -analogix,color-space:
+ input video data format.
+ COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
I don't think DT is an appropriate place to set this. To my knowledge
this depends
On Tue, Aug 25, 2015 at 10:29:39AM +0100, Russell King - ARM Linux wrote:
On Tue, Aug 25, 2015 at 11:12:48AM +0200, Thierry Reding wrote:
On Mon, Aug 24, 2015 at 09:48:27AM -0500, Rob Herring wrote:
It goes beyond bindings IMO. The use of the component framework or not
has been at the
[adding Kevin Hilman as cc who was also interested in CPUidle for Exynos]
Hello Krzysztof,
On 08/23/2015 03:26 AM, Krzysztof Kozlowski wrote:
[snip]
2015-08-21 16:21 GMT+09:00 Javier Martinez Canillas jav...@osg.samsung.com:
The big.LITTLE cpuidle driver is not a typical Exynos cpuidle
On Tue, Aug 25, 2015 at 05:41:19PM +0800, Yakir Yang wrote:
Hi Thierry,
在 2015/8/25 17:12, Thierry Reding 写道:
On Mon, Aug 24, 2015 at 09:48:27AM -0500, Rob Herring wrote:
On Mon, Aug 24, 2015 at 7:57 AM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Sun, Aug 23, 2015 at
On Sun, Aug 23, 2015 at 06:23:14PM -0500, Rob Herring wrote:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang y...@rock-chips.com wrote:
[...]
+ -analogix,link-rate:
+ max link rate supported by the eDP controller.
+ LINK_RATE_1_62GBPS = 0x6,
On Tue, Aug 25, 2015 at 11:12:48AM +0200, Thierry Reding wrote:
On Mon, Aug 24, 2015 at 09:48:27AM -0500, Rob Herring wrote:
It goes beyond bindings IMO. The use of the component framework or not
has been at the whim of driver writers as well. It is either used or
private APIs are created.
Hi Thierry,
在 2015/8/25 17:15, Thierry Reding 写道:
On Sun, Aug 23, 2015 at 06:23:14PM -0500, Rob Herring wrote:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang y...@rock-chips.com wrote:
[...]
+ -analogix,link-rate:
+ max link rate supported by the eDP controller.
+
On Tue, 25 Aug 2015, Anders Roxell wrote:
The exynos5_i2c_message_start enables interrupts while holding the i2c
lock which is sought by the irq handler. If an IRQ is received before
this lock is released then a deadlock occurs.
That's crap. The interrupt handler runs in an irq thread as RT
Quoting Bartlomiej Zolnierkiewicz (2015-08-06 06:41:50)
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos4x12.
Based on the earlier work by
.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
The kernelci.org bot recently reported a handful of exynos boot
failures in next-20150825[1] only when using exynos_defconfig. I went
ahead and bisected[2] the failure and found this patch was the
offender. Looking a bit closer, the kernelci.org
On Tue, Aug 25, 2015 at 12:36 AM, Hans Verkuil hverk...@xs4all.nl wrote:
On 08/23/2015 10:17 PM, Mauro Carvalho Chehab wrote:
From: Javier Martinez Canillas jav...@osg.samsung.com
The struct media_entity has a .parent field that stores a pointer
to the parent struct media_device. But recently
On Tue, Aug 25, 2015 at 12:40:01PM +0200, Thierry Reding wrote:
On Tue, Aug 25, 2015 at 10:29:39AM +0100, Russell King - ARM Linux wrote:
Now, what happens when some other DRM driver wants to use the tda998x
driver, and its bindings are not compatible with the component helpers?
They're
On 08/23/2015 10:17 PM, Mauro Carvalho Chehab wrote:
From: Javier Martinez Canillas jav...@osg.samsung.com
The struct media_entity has a .parent field that stores a pointer
to the parent struct media_device. But recently a media_gobj was
embedded into the entities and since struct media_gojb
On Tue, Aug 25, 2015 at 4:15 AM, Thierry Reding tred...@nvidia.com wrote:
On Sun, Aug 23, 2015 at 06:23:14PM -0500, Rob Herring wrote:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang y...@rock-chips.com wrote:
[...]
+ -analogix,link-rate:
+ max link rate supported by the eDP
as the most common USB Ethernet gadget.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
The kernelci.org bot recently reported a handful of exynos boot
failures in next-20150825[1] only when using exynos_defconfig.
I noticed the issue too but I fought it was a temporary network
-hsotg) hardware module is available on many Exynos based boards,
so enable DWC2 driver as well as the most common USB Ethernet gadget.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
The kernelci.org bot recently reported a handful of exynos boot
failures in next-20150825[1] only when
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