-pi.dts | 31
+
1 file changed, 31 insertions(+)
Reviewed-by: Doug Anderson diand...@chromium.org
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with every single other dts patch to pi.
Reviewed-by: Doug Anderson diand...@chromium.org
-Doug
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compatible string so that MAX98091
CODEC can be specified from device tree.
Signed-off-by: Wonjoon Lee woojoo@samsung.com
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Tushar Behera tusha...@samsung.com
---
Picked from https://chromium-review.googlesource.com/#/c
every 2 seconds for AC
detect, which is sufficient.
For proper functioning, requires (mfd: tps65090: Don't tell child
devices we have an IRQ if we don't). If we don't have that patch
we'll simply fail to probe on devices without an interrupt (just like
we did before this patch).
Signed-off-by: Doug
Kevin,
On Fri, Jun 20, 2014 at 2:48 PM, Kevin Hilman khil...@linaro.org wrote:
Hi Doug,
Doug Anderson diand...@chromium.org writes:
On Thu, Jun 19, 2014 at 11:43 AM, Kevin Hilman khil...@linaro.org wrote:
Doug Anderson diand...@chromium.org writes:
The original code for the exynos i2c
Kevin,
On Fri, Jun 20, 2014 at 4:13 PM, Kevin Hilman khil...@linaro.org wrote:
Doug Anderson diand...@chromium.org writes:
Kevin,
On Fri, Jun 20, 2014 at 2:48 PM, Kevin Hilman khil...@linaro.org wrote:
Hi Doug,
Doug Anderson diand...@chromium.org writes:
On Thu, Jun 19, 2014 at 11:43 AM
Daniel,
On Thu, Jun 19, 2014 at 2:07 AM, Daniel Lezcano
daniel.lezc...@linaro.org wrote:
On 06/19/2014 01:17 AM, Doug Anderson wrote:
Amit,
Thanks for posting!
On Wed, Jun 18, 2014 at 4:31 AM, Amit Daniel Kachhap
amit.dan...@samsung.com wrote:
This patch register the exynos mct
Hi,
On Thu, Jun 19, 2014 at 3:21 AM, Tomasz Figa tomasz.f...@gmail.com wrote:
+static struct delay_timer exynos4_delay_timer;
+
+static unsigned long exynos4_read_current_timer(void)
Note: I think this should return a cycles_t, not an unsigned long.
They're the same (right now), but probably
Daniel,
On Thu, Jun 19, 2014 at 9:02 AM, Daniel Lezcano
daniel.lezc...@linaro.org wrote:
My understanding of the current status is:
* I posed the 64-bit version that's almost as fast as the 32-bit version.
* I asked if people want the 32-bit version: no answer
* I asked if anyone is opposed
Tomasz,
On Thu, Jun 19, 2014 at 9:17 AM, Tomasz Figa tomasz.f...@gmail.com wrote:
On 19.06.2014 18:01, Doug Anderson wrote:
Hi,
On Thu, Jun 19, 2014 at 3:21 AM, Tomasz Figa tomasz.f...@gmail.com wrote:
+static struct delay_timer exynos4_delay_timer;
+
+static unsigned long
Daniel,
On Tue, Jun 17, 2014 at 5:13 AM, Daniel Lezcano
daniel.lezc...@linaro.org wrote:
On 06/04/2014 07:30 PM, Doug Anderson wrote:
In (93bfb76 clocksource: exynos_mct: register sched_clock callback) we
supported using the MCT as a scheduler clock. We properly marked
() to show up in ftrace profiles if it's the
bottleneck.
Signed-off-by: Doug Anderson diand...@chromium.org
---
Changes in v2:
- Split out from other patches so this can go into 3.16.
- Better comment about why exynos4_frc_read() should be traceable.
- No more useless inline.
drivers/clocksource
Kevin,
On Thu, Jun 19, 2014 at 11:43 AM, Kevin Hilman khil...@linaro.org wrote:
Doug Anderson diand...@chromium.org writes:
The original code for the exynos i2c controller registered for the
noirq variants. However during review feedback it was moved to
SIMPLE_DEV_PM_OPS without anyone
Lee,
On Wed, Jun 18, 2014 at 12:55 AM, Lee Jones lee.jo...@linaro.org wrote:
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
Preparing the way for the LPC device, which is just a plaform_device without
interrupts.
Signed-off-by: Bill Richardson wfric
Lee,
On Wed, Jun 18, 2014 at 12:57 AM, Lee Jones lee.jo...@linaro.org wrote:
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
This comment was incorrect, so update it.
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Simon Glass s
Lee,
On Wed, Jun 18, 2014 at 12:53 AM, Lee Jones lee.jo...@linaro.org wrote:
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
The lower-level driver may want to provide its own buffers. If so,
there's no need to allocate new ones. This already happens
Lee,
On Wed, Jun 18, 2014 at 9:46 AM, Lee Jones lee.jo...@linaro.org wrote:
On Wed, 18 Jun 2014, Doug Anderson wrote:
Lee,
On Wed, Jun 18, 2014 at 12:55 AM, Lee Jones lee.jo...@linaro.org wrote:
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
that will
eventually be used.]
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Doug Anderson diand...@chromium.org
Acked-by: Lee Jones lee.jo...@linaro.org
---
Changes in v2: None
drivers/mfd/cros_ec.c | 2 +-
drivers/mfd/cros_ec_i2c.c | 4 +--
drivers/mfd/cros_ec_spi.c | 10
This is a batch of cleanup patches picked from the ChromeOS 3.8 kernel
tree and applied to ToT. Most of these patches were authored by Bill
Richardson (CCed). Where appropriate I've squashed patches together,
though I have erred on the side of keeping patches logically distinct
rather than
From: Bill Richardson wfric...@chromium.org
When communicating with the EC, the cmd_xfer() function should return the
number of bytes it received from the EC, or negative on error.
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Doug Anderson diand...@chromium.org
Acked
-by: Doug Anderson diand...@chromium.org
---
Changes in v2:
- IRQs should be optional = move EC interrupt to keyboard.
drivers/input/keyboard/cros_ec_keyb.c | 58 ---
drivers/mfd/cros_ec.c | 35 +
include/linux/mfd/cros_ec.h
: Added common function to cros_ec.c]
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Doug Anderson diand...@chromium.org
---
Changes in v2:
- Added common function to cros_ec.c
- Changed to dev_dbg() as per http://crosreview.com/66726
drivers/mfd/cros_ec.c | 18
From: Simon Glass s...@chromium.org
Some commands take a while to execute. Use -EAGAIN to signal this to the
caller.
Signed-off-by: Simon Glass s...@chromium.org
Signed-off-by: Doug Anderson diand...@chromium.org
Acked-by: Lee Jones lee.jo...@linaro.org
---
Changes in v2: None
drivers/mfd
conflicts; documented that no code changes needed
on mainline]
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Doug Anderson diand...@chromium.org
Reviewed-by: Simon Glass s...@chromium.org
---
Changes in v2: None
include/linux/mfd/cros_ec.h | 4 ++--
1 file changed, 2
From: Bill Richardson wfric...@chromium.org
This is some internal structure reorganization / renaming to prepare
for future patches that will add a userspace API to cros_ec. There
should be no visible changes.
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Doug Anderson
.
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Doug Anderson diand...@chromium.org
Acked-by: Lee Jones lee.jo...@linaro.org
Reviewed-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Removed unneeded ret variable.
drivers/i2c/busses/i2c-cros-ec-tunnel.c | 15
From: Bill Richardson wfric...@chromium.org
This comment was incorrect, so update it.
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Simon Glass s...@chromium.org
Signed-off-by: Doug Anderson diand...@chromium.org
Acked-by: Lee Jones lee.jo...@linaro.org
---
Changes in v2
the transport. Before this change:
cros-ec-spi spi2.0: Chrome EC (SPI)
After this change:
cros-ec-spi spi2.0: Chrome EC device registered
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Doug Anderson diand...@chromium.org
Acked-by: Lee Jones lee.jo...@linaro.org
Reviewed
Amit,
Thanks for posting!
On Wed, Jun 18, 2014 at 4:31 AM, Amit Daniel Kachhap
amit.dan...@samsung.com wrote:
This patch register the exynos mct clocksource as the current timer
as it has constant clock rate. This will generate correct udelay for the
exynos platform and avoid using
are doing), so we can properly get the wake-up
condition.
Signed-off-by: Vincent Palatin vpala...@chromium.org
Signed-off-by: Doug Anderson diand...@chromium.org
---
drivers/i2c/busses/i2c-s3c2410.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c
only been compile-tested since I don't have all the
patches needed to make my machine using this i2c driver actually
suspend/resume.
Signed-off-by: Doug Anderson diand...@chromium.org
---
drivers/i2c/busses/i2c-exynos5.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git
Hi,
On Wed, Jun 18, 2014 at 9:54 PM, Doug Anderson diand...@chromium.org wrote:
From: Vincent Palatin vpala...@chromium.org
When the wake-up is triggered by the PMIC RTC, the RTC driver is trying
to read the PMIC interrupt status over I2C and fails because the I2C
controller is not resumed
.
Overall this looks good to me, so once nits above are fixed feel to
add my Reviewed-by. I've also built and booted this patch on
exynos5250-snow and tested that the RTC wakealarm fires and can even
wake the system up (with some additional work that I'll email you
about).
Reviewed-by: Doug Anderson
Simon,
On Tue, Jun 17, 2014 at 8:35 PM, Simon Glass s...@chromium.org wrote:
Hi Doug,
On 16 June 2014 14:39, Doug Anderson diand...@chromium.org wrote:
From: Bill Richardson wfric...@chromium.org
The members of struct cros_ec_device were improperly commented, and
intermixed the private
Simon,
On Tue, Jun 17, 2014 at 8:39 PM, Simon Glass s...@chromium.org wrote:
Hi Doug,
On 16 June 2014 14:39, Doug Anderson diand...@chromium.org wrote:
From: Bill Richardson wfric...@chromium.org
struct cros_ec_device has a superfluous name field. We can get all the
debugging info we need
Simon,
On Tue, Jun 17, 2014 at 8:42 PM, Simon Glass s...@chromium.org wrote:
diff --git a/drivers/input/keyboard/cros_ec_keyb.c
b/drivers/input/keyboard/cros_ec_keyb.c
index 4083796..dc37b6b 100644
--- a/drivers/input/keyboard/cros_ec_keyb.c
+++ b/drivers/input/keyboard/cros_ec_keyb.c
@@
Simon,
On Tue, Jun 17, 2014 at 9:25 PM, Simon Glass s...@chromium.org wrote:
Hi Doug,
On 17 June 2014 21:22, Doug Anderson diand...@chromium.org wrote:
Simon,
On Tue, Jun 17, 2014 at 8:39 PM, Simon Glass s...@chromium.org wrote:
Hi Doug,
On 16 June 2014 14:39, Doug Anderson diand
Simon,
On Tue, Jun 17, 2014 at 8:43 PM, Simon Glass s...@chromium.org wrote:
diff --git a/drivers/mfd/cros_ec_spi.c b/drivers/mfd/cros_ec_spi.c
index 09ca789..4d34f1c 100644
--- a/drivers/mfd/cros_ec_spi.c
+++ b/drivers/mfd/cros_ec_spi.c
@@ -289,21 +289,23 @@ static int
Simon,
On Tue, Jun 17, 2014 at 8:46 PM, Simon Glass s...@chromium.org wrote:
Hi,
On 16 June 2014 14:40, Doug Anderson diand...@chromium.org wrote:
From: Bill Richardson wfric...@chromium.org
When communicating with the EC, the cmd_xfer() function should return the
number of bytes
Daniel,
On Mon, Jun 16, 2014 at 1:52 AM, Daniel Lezcano
daniel.lezc...@linaro.org wrote:
Hi Dough,
thanks for the explanation. I still don't get why it is important to keep
others users of mct traceable because it is quite slow ? May be it is what
you explained here, but I miss the
Tushar,
On Mon, Jun 16, 2014 at 4:19 AM, Tushar Behera trbli...@gmail.com wrote:
On 06/13/2014 10:33 PM, Doug Anderson wrote:
Tushar,
On Tue, Jun 10, 2014 at 10:32 PM, Tushar Behera tusha...@samsung.com wrote:
Peach-pi board has MAX98090 audio codec connected on HSI2C-7 bus.
If you want
Mark,
On Mon, Jun 16, 2014 at 9:51 AM, Mark Brown broo...@kernel.org wrote:
On Mon, Jun 16, 2014 at 09:49:26AM -0700, Doug Anderson wrote:
Yes please. I think there's supposed to be some official ordering of
things. If anyone reading this has a pointer to the official sort
order of things
Kukjin,
On Wed, Jun 11, 2014 at 8:28 AM, Kukjin Kim kgene@samsung.com wrote:
On 06/12/14 00:19, Doug Anderson wrote:
Chander,
On Tue, Jun 10, 2014 at 9:52 PM, Chander Kashyapk.chan...@samsung.com
wrote:
Hi Doug,
On Tue, Jun 10, 2014 at 9:19 PM, Nicolas Pitrenicolas.pi...@linaro.org
Nicolas,
On Mon, Jun 9, 2014 at 1:55 PM, Nicolas Pitre nicolas.pi...@linaro.org wrote:
On Mon, 9 Jun 2014, Kevin Hilman wrote:
On Mon, Jun 9, 2014 at 1:22 PM, Nicolas Pitre nicolas.pi...@linaro.org
wrote:
On Mon, 9 Jun 2014, Andrew Bresticker wrote:
[1] While waiting for the
/291
Signed-off-by: Prathyush K prathyus...@samsung.com
Signed-off-by: Doug Anderson diand...@chromium.org
---
Note that I don't have suspend/resume actually working upstream, but I
see that /sys/bus/spi/drivers/cros-ec-spi/spi2.0/power/wakeup exists
with this patch and doesn't exist without
From: Bill Richardson wfric...@chromium.org
This comment was incorrect, so update it.
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Simon Glass s...@chromium.org
Signed-off-by: Doug Anderson diand...@chromium.org
---
include/linux/mfd/cros_ec.h | 3 +--
1 file changed, 1
This is a batch of cleanup patches picked from the ChromeOS 3.8 kernel
tree and applied to ToT. Most of these patches were authored by Bill
Richardson (CCed). Where appropriate I've squashed patches together,
though I have erred on the side of keeping patches logically distinct
rather than
that will
eventually be used.]
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Doug Anderson diand...@chromium.org
---
drivers/mfd/cros_ec.c | 2 +-
drivers/mfd/cros_ec_i2c.c | 4 +--
drivers/mfd/cros_ec_spi.c | 10 +++
include/linux/mfd/cros_ec.h | 65
From: Bill Richardson wfric...@chromium.org
Preparing the way for the LPC device, which is just a plaform_device without
interrupts.
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Doug Anderson diand...@chromium.org
---
drivers/mfd/cros_ec.c | 26
From: Bill Richardson wfric...@chromium.org
struct cros_ec_device has a superfluous name field. We can get all the
debugging info we need from the existing ec_name and phys_name fields, so
let's take out the extra field.
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Doug
conflicts; documented that no code changes needed
on mainline]
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Doug Anderson diand...@chromium.org
---
include/linux/mfd/cros_ec.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/linux/mfd/cros_ec.h
From: Bill Richardson wfric...@chromium.org
When communicating with the EC, the cmd_xfer() function should return the
number of bytes it received from the EC, or negative on error.
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Doug Anderson diand...@chromium.org
.
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Doug Anderson diand...@chromium.org
---
drivers/i2c/busses/i2c-cros-ec-tunnel.c | 15 +++
drivers/input/keyboard/cros_ec_keyb.c | 14 --
drivers/mfd/cros_ec.c | 32
-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Doug Anderson diand...@chromium.org
---
drivers/mfd/cros_ec_i2c.c | 15 +++
drivers/mfd/cros_ec_spi.c | 26 ++
2 files changed, 25 insertions(+), 16 deletions(-)
diff --git a/drivers/mfd/cros_ec_i2c.c b
From: Bill Richardson wfric...@chromium.org
This is some internal structure reorganization / renaming to prepare
for future patches that will add a userspace API to cros_ec. There
should be no visible changes.
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Doug Anderson
From: Simon Glass s...@chromium.org
Some commands take a while to execute. Use -EAGAIN to signal this to the
caller.
Signed-off-by: Simon Glass s...@chromium.org
Signed-off-by: Doug Anderson diand...@chromium.org
---
drivers/mfd/cros_ec_spi.c | 6 ++
1 file changed, 6 insertions(+)
diff
Tushar,
On Mon, Jun 16, 2014 at 8:36 PM, Tushar Behera trbli...@gmail.com wrote:
On Mon, Jun 16, 2014 at 10:19 PM, Doug Anderson diand...@google.com wrote:
Tushar,
On Mon, Jun 16, 2014 at 4:19 AM, Tushar Behera trbli...@gmail.com wrote:
On 06/13/2014 10:33 PM, Doug Anderson wrote:
Tushar
Daniel,
On Sun, Jun 15, 2014 at 2:18 PM, Daniel Lezcano
daniel.lezc...@linaro.org wrote:
On 06/04/2014 07:30 PM, Doug Anderson wrote:
In (93bfb76 clocksource: exynos_mct: register sched_clock callback) we
supported using the MCT as a scheduler clock. We properly marked
Chander,
On Fri, Jun 13, 2014 at 4:54 AM, Chander Kashyap k.chan...@samsung.com wrote:
This patch is effectively changing the mcpm_entry_point address from
nsbase + 0x1c to nsbase + 0x8
Hence while integrating with mainline u-boot we need to take care for
new mcpm_entry_point address.
With
Tushar,
On Tue, Jun 10, 2014 at 10:32 PM, Tushar Behera tusha...@samsung.com wrote:
Peach-pi board has MAX98090 audio codec connected on HSI2C-7 bus.
If you want to be a stickler about it, peach-pi actually has a
max98091. That requires code changes to the i2c driver, though.
...and
Mark,
On Fri, Jun 13, 2014 at 10:05 AM, Mark Brown broo...@kernel.org wrote:
On Fri, Jun 13, 2014 at 10:03:50AM -0700, Doug Anderson wrote:
On Tue, Jun 10, 2014 at 10:32 PM, Tushar Behera tusha...@samsung.com wrote:
Peach-pi board has MAX98090 audio codec connected on HSI2C-7 bus.
If you
/patch/4346701/ and
https://patchwork.kernel.org/patch/4346711/
Signed-off-by: Doug Anderson diand...@chromium.org
---
arch/arm/boot/dts/exynos5420-peach-pit.dts | 146 +
arch/arm/boot/dts/exynos5800-peach-pi.dts | 146 +
2 files changed, 292
Mark,
On Fri, Jun 13, 2014 at 10:13 AM, Doug Anderson diand...@google.com wrote:
Mark,
On Fri, Jun 13, 2014 at 10:05 AM, Mark Brown broo...@kernel.org wrote:
On Fri, Jun 13, 2014 at 10:03:50AM -0700, Doug Anderson wrote:
On Tue, Jun 10, 2014 at 10:32 PM, Tushar Behera tusha...@samsung.com
Mark,
On Fri, Jun 13, 2014 at 3:04 PM, Mark Brown broo...@kernel.org wrote:
On Fri, Jun 13, 2014 at 02:58:26PM -0700, Doug Anderson wrote:
Anyway, suffice to say that the i2c core needs to be extended to
handle the idea that a single device has more than one compatible
string. I'll leave
Thomas,
On Wed, Jun 4, 2014 at 11:05 AM, Thomas Gleixner t...@linutronix.de wrote:
On Wed, 4 Jun 2014, Doug Anderson wrote:
As we saw in (clocksource: exynos_mct: cache mct upper count), the
time spent reading the MCT shows up fairly high in real-world
profiles. That means that it's worth
.
Respective changes are preposed to spi-s3c64xx.c driver.
@ http://www.spinics.net/lists/linux-samsung-soc/msg32282.html
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Acked-by: Rob Herring r...@kernel.org
Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk
Cc: Doug Anderson
Paul,
On Wed, Jun 11, 2014 at 3:37 AM, Paul Bolle pebo...@tiscali.nl wrote:
On Tue, 2014-05-20 at 09:46 +0100, Lee Jones wrote:
On Wed, 30 Apr 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
This just updates include/linux/mfd/cros_ec_commands.h to match
Chander,
On Tue, Jun 10, 2014 at 9:52 PM, Chander Kashyap k.chan...@samsung.com wrote:
Hi Doug,
On Tue, Jun 10, 2014 at 9:19 PM, Nicolas Pitre nicolas.pi...@linaro.org
wrote:
On Tue, 10 Jun 2014, Doug Anderson wrote:
My S-state knowledge is not strong, but I believe that Lorenzo's
Chander,
On Tue, Jun 10, 2014 at 1:12 AM, Chander Kashyap
chander.kash...@linaro.org wrote:
On 10 June 2014 04:08, Lorenzo Pieralisi lorenzo.pieral...@arm.com wrote:
On Mon, Jun 09, 2014 at 06:03:31PM +0100, Doug Anderson wrote:
[...]
Cold boot and resume from suspend are detected via
Hi,
On Mon, Jun 9, 2014 at 11:48 PM, Shaik Ameer Basha
shaik.sams...@gmail.com wrote:
Hi Kevin,
We tested on 3 peach-pi boards. We are not observing this issue.
Even I tried with the below defconfig mentioned by you. No issues observed.
Naveen / Sylwester,
On Tue, Jun 10, 2014 at 4:00 AM, Naveen Krishna Ch
naveenkrishna...@gmail.com wrote:
Can we support both cs-gpio and cs-gpios for backward compatibility ?
After your change all DTBs using the original pattern will not work with
new kernels any more. At least I would expect
Naveen,
Not a full review, but a few quick things I happened to notice:
On Tue, Jun 10, 2014 at 3:08 AM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
@@ -94,7 +93,6 @@ Example:
spi-max-frequency = 1;
controller-data {
-
Tomasz,
On Tue, Jun 10, 2014 at 12:49 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
This is wrong. The cs-gpios property is supposed to be an array,
indexed by chip select number of SPI devices (indicated by their reg
properties).
Moreover, is there a need to parse this manually in this
Tomasz,
On Tue, Jun 10, 2014 at 12:59 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
On 10.06.2014 21:58, Doug Anderson wrote:
Tomasz,
On Tue, Jun 10, 2014 at 12:49 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
This is wrong. The cs-gpios property is supposed to be an array,
indexed by chip
Javier,
On Tue, Jun 10, 2014 at 1:03 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Yes, I did not have this issue before. However... I installed the latest Peach
pit recovery image you provided me and mainline kernel started to hang on
boot.
I remembered this thread so
Krzystof,
On Mon, Jun 9, 2014 at 3:16 AM, Krzysztof Kozlowski
k.kozlow...@samsung.com wrote:
On pon, 2014-06-09 at 11:37 +0200, Javier Martinez Canillas wrote:
MAX77802 is a PMIC that contains 10 high efficiency Buck regulators,
32 Low-dropout (LDO) regulators, two 32kHz buffered clock
Lorenzo,
On Sat, Jun 7, 2014 at 11:12 AM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
On Fri, Jun 06, 2014 at 10:43:05PM +0100, Doug Anderson wrote:
On exynos mcpm systems the firmware is hardcoded to jump to an address
in SRAM (0x02073000) when secondary CPUs come up. By default
Tomasz,
On Fri, Jun 6, 2014 at 4:41 PM, Mike Turquette mturque...@linaro.org wrote:
Quoting Tomasz Figa (2014-06-05 15:26:31)
On 05.06.2014 22:35, Doug Anderson wrote:
The aclk66_peric clock is a gate clock with a whole bunch of gates
underneath it. This big gate isn't very useful
Kevin and Nicolas,
On Mon, Jun 9, 2014 at 1:27 PM, Kevin Hilman khil...@linaro.org wrote:
Nicolas Pitre nicolas.pi...@linaro.org writes:
On Sat, 7 Jun 2014, Abhilash Kesavan wrote:
Hi Nicolas,
The first man of the incoming cluster enables its snoops via the
power_up_setup function. During
Javier,
On Mon, Jun 9, 2014 at 3:55 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
* The RTC has many subtle differences between the 77686 and 77802.
They expanded it to handle a 200 year timeframe instead of 100 and
that meant that they had to shuffle the bits around
Tushar,
On Thu, Jun 5, 2014 at 9:38 PM, Tushar Behera trbli...@gmail.com wrote:
On 06/06/2014 06:38 AM, Doug Anderson wrote:
Hi,
When I try to boot linuxnext on my exynos5420-peach-pit chromebook I
have problems bringing up extra CPUs:
1. They don't come up
[ ... ]
[1.125030] CPU1
Abhilash,
On Fri, Jun 6, 2014 at 10:36 AM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Hi Doug,
The first change in the kernel (clearing an iRAM location) is needed
because of an unnecessary change that we are carrying in the Chrome
U-boot. There is no reason for us to have the
Abhilash,
On Fri, Jun 6, 2014 at 11:12 AM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Hi Doug,
On Fri, Jun 6, 2014 at 11:32 PM, Doug Anderson diand...@google.com wrote:
Abhilash,
On Fri, Jun 6, 2014 at 10:36 AM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Hi Doug
Abhilash,
On Fri, Jun 6, 2014 at 11:31 AM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Hi Doug,
On Fri, Jun 6, 2014 at 11:50 PM, Doug Anderson diand...@google.com wrote:
Abhilash,
On Fri, Jun 6, 2014 at 11:12 AM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Hi Doug
On Fri, Jun 6, 2014 at 12:09 PM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Hi Doug,
On Sat, Jun 7, 2014 at 12:26 AM, Doug Anderson diand...@google.com wrote:
Abhilash,
On Fri, Jun 6, 2014 at 11:31 AM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Hi Doug,
On Fri, Jun 6
Hi,
On Fri, Jun 6, 2014 at 2:01 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Fri, Jun 06, 2014 at 01:49:11PM -0700, Doug Anderson wrote:
This works and IMHO is much cleaner because it totally removes the
U-Boot dependency. I'll cleanup to not be so insane and post:
diff
is implemented for systems using exynos-mcpm we'll
need to make sure we reinstall our fixed up code after resume. ...but
that's not anything new since IRAM (and thus the address of the
mcpm_entry_point) is lost across suspend/resume anyway.
Signed-off-by: Doug Anderson diand...@chromium.org
---
arch
Hi,
On Fri, Jun 6, 2014 at 1:49 PM, Doug Anderson diand...@google.com wrote:
Are you talking about the re-writing the mcpm entry point address
post-resume ?
Or even (as Andrew points out) just don't use it.
This works and IMHO is much cleaner because it totally removes the
U-Boot
Hi,
To add a few things to Olof's comments:
On Fri, Jun 6, 2014 at 2:49 PM, Olof Johansson o...@lixom.net wrote:
What we can do, though, is to publicly shame you all Google People very
strongly for not making firmware updates in the field safer and easier.
After all you must all know already
Nicolas,
On Fri, Jun 6, 2014 at 3:35 PM, Nicolas Pitre nicolas.pi...@linaro.org wrote:
On Fri, 6 Jun 2014, Doug Anderson wrote:
On exynos mcpm systems the firmware is hardcoded to jump to an address
in SRAM (0x02073000) when secondary CPUs come up. By default the
firmware puts a bunch
Nicolas,
On Fri, Jun 6, 2014 at 3:38 PM, Nicolas Pitre nicolas.pi...@linaro.org wrote:
On Fri, 6 Jun 2014, Doug Anderson wrote:
Note that handling CPU resume in a way that can be updated by RW
firmware is non-trivial and requires some SRAM to be saved across
suspend/resume.
Saved
Mike,
On Fri, Jun 6, 2014 at 3:31 PM, Mike Turquette mturque...@linaro.org wrote:
Anyways, getting back on point, Tomasz was right about the whole clk_get
thing. So I'm happy to take either V1 or V3 of your patch. I will be
submitting a second PR for 3.16 next week and it will include
is implemented for systems using exynos-mcpm we'll
need to make sure we reinstall our fixed up code after resume. ...but
that's not anything new since IRAM (and thus the address of the
mcpm_entry_point) is lost across suspend/resume anyway.
Signed-off-by: Doug Anderson diand...@chromium.org
Vincent,
On Thu, Jun 5, 2014 at 12:55 AM, Vincent Guittot
vincent.guit...@linaro.org wrote:
On 4 June 2014 19:30, Doug Anderson diand...@chromium.org wrote:
From: Mandeep Singh Baines m...@chromium.org
Saves one register read. Note that the upper count only changes every
~178 seconds
Tomasz,
On Thu, Jun 5, 2014 at 4:18 AM, Tomasz Figa tomasz.f...@gmail.com wrote:
On 04.06.2014 20:49, Doug Anderson wrote:
Thomas,
On Wed, Jun 4, 2014 at 11:05 AM, Thomas Gleixner t...@linutronix.de wrote:
On Wed, 4 Jun 2014, Doug Anderson wrote:
As we saw in (clocksource: exynos_mct
Tomasz / Mike,
On Fri, May 30, 2014 at 9:32 AM, Doug Anderson diand...@chromium.org wrote:
Right now if you've got earlyprintk enabled on exynos5420-peach-pit
then you'll get a hang on boot. Here's why:
1. The i2c-s3c2410 driver will probe at subsys_initcall. It will
enable its clock
Tomasz,
On Thu, Jun 5, 2014 at 12:14 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
On 05.06.2014 20:48, Doug Anderson wrote:
Tomasz / Mike,
On Fri, May 30, 2014 at 9:32 AM, Doug Anderson diand...@chromium.org wrote:
Right now if you've got earlyprintk enabled on exynos5420-peach-pit
Tomasz,
On Thu, Jun 5, 2014 at 12:31 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
One more question that just came to my mind: Why it is just the
aclk66_peri and not its children related to UARTs?
Can you re-read out the original patch description and see if it
answers that? Basically: the
) this clock is exported as part of
the common clock bindings. Remove it since there are no in-kernel
device trees using it and no reason anyone out of tree should refer to
it either.
Signed-off-by: Doug Anderson diand...@chromium.org
---
Changes in v3:
- Now just remove aclk66_peric from the tree
Hi,
On Thu, Jun 5, 2014 at 1:10 PM, Doug Anderson diand...@chromium.org wrote:
Hmmm, I think I've convinced myself that your suggestion of just
removing this gate from the table is the right thing to do. Patch
will be coming up soon.
It's here https://patchwork.kernel.org/patch/4308631
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