Fwd: Role of PLL_ENABLE_BIT

2014-07-31 Thread Humberto Naves
-- Forwarded message -- From: Humberto Naves hsna...@gmail.com Date: Thu, Jul 31, 2014 at 11:01 AM Subject: Re: Role of PLL_ENABLE_BIT To: Yadwinder Singh Brar yadi.bra...@gmail.com Cc: linux-samsung-soc linux-samsung-soc@vger.kernel.org, Mike Turquette mturque...@linaro.org

Re: Role of PLL_ENABLE_BIT

2014-07-31 Thread Humberto Naves
Hi Andreas, I guess the original message was not plain text, and majordomo refused to deliver it :-( The signedness is not an issue, if I just use what I sent in the patch, the set_rate function works like a charm. But otherwise, the whole system freezes and I have to reboot the machine. Best,

Re: [PATCHv2 1/5] clk: samsung: exynos5410: Add NULL pointer checks in clock init

2014-07-31 Thread Humberto Naves
Hi, I am bit confused by your response: first you mentioned that I should remove the NULL check for variable np, but later on you suggested that I should rearrange the conditional statement to avoid adding more indentation. My guess is that I should remove that if statement altogether? Regarding

Re: [PATCHv2 4/5] clk: samsung: exynos5410: Add fixed rate clocks

2014-07-31 Thread Humberto Naves
Hi Tomasz, I perfectly see your point. However my question was why you did you decide to postpone Sylwester's? Was there any specific reason? I suppose it would break all the dtb compatibility, but besides that, was there any other reason? Best, Humberto On Thu, Jul 31, 2014 at 2:53 PM, Tomasz

Re: [PATCHv2 5/5] clk: samsung: exynos5410: Added clocks DPLL, EPLL, IPLL, and VPLL

2014-07-31 Thread Humberto Naves
Hi Tomasz, I remember checking these rates on my calculator. You might notice the odd frequency of 45158401Hz (no pun intended) in the EPLL clock. This particular clock frequency was giving me a big headache in a previous project, since it was wrongly listed as 45158400. At first it seems

Re: [PATCHv2 4/5] clk: samsung: exynos5410: Add fixed rate clocks

2014-07-31 Thread Humberto Naves
Hi, On Thu, Jul 31, 2014 at 1:45 PM, Sylwester Nawrocki s.nawro...@samsung.com wrote: Can you explain what is rationale behind this change ? Is it related to suspend/resume ordering ? I had forgotten, but now remember the reason why I did this. If you see the current implementation of

Re: [PATCHv2 5/5] clk: samsung: exynos5410: Added clocks DPLL, EPLL, IPLL, and VPLL

2014-07-31 Thread Humberto Naves
Hi, On Thu, Jul 31, 2014 at 5:19 PM, Tomasz Figa tomasz.f...@gmail.com wrote: I'm not sure I get the idea of the field you're suggesting. If I understand correctly, your intention would be to provide a default frequency if there is no table provided. I don't think there is a need for it,