NAK
In testing we have seen that, when sysmmu of mfc/gscl is used,
the respective IP clock has to be ON, or else it was malfunctioning.
So for smmu_mfcl and smmu_mfcr, the parent should be mfc
so that we make sure the parent is turned on every time sysmmu is accessed.
Same thing applies to gscl al
Hi,
Current clock driver of exynos5250 does not contain sub mux clock
definition for aclk_266 and aclk_333. These sub mux clocks are driven by
output of divider clocks. These sub mux clocks drive the gate clocks
of Gscaler and MFC. Currently Gscaler and MFC gate clocks are
referring to divider
cl
Quoting Prasanna Kumar (2013-03-25 21:26:26)
> From: Prasanna Kumar
No need for the above line.
>
> Gscaler :
>
> 1. For "aclk_300_gscl",following clocks are added
> Mux clocks
> mout_aclk_300_gscl_mid,
> mout_aclk_300_gscl_mid1,
> mo
From: Prasanna Kumar
Gscaler :
1. For "aclk_300_gscl",following clocks are added
Mux clocks
mout_aclk_300_gscl_mid,
mout_aclk_300_gscl_mid1,
mout_aclk_300_gscl
Divider clock
div_aclk300_gscl
Sub-Mux c
