Hi Chanwoo,
On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
This patch adds the mux/divider/gate clock fo CMU_MIF domain which includes
nit: %s/fo/of
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect).
The CMU_MIF domain provides the source clocks for
Hi Pankaj,
On 12/08/2014 08:37 PM, Pankaj Dubey wrote:
Hi Chanwoo,
On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
This patch adds the mux/divider/gate clock fo CMU_MIF domain which includes
nit: %s/fo/of
I'll fix it.
the clocks for DMC(DRAM memory controller) and CCI(Cache
This patch adds the mux/divider/gate clock fo CMU_MIF domain which includes
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect).
The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa
