On 19.05.2014 05:30, Tushar Behera wrote:
On 15 May 2014 19:37, Tomasz Figa t.f...@samsung.com wrote:
Hi Rahul, Tushar,
On 15.05.2014 15:44, Rahul Sharma wrote:
Hi Tushar,
Basically you are adding a new clock-type for Clkout. IMO clkout
is not a special hardware. Existing clock types can
On 15 May 2014 19:37, Tomasz Figa t.f...@samsung.com wrote:
Hi Rahul, Tushar,
On 15.05.2014 15:44, Rahul Sharma wrote:
Hi Tushar,
Basically you are adding a new clock-type for Clkout. IMO clkout
is not a special hardware. Existing clock types can be reused to
support clkout. I see 3 major
Hi Tushar,
Basically you are adding a new clock-type for Clkout. IMO clkout
is not a special hardware. Existing clock types can be reused to
support clkout. I see 3 major problem here:
1) Clkout - (Mux + Gate). You clubbed mux and gate together, and
exposing as a single clock which is something
Hi Rahul, Tushar,
On 15.05.2014 15:44, Rahul Sharma wrote:
Hi Tushar,
Basically you are adding a new clock-type for Clkout. IMO clkout
is not a special hardware. Existing clock types can be reused to
support clkout. I see 3 major problem here:
1) Clkout - (Mux + Gate). You clubbed mux
On 15 May 2014 19:37, Tomasz Figa t.f...@samsung.com wrote:
Hi Rahul, Tushar,
On 15.05.2014 15:44, Rahul Sharma wrote:
Hi Tushar,
Basically you are adding a new clock-type for Clkout. IMO clkout
is not a special hardware. Existing clock types can be reused to
support clkout. I see 3 major
On 05/10/2014 09:21 AM, Pankaj Dubey wrote:
On 05/09/2014 10:00 PM, Tushar Behera wrote:
All SoC in Exynos-series have a clock with name XCLKOUT to provide
debug information about various clocks available in the SoC. The register
controlling the MUX and GATE of this clock is provided within
All SoC in Exynos-series have a clock with name XCLKOUT to provide
debug information about various clocks available in the SoC. The register
controlling the MUX and GATE of this clock is provided within PMU domain.
Since PMU domain can't be dedicatedly mapped by every driver, the register
needs to
On 05/09/2014 10:00 PM, Tushar Behera wrote:
All SoC in Exynos-series have a clock with name XCLKOUT to provide
debug information about various clocks available in the SoC. The register
controlling the MUX and GATE of this clock is provided within PMU domain.
Since PMU domain can't be
