Re: [PATCH 3/3] clk: exynos5410: Added clocks BPLL, DPLL, EPLL, IPLL, MPLL, and VPLL

2014-07-31 Thread Thomas Abraham
Hi Humberto, On Wed, Jul 30, 2014 at 8:06 PM, Humberto Silva Naves hsna...@gmail.com wrote: Added the remaining PLL clocks, and also registered the configuration tables with the PLL coefficients for the supported frequencies. These frequency tables are valid when a 24MHz clock is supplied as

[PATCH 3/3] clk: exynos5410: Added clocks BPLL, DPLL, EPLL, IPLL, MPLL, and VPLL

2014-07-30 Thread Humberto Silva Naves
Added the remaining PLL clocks, and also registered the configuration tables with the PLL coefficients for the supported frequencies. These frequency tables are valid when a 24MHz clock is supplied as the input clock source (which I believe is always the case). Furthermore, the corresponding