On Thu, Dec 15, 2011 at 09:54:15AM +0800, Richard Zhao wrote:
> On Thu, Dec 15, 2011 at 09:46:20AM +0800, Shawn Guo wrote:
> > On Thu, Dec 15, 2011 at 09:02:20AM +0800, Richard Zhao wrote:
> > > On Wed, Dec 14, 2011 at 03:01:19PM +, Dave Martin wrote:
> > > > On Wed, Dec 14, 2011 at 10:05:04PM
On Thu, Dec 15, 2011 at 09:46:20AM +0800, Shawn Guo wrote:
> On Thu, Dec 15, 2011 at 09:02:20AM +0800, Richard Zhao wrote:
> > On Wed, Dec 14, 2011 at 03:01:19PM +, Dave Martin wrote:
> > > On Wed, Dec 14, 2011 at 10:05:04PM +0800, Richard Zhao wrote:
> > > > On Wed, Dec 14, 2011 at 09:26:24PM
On Thu, Dec 15, 2011 at 09:02:20AM +0800, Richard Zhao wrote:
> On Wed, Dec 14, 2011 at 03:01:19PM +, Dave Martin wrote:
> > On Wed, Dec 14, 2011 at 10:05:04PM +0800, Richard Zhao wrote:
> > > On Wed, Dec 14, 2011 at 09:26:24PM +0800, Shawn Guo wrote:
> > > > Hi Dave,
> > > >
> > > > Sorry for
On Wed, Dec 14, 2011 at 03:01:19PM +, Dave Martin wrote:
> On Wed, Dec 14, 2011 at 10:05:04PM +0800, Richard Zhao wrote:
> > On Wed, Dec 14, 2011 at 09:26:24PM +0800, Shawn Guo wrote:
> > > Hi Dave,
> > >
> > > Sorry for that I did not look into previous post to point it out.
> > >
> > > On W
On Wed, Dec 14, 2011 at 10:05:04PM +0800, Richard Zhao wrote:
> On Wed, Dec 14, 2011 at 09:26:24PM +0800, Shawn Guo wrote:
> > Hi Dave,
> >
> > Sorry for that I did not look into previous post to point it out.
> >
> > On Wed, Dec 14, 2011 at 11:39:41AM +, Dave Martin wrote:
> > > The i.MX6 Qu
On Wed, Dec 14, 2011 at 09:26:24PM +0800, Shawn Guo wrote:
> Hi Dave,
>
> Sorry for that I did not look into previous post to point it out.
>
> On Wed, Dec 14, 2011 at 11:39:41AM +, Dave Martin wrote:
> > The i.MX6 Quad SoC will work without the l2x0 L2 cache controller
> > support built into
Hi Dave,
Sorry for that I did not look into previous post to point it out.
On Wed, Dec 14, 2011 at 11:39:41AM +, Dave Martin wrote:
> The i.MX6 Quad SoC will work without the l2x0 L2 cache controller
> support built into the kernel, so this patch removes the dependency
> on CACHE_L2X0 and sel
The i.MX6 Quad SoC will work without the l2x0 L2 cache controller
support built into the kernel, so this patch removes the dependency
on CACHE_L2X0 and selects MIGHT_HAVE_CACHE_L2X0 instead.
This makes the l2x0 support optional, so that it can be turned off
when desired for debugging purposes etc.