Hello Tomasz,
On 04/07/2015 11:28 PM, Tomasz Figa wrote:
>
> Looks good to me. You can consider this Acked-by, as long as Sylwester
> is not opposed to this approach.
>
Thanks a lot, I've posted it as a proper patch now.
> Best regards,
> Tomasz
>
Best regards,
Javier
--
To unsubscribe from
Hi Javier,
On Tue, Apr 7, 2015 at 8:30 PM, Javier Martinez Canillas
wrote:
> Hello Abhilash,
>
> On 04/07/2015 04:38 PM, Abhilash Kesavan wrote:
>>>
>>> [0]
>>> From 78aa551ebcb9a4a7ae9d5581c33e0c0f19fe5ad6 Mon Sep 17 00:00:00 2001
>>> From: Javier Martinez Canillas
>>> Date: Tue, 7 Apr 2015 15:
2015-04-07 16:11 GMT+02:00 Javier Martinez Canillas
:
> From 78aa551ebcb9a4a7ae9d5581c33e0c0f19fe5ad6 Mon Sep 17 00:00:00 2001
> From: Javier Martinez Canillas
> Date: Tue, 7 Apr 2015 15:53:27 +0200
> Subject: [RFC PATCH] clk: exynos5420: Restore GATE_BUS_TOP on suspend
>
> Commit ae43b3289186 ("A
Javier Martinez Canillas writes:
[...]
> Yes, the following patch [0] is enough to make S2R working. If you think
> that is correct then I'll post it as a proper patch then.
[...]
> [0]
> From 78aa551ebcb9a4a7ae9d5581c33e0c0f19fe5ad6 Mon Sep 17 00:00:00 2001
> From: Javier Martinez Canillas
>
Hello Abhilash,
On 04/07/2015 04:38 PM, Abhilash Kesavan wrote:
>>
>> [0]
>> From 78aa551ebcb9a4a7ae9d5581c33e0c0f19fe5ad6 Mon Sep 17 00:00:00 2001
>> From: Javier Martinez Canillas
>> Date: Tue, 7 Apr 2015 15:53:27 +0200
>> Subject: [RFC PATCH] clk: exynos5420: Restore GATE_BUS_TOP on suspend
>>
Hi Javier,
On Tue, Apr 7, 2015 at 7:41 PM, Javier Martinez Canillas
wrote:
> Hello Tomasz,
>
> On 04/07/2015 02:46 PM, Tomasz Figa wrote:
>> 2015-04-07 13:56 GMT+02:00 Javier Martinez Canillas
>> :
>>> So I disabled the sss clock before trying a S2R:
>>>
>>> # devmem 0x10018800 32 0xFFFB
>>>
Hello Abhilash,
On 04/07/2015 04:11 PM, Abhilash Kesavan wrote:
>
> Yes, though it increasingly looks like aclk266_g2d needs to stay ON
> and we should use your patch that keeps it enabled prior to suspend.
>
Indeed, could you please give me some feedback on the latest RFC patch
I shared [0] on
Hello Tomasz,
On 04/07/2015 02:46 PM, Tomasz Figa wrote:
> 2015-04-07 13:56 GMT+02:00 Javier Martinez Canillas
> :
>> So I disabled the sss clock before trying a S2R:
>>
>> # devmem 0x10018800 32 0xFFFB
>> (CLK_SSS in CLK_GATE_IP_G2D is gated)
>>
>> and S2R worked anyways but I see that CLK_GA
Hi Javier,
On Tue, Apr 7, 2015 at 4:29 PM, Javier Martinez Canillas
wrote:
> Hello Abhilash,
>
> On 04/02/2015 02:22 PM, Abhilash Kesavan wrote:
>> Hi,
>>
>> On Thu, Apr 2, 2015 at 4:01 AM, Javier Martinez Canillas
>> wrote:
>>> Hello Sylwester,
>>>
>>> On 04/01/2015 07:31 PM, Sylwester Nawrocki
2015-04-07 13:56 GMT+02:00 Javier Martinez Canillas
:
> So I disabled the sss clock before trying a S2R:
>
> # devmem 0x10018800 32 0xFFFB
> (CLK_SSS in CLK_GATE_IP_G2D is gated)
>
> and S2R worked anyways but I see that CLK_GATE_IP_G2D is reset to
> its default value on S2R so maybe that is wh
On 04/07/2015 12:59 PM, Javier Martinez Canillas wrote:
>
> So IIUC the CG_STATUS0 bits were a red herring and the real problem
> is that the aclk266_g2d needs to be enabled during suspend (although
> we still don't know why).
>
> It seems were are at a dead end now. Without being able to ask the
Hello Abhilash,
On 04/02/2015 02:22 PM, Abhilash Kesavan wrote:
> Hi,
>
> On Thu, Apr 2, 2015 at 4:01 AM, Javier Martinez Canillas
> wrote:
>> Hello Sylwester,
>>
>> On 04/01/2015 07:31 PM, Sylwester Nawrocki wrote:
>>> On 01/04/15 13:44, Javier Martinez Canillas wrote:
On 04/01/2015 01:03
Hi,
On Thu, Apr 2, 2015 at 4:01 AM, Javier Martinez Canillas
wrote:
> Hello Sylwester,
>
> On 04/01/2015 07:31 PM, Sylwester Nawrocki wrote:
>> On 01/04/15 13:44, Javier Martinez Canillas wrote:
>>> On 04/01/2015 01:03 PM, Sylwester Nawrocki wrote:
It's not clear what subsystems affect state
Hello Sylwester,
On 04/01/2015 07:31 PM, Sylwester Nawrocki wrote:
> On 01/04/15 13:44, Javier Martinez Canillas wrote:
>> On 04/01/2015 01:03 PM, Sylwester Nawrocki wrote:
>>> It's not clear what subsystems affect state of the CG_STATUSx registers, it
>>> would be good if we could get more inform
Quoting Krzysztof Kozlowski (2015-04-01 02:16:08)
> 2015-04-01 6:03 GMT+02:00 Kevin Hilman :
> > Abhilash Kesavan writes:
> >
> >> On Wed, Apr 1, 2015 at 2:32 AM, Kevin Hilman wrote:
> >>> Javier Martinez Canillas writes:
> >>>
> >>> [...]
> >>>
> Unfortunately I don't fully understand why
Hello Javier,
On 01/04/15 13:44, Javier Martinez Canillas wrote:
> On 04/01/2015 01:03 PM, Sylwester Nawrocki wrote:
>> On 31/03/15 22:00, Javier Martinez Canillas wrote:
>>> On 03/31/2015 04:38 PM, Abhilash Kesavan wrote:
javier.marti...@collabora.co.uk> wrote:
I had a look at this some
Hello Sylwester,
On 04/01/2015 01:03 PM, Sylwester Nawrocki wrote:
>
> On 31/03/15 22:00, Javier Martinez Canillas wrote:
>> On 03/31/2015 04:38 PM, Abhilash Kesavan wrote:
>>> javier.marti...@collabora.co.uk> wrote:
>
Unfortunately I don't fully understand why this clock needs to be
e
Hello,
On 31/03/15 22:00, Javier Martinez Canillas wrote:
> On 03/31/2015 04:38 PM, Abhilash Kesavan wrote:
>> javier.marti...@collabora.co.uk> wrote:
>>> Unfortunately I don't fully understand why this clock needs to be
>>> enabled. It would be good if someone at Samsung can explain in
>>> more
2015-04-01 6:03 GMT+02:00 Kevin Hilman :
> Abhilash Kesavan writes:
>
>> On Wed, Apr 1, 2015 at 2:32 AM, Kevin Hilman wrote:
>>> Javier Martinez Canillas writes:
>>>
>>> [...]
>>>
Unfortunately I don't fully understand why this clock needs to be
enabled. It would be good if someone at
Abhilash Kesavan writes:
> On Wed, Apr 1, 2015 at 2:32 AM, Kevin Hilman wrote:
>> Javier Martinez Canillas writes:
>>
>> [...]
>>
>>> Unfortunately I don't fully understand why this clock needs to be
>>> enabled. It would be good if someone at Samsung can explain in more
>>> detail what the rea
Hi Kevin,
On Wed, Apr 1, 2015 at 2:32 AM, Kevin Hilman wrote:
> Javier Martinez Canillas writes:
>
> [...]
>
>> Unfortunately I don't fully understand why this clock needs to be
>> enabled. It would be good if someone at Samsung can explain in more
>> detail what the real problem really is.
>
>
Javier Martinez Canillas writes:
[...]
> Unfortunately I don't fully understand why this clock needs to be
> enabled. It would be good if someone at Samsung can explain in more
> detail what the real problem really is.
+1
Maybe Abhilash can shed some light here?
We really should know *why* th
Hello Abhilash,
On 03/31/2015 04:38 PM, Abhilash Kesavan wrote:
> javier.marti...@collabora.co.uk> wrote:
>> On 03/30/2015 06:07 PM, Tomasz Figa wrote:
>> >
>> > If look-up speed is important here, maybe all the relevant clocks
>> > could be looked up once at initialization time and just prepared
Hello Tomasz,
Thanks a lot for your feedback.
On 03/30/2015 06:07 PM, Tomasz Figa wrote:
> Hi Javier,
>
> Please see my comments inline.
>
> 2015-03-31 0:53 GMT+09:00 Javier Martinez Canillas
> :
> [snip]
>> diff --git a/drivers/clk/samsung/clk-exynos5420.c
>> b/drivers/clk/samsung/clk-exynos5
Hi Javier,
Please see my comments inline.
2015-03-31 0:53 GMT+09:00 Javier Martinez Canillas
:
[snip]
> diff --git a/drivers/clk/samsung/clk-exynos5420.c
> b/drivers/clk/samsung/clk-exynos5420.c
> index 07d666cc6a29..2d39b629144a 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/driver
Commit ae43b3289186 ("ARM: 8202/1: dmaengine: pl330: Add runtime Power
Management support v12") added pm support for the pl330 dma driver but
it makes the clock for the Exynos5420 MDMA0 DMA controller to be gated
during suspend and this clock needs to remain enabled in order to make
the system resu
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