[PATCH 4/7] ARM: GIC: move gic_chip_data structure declaration to header

[Changhwan Youn]

Since Samsung EXYNOS4210 cannot support register banking in GIC,
so needs to update CPU interface base address.
The 'gic_chip_data' is used for it, this patch moves gic_chip_data
structure declaraton to arch/arm/include/asm/hardware/gic.h to use
it.

Cc: Russell King rmk+ker...@arm.linux.org.uk
Signed-off-by: Changhwan Youn chaos.y...@samsung.com
---
 arch/arm/common/gic.c   |6 --
 arch/arm/include/asm/hardware/gic.h |6 ++
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 4ddd0a6..23564ed 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -38,12 +38,6 @@ static DEFINE_SPINLOCK(irq_controller_lock);
 /* Address of GIC 0 CPU interface */
 void __iomem *gic_cpu_base_addr __read_mostly;
 
-struct gic_chip_data {
-   unsigned int irq_offset;
-   void __iomem *dist_base;
-   void __iomem *cpu_base;
-};
-
 /*
  * Supported arch specific GIC irq extension.
  * Default make them NULL.
diff --git a/arch/arm/include/asm/hardware/gic.h 
b/arch/arm/include/asm/hardware/gic.h
index 0691f9d..435d3f8 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -41,6 +41,12 @@ void gic_secondary_init(unsigned int);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
 void gic_enable_ppi(unsigned int);
+
+struct gic_chip_data {
+   unsigned int irq_offset;
+   void __iomem *dist_base;
+   void __iomem *cpu_base;
+};
 #endif
 
 #endif
-- 
1.7.1

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[PATCH 0/7] ARM: EXYNOS4: Adds External GIC

[Changhwan Youn]

This patch adds implementation External GIC on EXYNOS4 SoC.

Note: need to update timer codes for supporting old type of
EXYNOS4 SoCs.

[PATCH 1/7] ARM: EXYNOS4: Add external GIC io memory mapping
[PATCH 2/7] ARM: EXYNOS4: modify interrupt mappings for external GIC
[PATCH 3/7] ARM: EXYNOS4: set the affinity of mct1 interrupt using IRQ_MCT_L1
[PATCH 4/7] ARM: GIC: move gic_chip_data structure declaration to header
[PATCH 5/7] ARM: EXYNOS4: Add support external GIC
[PATCH 6/7] ARM: EXYNOS4: Remove clock event timers using ARM private timers
[PATCH 7/7] ARM: EXYNOS4: Add chained enrty/exit function to uart interrupt 
handler
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[PATCH 2/7] ARM: EXYNOS4: modify interrupt mappings for external GIC

[Changhwan Youn]

To support external GIC needs to update mapping of interrupt number.
This patch modifies it for external GIC and accordingly removes
the unused code.

Signed-off-by: Changhwan Youn chaos.y...@samsung.com
---
 arch/arm/mach-exynos4/cpu.c   |8 --
 arch/arm/mach-exynos4/include/mach/irqs.h |  188 ++---
 2 files changed, 93 insertions(+), 103 deletions(-)

diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 6a1ed74..fa33294 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -167,14 +167,6 @@ void __init exynos4_init_irq(void)
 
for (irq = 0; irq  MAX_COMBINER_NR; irq++) {
 
-   /*
-* From SPI(0) to SPI(39) and SPI(51), SPI(53) are
-* connected to the interrupt combiner. These irqs
-* should be initialized to support cascade interrupt.
-*/
-   if ((irq = 40)  !(irq == 51)  !(irq == 53))
-   continue;
-
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
COMBINER_IRQ(irq, 0));
combiner_cascade_irq(irq, IRQ_SPI(irq));
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h 
b/arch/arm/mach-exynos4/include/mach/irqs.h
index 5d03730..e497ea2 100644
--- a/arch/arm/mach-exynos4/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -25,34 +25,100 @@
 
 #define IRQ_SPI(x) S5P_IRQ(x+32)
 
-#define IRQ_MCT1   IRQ_SPI(35)
-
-#define IRQ_EINT0  IRQ_SPI(40)
-#define IRQ_EINT1  IRQ_SPI(41)
-#define IRQ_EINT2  IRQ_SPI(42)
-#define IRQ_EINT3  IRQ_SPI(43)
-#define IRQ_USB_HSOTG  IRQ_SPI(44)
-#define IRQ_USB_HOST   IRQ_SPI(45)
-#define IRQ_MODEM_IF   IRQ_SPI(46)
-#define IRQ_ROTATORIRQ_SPI(47)
-#define IRQ_JPEG   IRQ_SPI(48)
-#define IRQ_2D IRQ_SPI(49)
-#define IRQ_PCIE   IRQ_SPI(50)
-#define IRQ_MCT0   IRQ_SPI(51)
-#define IRQ_MFCIRQ_SPI(52)
-#define IRQ_AUDIO_SS   IRQ_SPI(54)
-#define IRQ_AC97   IRQ_SPI(55)
-#define IRQ_SPDIF  IRQ_SPI(56)
-#define IRQ_KEYPAD IRQ_SPI(57)
-#define IRQ_INTFEEDCTRL_SSSIRQ_SPI(58)
-#define IRQ_SLIMBUSIRQ_SPI(59)
-#define IRQ_PMUIRQ_SPI(60)
-#define IRQ_TSIIRQ_SPI(61)
-#define IRQ_SATA   IRQ_SPI(62)
-#define IRQ_GPSIRQ_SPI(63)
+#define IRQ_EINT0  IRQ_SPI(16)
+#define IRQ_EINT1  IRQ_SPI(17)
+#define IRQ_EINT2  IRQ_SPI(18)
+#define IRQ_EINT3  IRQ_SPI(19)
+#define IRQ_EINT4  IRQ_SPI(20)
+#define IRQ_EINT5  IRQ_SPI(21)
+#define IRQ_EINT6  IRQ_SPI(22)
+#define IRQ_EINT7  IRQ_SPI(23)
+#define IRQ_EINT8  IRQ_SPI(24)
+#define IRQ_EINT9  IRQ_SPI(25)
+#define IRQ_EINT10 IRQ_SPI(26)
+#define IRQ_EINT11 IRQ_SPI(27)
+#define IRQ_EINT12 IRQ_SPI(28)
+#define IRQ_EINT13 IRQ_SPI(29)
+#define IRQ_EINT14 IRQ_SPI(30)
+#define IRQ_EINT15 IRQ_SPI(31)
+#define IRQ_EINT16_31  IRQ_SPI(32)
+
+#define IRQ_PDMA0  IRQ_SPI(35)
+#define IRQ_PDMA1  IRQ_SPI(36)
+#define IRQ_TIMER0_VIC IRQ_SPI(37)
+#define IRQ_TIMER1_VIC IRQ_SPI(38)
+#define IRQ_TIMER2_VIC IRQ_SPI(39)
+#define IRQ_TIMER3_VIC IRQ_SPI(40)
+#define IRQ_TIMER4_VIC IRQ_SPI(41)
+#define IRQ_MCT_L0 IRQ_SPI(42)
+#define IRQ_WDTIRQ_SPI(43)
+#define IRQ_RTC_ALARM  IRQ_SPI(44)
+#define IRQ_RTC_TICIRQ_SPI(45)
+#define IRQ_GPIO_XBIRQ_SPI(46)
+#define IRQ_GPIO_XAIRQ_SPI(47)
+#define IRQ_MCT_L1 IRQ_SPI(48)
+
+#define IRQ_UART0  IRQ_SPI(52)
+#define IRQ_UART1  IRQ_SPI(53)
+#define IRQ_UART2  IRQ_SPI(54)
+#define IRQ_UART3  IRQ_SPI(55)
+#define IRQ_UART4  IRQ_SPI(56)
+#define IRQ_MCT_G0 IRQ_SPI(57)
+#define IRQ_IICIRQ_SPI(58)
+#define IRQ_IIC1   IRQ_SPI(59)
+#define IRQ_IIC2   IRQ_SPI(60)
+#define IRQ_IIC3   IRQ_SPI(61)
+#define IRQ_IIC4   IRQ_SPI(62)
+#define IRQ_IIC5   IRQ_SPI(63)
+#define IRQ_IIC6   IRQ_SPI(64)
+#define IRQ_IIC7   IRQ_SPI(65)
+
+#define IRQ_USB_HOST   IRQ_SPI(70)
+#define IRQ_USB_HSOTG  IRQ_SPI(71)
+#define IRQ_MODEM_IF   IRQ_SPI(72)
+#define IRQ_HSMMC0 IRQ_SPI(73)
+#define IRQ_HSMMC1 IRQ_SPI(74)
+#define IRQ_HSMMC2 IRQ_SPI(75)
+#define IRQ_HSMMC3 IRQ_SPI(76)
+
+#define IRQ_MIPICSI0   IRQ_SPI(78)
+
+#define IRQ_MIPICSI1   IRQ_SPI(80)
+

[PATCH 5/7] ARM: EXYNOS4: Add support external GIC

[Changhwan Youn]

For full support of power modes, this patch adds implementation
external GIC on EXYNOS4.

External GIC of Exynos4 cannot support register banking so
several interrupt related code for CPU1 should be different
from that of CPU0.

Signed-off-by: Changhwan Youn chaos.y...@samsung.com
---
 arch/arm/mach-exynos4/cpu.c  |   10 
 arch/arm/mach-exynos4/include/mach/entry-macro.S |5 
 arch/arm/mach-exynos4/include/mach/map.h |1 +
 arch/arm/mach-exynos4/platsmp.c  |   27 +-
 4 files changed, 42 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index fa33294..40a866c 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -16,6 +16,7 @@
 
 #include asm/proc-fns.h
 #include asm/hardware/cache-l2x0.h
+#include asm/hardware/gic.h
 
 #include plat/cpu.h
 #include plat/clock.h
@@ -159,11 +160,20 @@ void __init exynos4_init_clocks(int xtal)
exynos4_setup_clocks();
 }
 
+static void exynos4_gic_irq_eoi(struct irq_data *d)
+{
+   struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
+
+   gic_data-cpu_base = S5P_VA_GIC_CPU +
+   (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+}
+
 void __init exynos4_init_irq(void)
 {
int irq;
 
gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+   gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi;
 
for (irq = 0; irq  MAX_COMBINER_NR; irq++) {
 
diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S 
b/arch/arm/mach-exynos4/include/mach/entry-macro.S
index d8f38c2..4fad076 100644
--- a/arch/arm/mach-exynos4/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S
@@ -10,6 +10,7 @@
 */
 
 #include mach/hardware.h
+#include mach/map.h
 #include asm/hardware/gic.h
 
.macro  disable_fiq
@@ -18,6 +19,10 @@
.macro  get_irqnr_preamble, base, tmp
ldr \base, =gic_cpu_base_addr
ldr \base, [\base]
+   mrc p15, 0, \tmp, c0, c0, 5
+   and \tmp, \tmp, #3
+   cmp \tmp, #1
+   addeq   \base, \base, #EXYNOS4_GIC_BANK_OFFSET
.endm
 
.macro  arch_ret_to_user, tmp1, tmp2
diff --git a/arch/arm/mach-exynos4/include/mach/map.h 
b/arch/arm/mach-exynos4/include/mach/map.h
index 9d5d797..2339a70 100644
--- a/arch/arm/mach-exynos4/include/mach/map.h
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -63,6 +63,7 @@
 
 #define EXYNOS4_PA_GIC_CPU 0x1048
 #define EXYNOS4_PA_GIC_DIST0x1049
+#define EXYNOS4_GIC_BANK_OFFSET0x8000
 
 #define EXYNOS4_PA_COREPERI0x1050
 #define EXYNOS4_PA_TWD 0x10500600
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index c5e65a0..decf528 100644
--- a/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -58,6 +58,31 @@ static void __iomem *scu_base_addr(void)
 
 static DEFINE_SPINLOCK(boot_lock);
 
+static void __cpuinit exynos4_gic_secondary_init(void)
+{
+   void __iomem *dist_base = S5P_VA_GIC_DIST +
+(EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+   void __iomem *cpu_base = S5P_VA_GIC_CPU +
+   (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+   int i;
+
+   /*
+* Deal with the banked PPI and SGI interrupts - disable all
+* PPI interrupts, ensure all SGI interrupts are enabled.
+*/
+   __raw_writel(0x, dist_base + GIC_DIST_ENABLE_CLEAR);
+   __raw_writel(0x, dist_base + GIC_DIST_ENABLE_SET);
+
+   /*
+* Set priority on PPI and SGI interrupts
+*/
+   for (i = 0; i  32; i += 4)
+   __raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
+
+   __raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK);
+   __raw_writel(1, cpu_base + GIC_CPU_CTRL);
+}
+
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
/*
@@ -65,7 +90,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
 * core (e.g. timer irq), then they will not have been enabled
 * for us: do so
 */
-   gic_secondary_init(0);
+   exynos4_gic_secondary_init();
 
/*
 * let the primary processor know we're out of the
-- 
1.7.1

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[PATCH 6/7] ARM: EXYNOS4: Remove clock event timers using ARM private timers

[Changhwan Youn]

External GIC cannot support PPI (Private Peripheral Interrupt) for
ARM private timers. Thus MCT should be selected as clock event timers
by default.

Signed-off-by: Changhwan Youn chaos.y...@samsung.com
---
 arch/arm/mach-exynos4/Kconfig|3 +-
 arch/arm/mach-exynos4/Makefile   |7 +-
 arch/arm/mach-exynos4/cpu.c  |2 +-
 arch/arm/mach-exynos4/include/mach/entry-macro.S |6 -
 arch/arm/mach-exynos4/include/mach/irqs.h|2 -
 arch/arm/mach-exynos4/localtimer.c   |   26 --
 arch/arm/mach-exynos4/time.c |  303 --
 7 files changed, 4 insertions(+), 345 deletions(-)
 delete mode 100644 arch/arm/mach-exynos4/localtimer.c
 delete mode 100644 arch/arm/mach-exynos4/time.c

diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index 1435fc3..0aca083 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -16,7 +16,8 @@ config CPU_EXYNOS4210
  Enable EXYNOS4210 CPU support
 
 config EXYNOS4_MCT
-   bool Kernel timer support by MCT
+   bool
+   default y
help
  Use MCT (Multi Core Timer) as kernel timers
 
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 60fe5ec..c3c70ab 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -20,12 +20,7 @@ obj-$(CONFIG_CPU_IDLE)   += cpuidle.o
 
 obj-$(CONFIG_SMP)  += platsmp.o headsmp.o
 
-ifeq ($(CONFIG_EXYNOS4_MCT),y)
-obj-y  += mct.o
-else
-obj-y  += time.o
-obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
-endif
+obj-$(CONFIG_EXYNOS4_MCT)  += mct.o
 
 obj-$(CONFIG_HOTPLUG_CPU)  += hotplug.o
 
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 40a866c..d153309 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -172,7 +172,7 @@ void __init exynos4_init_irq(void)
 {
int irq;
 
-   gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+   gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi;
 
for (irq = 0; irq  MAX_COMBINER_NR; irq++) {
diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S 
b/arch/arm/mach-exynos4/include/mach/entry-macro.S
index 4fad076..d7a1e28 100644
--- a/arch/arm/mach-exynos4/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S
@@ -80,10 +80,4 @@
/* As above, this assumes that irqstat and base are preserved.. 
*/
 
.macro test_for_ltirq, irqnr, irqstat, base, tmp
-   bic \irqnr, \irqstat, #0x1c00
-   mov \tmp, #0
-   cmp \irqnr, #29
-   moveq   \tmp, #1
-   streq   \irqstat, [\base, #GIC_CPU_EOI]
-   cmp \tmp, #0
.endm
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h 
b/arch/arm/mach-exynos4/include/mach/irqs.h
index e497ea2..250427f 100644
--- a/arch/arm/mach-exynos4/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -19,8 +19,6 @@
 
 #define IRQ_PPI(x) S5P_IRQ(x+16)
 
-#define IRQ_LOCALTIMER IRQ_PPI(13)
-
 /* SPI: Shared Peripheral Interrupt */
 
 #define IRQ_SPI(x) S5P_IRQ(x+32)
diff --git a/arch/arm/mach-exynos4/localtimer.c 
b/arch/arm/mach-exynos4/localtimer.c
deleted file mode 100644
index 6bf3d0a..000
--- a/arch/arm/mach-exynos4/localtimer.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* linux/arch/arm/mach-exynos4/localtimer.c
- *
- * Cloned from linux/arch/arm/mach-realview/localtimer.c
- *
- *  Copyright (C) 2002 ARM Ltd.
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include linux/clockchips.h
-
-#include asm/irq.h
-#include asm/localtimer.h
-
-/*
- * Setup the local clock events for a CPU.
- */
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
-   evt-irq = IRQ_LOCALTIMER;
-   twd_timer_setup(evt);
-   return 0;
-}
diff --git a/arch/arm/mach-exynos4/time.c b/arch/arm/mach-exynos4/time.c
deleted file mode 100644
index 9a74294..000
--- a/arch/arm/mach-exynos4/time.c
+++ /dev/null
@@ -1,303 +0,0 @@
-/* linux/arch/arm/mach-exynos4/time.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS4 (and compatible) HRT support
- * PWM 2/4 is used for this feature
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include linux/sched.h
-#include linux/interrupt.h
-#include linux/irq.h
-#include linux/err.h
-#include linux/clk.h

[PATCH] mmc: dw_mmc: protect a sequence of request and request-done.

[Seungwon Jeon]

Response timeout(RTO), Response crc error(RCRC) and Response error(RE)
signals come with command done(CD) and can be raised preceding command
done(CD). That is these error interrupts and CD can be handled in
separate dw_mci_interrupt(). If mmc_request_done() is called because of
response timeout before command done is occured, next request can be
sent, but CD of current request is not finished. This can bring about
a broken sequence of request and request-done.

And Data error interrupt(DRTO, DCRC, SBE, EBE) and data transfer
over(DTO) are same reanson.

Signed-off-by: Seungwon Jeon tgih@samsung.com
---
 drivers/mmc/host/dw_mmc.c |5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 1ca830c..22be372 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -1202,7 +1202,6 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
host-cmd_status = status;
smp_wmb();
set_bit(EVENT_CMD_COMPLETE, host-pending_events);
-   tasklet_schedule(host-tasklet);
}
 
if (pending  DW_MCI_DATA_ERROR_FLAGS) {
@@ -1211,7 +1210,9 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
host-data_status = status;
smp_wmb();
set_bit(EVENT_DATA_ERROR, host-pending_events);
-   tasklet_schedule(host-tasklet);
+   if (!(pending  (SDMMC_INT_DTO | SDMMC_INT_DCRC |
+SDMMC_INT_SBE | SDMMC_INT_EBE)))
+   tasklet_schedule(host-tasklet);
}
 
if (pending  SDMMC_INT_DATA_OVER) {
-- 
1.7.1

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[PATCH] mmc: dw_mmc: set the card_width bit per card.

[Seungwon Jeon]

This patch sets the card_width bit of CTYPE for the corresponding card.

CTYPE[31] and CTYPE[16] correspond respectively to card[15] and card[0]
for 8-bit mode. And CTYPE[15] and CTYPE[0] correspond respectively to
card[15] and CTYPE[0] for 1-bit or 4-bit mode.

Signed-off-by: Seungwon Jeon tgih@samsung.com
---
 drivers/mmc/host/dw_mmc.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 66dcddb..1ca830c 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -574,7 +574,7 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot)
}
 
/* Set the current slot bus width */
-   mci_writel(host, CTYPE, slot-ctype);
+   mci_writel(host, CTYPE, (slot-ctype  slot-id));
 }
 
 static void dw_mci_start_request(struct dw_mci *host,
-- 
1.7.1

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Re: [PATCH] mmc: dw_mmc: protect a sequence of request and request-done.

[Will Newton]

On Mon, Jun 20, 2011 at 9:24 AM, Seungwon Jeon tgih@samsung.com wrote:
 Response timeout(RTO), Response crc error(RCRC) and Response error(RE)
 signals come with command done(CD) and can be raised preceding command
 done(CD). That is these error interrupts and CD can be handled in
 separate dw_mci_interrupt(). If mmc_request_done() is called because of
 response timeout before command done is occured, next request can be
 sent, but CD of current request is not finished. This can bring about
 a broken sequence of request and request-done.

 And Data error interrupt(DRTO, DCRC, SBE, EBE) and data transfer
 over(DTO) are same reanson.

 Signed-off-by: Seungwon Jeon tgih@samsung.com

Acked-by: Will Newton will.new...@imgtec.com
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Re: [PATCH] mmc: dw_mmc: set the card_width bit per card.

[Will Newton]

On Mon, Jun 20, 2011 at 9:23 AM, Seungwon Jeon tgih@samsung.com wrote:
 This patch sets the card_width bit of CTYPE for the corresponding card.

 CTYPE[31] and CTYPE[16] correspond respectively to card[15] and card[0]
 for 8-bit mode. And CTYPE[15] and CTYPE[0] correspond respectively to
 card[15] and CTYPE[0] for 1-bit or 4-bit mode.

 Signed-off-by: Seungwon Jeon tgih@samsung.com

Acked-by: Will Newton will.new...@imgtec.com
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Re: [PATCH v2 1/5] ARM: EXYNOS4: Change clock name for FIMD

[Sylwester Nawrocki]

Hi JinGoo,

On 06/20/2011 09:14 AM, JinGoo Han wrote:
 Hi, Sylwester Nawrocki.
 I appreciate your review and suggestion.
 
 Please, refer to the LCD contoller clock table as follows:

ok, thanks for the update. 

  - s3c2440 uses 's3c2410fb.c', not 's3c-fb.c' since  LCD controller IP is 
 different.
However, s3c2443 uses 's3c-fb.c'. So I add s3c2443 to table instead of 
 s3c2440.

Yes, I was aware of that. My bad to put s3c2440 in the table.

  - s3c6410 has SCLK_LCD, but, clock name is not defined.
  - Exynos4 does not use name HCLK.
 
   | LCD controller||
   | (IP core) clock   | LCD pixel clock|
 --++---+
 s3c2443   |  HCLK (lcd)   | x  |  DISPCLK (display-if) |
 --++---+
 s3c6410   |  HCLK (lcd)   | x  |  SCLK_LCD  (N/A)  |
 --++---+
 s5pc100   |  HCLK (lcd)   | x  |  SCLK_LCD  (sclk_lcd) |
 --++---+
 s5pv210   |  HCLK_DSYS (lcd)  | x  |  SCLK_FIMD (sclk_fimd)|
 --+---++
 exynos4   |  ACLK_160 (fimd)  | O  |  SCLK_FIMD (sclk_fimd)|
 --++---+
 ^^^
In mach-exynos4/clock.c this clock is described as ACLK_133 (lcd)

 
 s3c2443, s3c6410, s5pc100 and s5pv210 don't use 'sclk_lcd' or 'sclk_fimd'.
 'lcd' clock is also used to generate the LCD pixel clock.
 
 My point is that LCD controller clock should be named lcd for consistence.

Yes, I agree. After thinking about it a bit more I was going to propose
that too.

 If there is not mux for lcd pixel clock in case of exynos4, sclk_fimd will 
 be set
 in machine directory.

OK, you patch for s3c-fb driver looks like a significant improvement comparing
to the original one. But I think we should remove the callback into machine
code.
The driver could just directly be doing clk_get(dev, sclk_fimd); If this
succeeds and clksel option is not set in the IP variant then the driver should
treat sclk_fimd as pixel clock, i.e. it will set its frequency and enable it.
It should not care about setting the parent for sclk_fimd, this should
be done before s3c-fb probe is called.

The problem is that I don't know what to do it the bootloader does not set
a parent clock for sclk_fimd.. 
The board code could just get sclk_fimd and set mout_mpll as its parent, like
it's done in your patch:
[PATCH v2 3/5] ARM: EXYNOS4: Add platform device and helper functions for FIMD
(except passing a pointer to the driver).

However there have been objections to put such things in the board code in
the past.
In case of camera clocks we used to have internally a function in the machine
file setting the parent clocks, until bootloader was modified to configure them.


 
 As you mentioned, I also think that we need to create two clock connection ids
 such as  bus_ck, pix_ck in order to use SCLK_LCD or SCLK_FIMD.
 Moreover, 'lcd' in s5pv210 should be changed to 'fimd' according to s5pv210 
 datasheet.

Yeah, that makes sense.

 However, it requires many works to convert.

It's a bit laborious. But it's doable.

 
 So, I think that 'two clock connection ids' patch would be submitted later,
 after committing the patches that I submitted on last Friday.

I agree with that, given that the callback is removed from the platform data
structure.
We need to get ourselves onto path of migration to the device tree and IMHO
adding more callbacks to board code is a step in opposite direction.


Thanks, 
S. 
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Re: [PATCH v2 1/5] ARM: EXYNOS4: Change clock name for FIMD

[daeinki]

Hi, Mr. Han and Sylwester.
below is my opinion.

JinGoo Han 쓴 글:
 Hi, Sylwester Nawrocki.
 I appreciate your review and suggestion.
 
 Please, refer to the LCD contoller clock table as follows:
  - s3c2440 uses 's3c2410fb.c', not 's3c-fb.c' since  LCD controller IP is 
 different.
However, s3c2443 uses 's3c-fb.c'. So I add s3c2443 to table instead of 
 s3c2440.
  - s3c6410 has SCLK_LCD, but, clock name is not defined.
  - Exynos4 does not use name HCLK.
 
   | LCD controller||
   | (IP core) clock   | LCD pixel clock|
 --++---+
 s3c2443   |  HCLK (lcd)   | x  |  DISPCLK (display-if) |
 --++---+
 s3c6410   |  HCLK (lcd)   | x  |  SCLK_LCD  (N/A)  |
 --++---+
 s5pc100   |  HCLK (lcd)   | x  |  SCLK_LCD  (sclk_lcd) |
 --++---+
 s5pv210   |  HCLK_DSYS (lcd)  | x  |  SCLK_FIMD (sclk_fimd)|
 --+---++
 exynos4   |  ACLK_160 (fimd)  | O  |  SCLK_FIMD (sclk_fimd)|
 --++---+
 
 s3c2443, s3c6410, s5pc100 and s5pv210 don't use 'sclk_lcd' or 'sclk_fimd'.
 'lcd' clock is also used to generate the LCD pixel clock.
 
 My point is that LCD contoroller clock should be named lcd for consistence.
 If there is not mux for lcd pixel clock in case of exynos4, sclk_fimd will 
 be set
 in machine directory.
 
 As you mentioned, I also think that we need to create two clock connection ids
 such as  bus_ck, pix_ck in order to use SCLK_LCD or SCLK_FIMD.
 Moreover, 'lcd' in s5pv210 should be changed to 'fimd' according to s5pv210 
 datasheet.
 However, it requres many works to convert.
 
 So, I think that 'two clock connection ids' patch would be submitted later,
 after committing the patches that I submitted on last Friday.
 
 
 On 06/19/2011 23:39 AM, Sylwester Nawrocki wrote:
 Hi Jingoo,

 On 06/17/2011 03:01 PM, Jingoo Han wrote:
 This patch changes clock name for FIMD from fimd to lcd.

 Signed-off-by: Jingoo Hanjg1@samsung.com
 ---
   arch/arm/mach-exynos4/clock.c |4 ++--
   1 files changed, 2 insertions(+), 2 deletions(-)

 diff --git a/arch/arm/mach-exynos4/clock.c
 b/arch/arm/mach-exynos4/clock.c index 871f9d5..12e6853 100644
 --- a/arch/arm/mach-exynos4/clock.c
 +++ b/arch/arm/mach-exynos4/clock.c
 @@ -433,12 +433,12 @@ static struct clk init_clocks_off[] = {
 .enable  = exynos4_clk_ip_cam_ctrl,
 .ctrlbit = (1  3),
}, {
 -  .name  = fimd,
 +  .name  = lcd,
 .id  = 0,
 .enable  = exynos4_clk_ip_lcd0_ctrl,
 I think we're inevitably heading to disaster with this kind of implicit
 clocks mapping across various SoCs. It is getting harder to figure out
 what's going on with every new SoC support added.
 The fimd clock in this case (exynos4) is not really a HCLK clock, like,
 for instance, in case of s5pv210. But after this patch they would both be
 named lcd. You cannot set frequency on fimd clock, it is only for
 gating the bus clock to the LCD controller, right ? Whereas lcd
 indicates HCLK on s5pv210 and can also be used to generate the LCD pixel
 clock.
 I know you are not going to use lcd clock in the driver for setting up
 the pixel clock frequency on exynos4 but it's all confusing this way.

 I dug in the datasheets and it looks like the LCD controller's IP main
 (bus) clock is named HCLK there and lcd throughout the code.

   | LCD controller||
   | (IP core) clock   | LCD pixel clock|
 --++---+
 s3c2440   |  HCLK (lcd)   | x  |  N/A ?|
 --++---+
 s3c6410   |  HCLK (lcd)   | x  |  LCD  |
 --++---+
 s5pc100   |  HCLK (lcd)   | x  |  SCLK_LCD  (sclk_lcd) |
 --++---+
 s5pv210   |  HCLK(_DSYS) (lcd)| x  |  SCLK_FIMD (sclk_fimd)|
 --+---+---+
 exynos4   |  ?| -  |  SCLK_FIMD?(sclk_fimd)|
 --++---+

 I think we could try to create two clock connection ids to the framebuffer
 device in the first place, e.g. bus_ck, pix_ck.
 And then think about how handle that in the driver.

 But this requires conversion to the omap-style clock registration method,
 something like in the attached patch. The patch is only for s5pv210 and
 and compile tested only as I didn't have any board to test it here.
 It's based on for-next branch at http://tinyurl.com/6yzravy I think there
 might be more issues to convert the old s3c24xx platforms, nevertheless
 the attached patch should not affect them.

 --
 Regards,
 

[PATCH 0/6] Add basic device tree support for Samsung's Exynos4 platform

[Thomas Abraham]

This patch series adds a basic device tree based boot for Samsung's Exynos4
platforms and specifically for smdkv310 board. Device tree based driver
probe is added for uart, sdhci and watchdog drivers. These patches
enable booting to console on smdkv310 board with some of the devices
initialized with data from the device tree.

This patch series is based on
git.secretlab.ca/git/linux-2.6.git devicetree/test

and depends on the following patches which are not yet available in
the devicetree/test branch.

1. [PATCH] ARM: EXYNOS4: Fix card detection for sdhci 0 and 2
[http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg04704.html]

2. [PATCH] ARM: EXYNOS4: Fix missing S5P_VA_AUDSS definition
[http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg04866.html]

3. [PATCH 0/9] Add clkdev support for Samsung platforms
[http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg04874.html]

4. Consolidate the clkdev header files
[http://patchwork.ozlabs.org/patch/97862/]

Thomas Abraham (6):
  serial: samsung: Keep a copy of platform data in driver's private data
  serial: samsung: Add device tree support for s5pv210 uart driver
  watchdog: s3c2410: Add support for device tree based probe
  mmc: sdhci-s3c: Add support for device tree based probe
  arm: dts: Add nodes in smdkv310 device tree source file
  arm: exynos4: Add a new Exynos4 device tree enabled machine

 Documentation/devicetree/bindings/arm/samsung.txt  |3 +-
 .../bindings/tty/serial/samsung_uart.txt   |   50 +++
 .../devicetree/bindings/watchdog/samsung-wdt.txt   |   12 ++
 arch/arm/boot/dts/exynos4-smdkv310.dts |  135 +++-
 arch/arm/mach-exynos4/Kconfig  |   11 ++
 arch/arm/mach-exynos4/Makefile |1 +
 arch/arm/mach-exynos4/mach-exynos4-dt.c|   94 ++
 drivers/mmc/host/sdhci-s3c.c   |   11 ++
 drivers/tty/serial/s5pv210.c   |   39 +-
 drivers/tty/serial/samsung.c   |  114 -
 drivers/tty/serial/samsung.h   |4 +-
 drivers/watchdog/s3c2410_wdt.c |   10 ++
 12 files changed, 473 insertions(+), 11 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/tty/serial/samsung_uart.txt
 create mode 100644 Documentation/devicetree/bindings/watchdog/samsung-wdt.txt
 create mode 100644 arch/arm/mach-exynos4/mach-exynos4-dt.c

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[PATCH 1/6] serial: samsung: Keep a copy of platform data in driver's private data

[Thomas Abraham]

The driver depends on pdev-dev.platform_data to retrive information
about the platform data even after the initialization. To add device
tree support, this has to be changed in way that the platform data
is avialable from driver's private data. This patch adds support
for keeping a copy of the plaform data in s3c24xx_uart_info and using
it when needed after the initialization.

Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
 drivers/tty/serial/s5pv210.c |   12 ++--
 drivers/tty/serial/samsung.c |   24 
 drivers/tty/serial/samsung.h |4 +++-
 3 files changed, 33 insertions(+), 7 deletions(-)

diff --git a/drivers/tty/serial/s5pv210.c b/drivers/tty/serial/s5pv210.c
index d6b2423..3b2021a 100644
--- a/drivers/tty/serial/s5pv210.c
+++ b/drivers/tty/serial/s5pv210.c
@@ -27,9 +27,13 @@
 static int s5pv210_serial_setsource(struct uart_port *port,
struct s3c24xx_uart_clksrc *clk)
 {
-   struct s3c2410_uartcfg *cfg = port-dev-platform_data;
+   struct s3c24xx_uart_port *ourport;
+   struct s3c2410_uartcfg *cfg;
unsigned long ucon = rd_regl(port, S3C2410_UCON);
 
+   ourport = container_of(port, struct s3c24xx_uart_port, port);
+   cfg = ourport-info-cfg;
+
if ((cfg-clocks_size) == 1)
return 0;
 
@@ -50,9 +54,13 @@ static int s5pv210_serial_setsource(struct uart_port *port,
 static int s5pv210_serial_getsource(struct uart_port *port,
struct s3c24xx_uart_clksrc *clk)
 {
-   struct s3c2410_uartcfg *cfg = port-dev-platform_data;
+   struct s3c24xx_uart_port *ourport;
+   struct s3c2410_uartcfg *cfg;
u32 ucon = rd_regl(port, S3C2410_UCON);
 
+   ourport = container_of(port, struct s3c24xx_uart_port, port);
+   cfg = ourport-info-cfg;
+
clk-divisor = 1;
 
if ((cfg-clocks_size) == 1)
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index 7ead421..77d900f 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -42,6 +42,7 @@
 #include linux/delay.h
 #include linux/clk.h
 #include linux/cpufreq.h
+#include linux/slab.h
 
 #include asm/irq.h
 
@@ -169,10 +170,13 @@ static inline struct s3c24xx_uart_info 
*s3c24xx_port_to_info(struct uart_port *p
 
 static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port 
*port)
 {
+   struct s3c24xx_uart_port *ourport;
+
if (port-dev == NULL)
return NULL;
 
-   return (struct s3c2410_uartcfg *)port-dev-platform_data;
+   ourport = container_of(port, struct s3c24xx_uart_port, port);
+   return ourport-info-cfg;
 }
 
 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
@@ -1053,7 +1057,7 @@ static int s3c24xx_serial_init_port(struct 
s3c24xx_uart_port *ourport,
struct platform_device *platdev)
 {
struct uart_port *port = ourport-port;
-   struct s3c2410_uartcfg *cfg;
+   struct s3c2410_uartcfg *cfg = platdev-dev.platform_data;
struct resource *res;
int ret;
 
@@ -1062,14 +1066,24 @@ static int s3c24xx_serial_init_port(struct 
s3c24xx_uart_port *ourport,
if (platdev == NULL)
return -ENODEV;
 
-   cfg = s3c24xx_dev_to_cfg(platdev-dev);
-
if (port-mapbase != 0)
return 0;
 
+   if (cfg) {
+   memcpy((void *)info-cfg, cfg, sizeof(struct s3c2410_uartcfg));
+   info-cfg.clocks = kzalloc(sizeof(struct s3c24xx_uart_clksrc) *
+   cfg-clocks_size, GFP_KERNEL);
+   if (!info-cfg.clocks)
+   return -ENOMEM;
+   memcpy(info-cfg.clocks, cfg-clocks,
+   sizeof(struct s3c24xx_uart_clksrc) * cfg-clocks_size);
+   }
+
+   cfg = info-cfg;
if (cfg-hwport  CONFIG_SERIAL_SAMSUNG_UARTS) {
printk(KERN_ERR %s: port %d bigger than %d\n, __func__,
   cfg-hwport, CONFIG_SERIAL_SAMSUNG_UARTS);
+   kfree(info-cfg.clocks);
return -ERANGE;
}
 
@@ -1181,11 +1195,13 @@ EXPORT_SYMBOL_GPL(s3c24xx_serial_probe);
 int __devexit s3c24xx_serial_remove(struct platform_device *dev)
 {
struct uart_port *port = s3c24xx_dev_to_port(dev-dev);
+   struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 
if (port) {
s3c24xx_serial_cpufreq_deregister(to_ourport(port));
device_remove_file(dev-dev, dev_attr_clock_source);
uart_remove_one_port(s3c24xx_uart_drv, port);
+   kfree(info-cfg.clocks);
}
 
return 0;
diff --git a/drivers/tty/serial/samsung.h b/drivers/tty/serial/samsung.h
index a69d9a5..4f2f6f5 100644
--- a/drivers/tty/serial/samsung.h
+++ b/drivers/tty/serial/samsung.h
@@ -24,6 +24,9 @@ struct s3c24xx_uart_info {
 
unsigned inthas_divslot:1;

[PATCH 4/6] mmc: sdhci-s3c: Add support for device tree based probe

[Thomas Abraham]

Add of_match_table to enable sdhci-s3c driver to be probed when a compatible
sdhci device node is found in device tree.

Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
This is temporary patch. sdhci-s3c driver has to be moved to sdhci-pltfm
based driver.

 drivers/mmc/host/sdhci-s3c.c |   11 +++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 69e3ee3..5ccbee0 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -629,6 +629,16 @@ static int sdhci_s3c_resume(struct platform_device *dev)
 #define sdhci_s3c_resume NULL
 #endif
 
+#ifdef CONFIG_OF
+static const struct of_device_id s3c_sdhci_match[] = {
+   { .compatible = samsung,s3c-sdhci },
+   {},
+};
+MODULE_DEVICE_TABLE(of, s3c_sdhci_match);
+#else
+#define s3c_sdhci_match NULL
+#endif
+
 static struct platform_driver sdhci_s3c_driver = {
.probe  = sdhci_s3c_probe,
.remove = __devexit_p(sdhci_s3c_remove),
@@ -637,6 +647,7 @@ static struct platform_driver sdhci_s3c_driver = {
.driver = {
.owner  = THIS_MODULE,
.name   = s3c-sdhci,
+   .of_match_table = s3c_sdhci_match,
},
 };
 
-- 
1.6.6.rc2

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[PATCH 5/6] arm: dts: Add nodes in smdkv310 device tree source file

[Thomas Abraham]

Include device tree nodes for watchdog timer, sdhci instance 0 and 1,
and uart instances 0 to 3.

Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
 arch/arm/boot/dts/exynos4-smdkv310.dts |  135 +++-
 1 files changed, 133 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4-smdkv310.dts 
b/arch/arm/boot/dts/exynos4-smdkv310.dts
index dd6c80a..721563f 100644
--- a/arch/arm/boot/dts/exynos4-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4-smdkv310.dts
@@ -1,11 +1,142 @@
+/*
+ * Samsung's Exynos4 based smdkv310 board device tree source.
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ * Copyright (c) 2010-2011 Linaro Ltd.
+ * www.linaro.org
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
 /dts-v1/;
 /include/ skeleton.dtsi
 
 / {
model = Samsung Exynos4 SMDKV310 eval board;
-   compatible = samsung,smdkv310, samsung,s5pv310;
+   compatible = samsung,smdkv310, samsung,s5pv310, 
samsung,exynos4210;
 
memory {
-   reg = 0x4000 0x0800;
+   reg = 0x4000 0x8000;
+   };
+
+   chosen {
+   bootargs = root=/dev/mmcblk0p1 rootfstype=ext3 rootwait 
console=ttySAC1,115200;
+   };
+
+   soc {
+   #address-cells = 1;
+   #size-cells = 1;
+   interrupt-parent = intc;
+   compatible = simple-bus;
+   ranges;
+
+   intc:interrupt-controller@0x10501000 {
+   compatible = samsung,exynos4-gic,arm,cortex-a9-gic;
+   #interrupt-cells = 1;
+   interrupt-controller;
+   reg = 0x10501000 0x1000, 0x10500100 0x100;
+   irq-start = 61;
+   };
+
+   watchdog@0x1006 {
+   compatible = samsung,s3c2410-wdt;
+   reg = 0x1006 0x400;
+   interrupts = 552;
+   };
+
+   sdhci@0x1253 {
+   compatible = samsung,s3c-sdhci;
+   reg = 0x1253 0x1000;
+   interrupts = 362;
+   };
+
+   sdhci@0x1251 {
+   compatible = samsung,s3c-sdhci;
+   reg = 0x1251 0x1000;
+   interrupts = 360;
+   };
+
+   serial@0x1380 {
+   compatible = samsung,s5pv210-uart;
+   reg = 0x1380 0x100;
+   interrupts = 16 18 17;
+   fifosize = 256;
+   hwport = 0;
+   flags = 0;
+   uart_flags = 0;
+   has_fracval = 1;
+   ucon_default = 0x3c5;
+   ulcon_default = 0x3;
+   ufcon_default = 0x111;
+   uart_clksrc0 {
+   clk_name = uclk1;
+   divisor = 1;
+   min_baud = 0;
+   max_baud = 0;
+   };
+   };
+
+   serial@0x1381 {
+   compatible = samsung,s5pv210-uart;
+   reg = 0x1381 0x100;
+   interrupts = 20 22 21;
+   fifosize = 64;
+   hwport = 1;
+   flags = 0;
+   uart_flags = 0;
+   has_fracval = 1;
+   ucon_default = 0x3c5;
+   ulcon_default = 0x3;
+   ufcon_default = 0x111;
+   uart_clksrc0 {
+   clk_name = uclk1;
+   divisor = 1;
+   min_baud = 0;
+   max_baud = 0;
+   };
+   };
+
+   serial@0x1382 {
+   compatible = samsung,s5pv210-uart;
+   reg = 0x1382 0x100;
+   interrupts = 24 26 25;
+   fifosize = 16;
+   hwport = 1;
+   flags = 0;
+   uart_flags = 0;
+   has_fracval = 1;
+   ucon_default = 0x3c5;
+   ulcon_default = 0x3;
+   ufcon_default = 0x111;
+   uart_clksrc0 {
+   clk_name = uclk1;
+   divisor = 1;
+   min_baud = 0;
+   max_baud = 0;
+   };
+   };
+
+   

[PATCH 6/6] arm: exynos4: Add a new Exynos4 device tree enabled machine

[Thomas Abraham]

Basic Exynos4 machine with device tree support that can boot on a Exynos4
based smdkv310 board and bring up the console.

Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
 Documentation/devicetree/bindings/arm/samsung.txt |3 +-
 arch/arm/mach-exynos4/Kconfig |   11 +++
 arch/arm/mach-exynos4/Makefile|1 +
 arch/arm/mach-exynos4/mach-exynos4-dt.c   |   94 +
 4 files changed, 108 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-exynos4/mach-exynos4-dt.c

diff --git a/Documentation/devicetree/bindings/arm/samsung.txt 
b/Documentation/devicetree/bindings/arm/samsung.txt
index 594cb97..80d29bb 100644
--- a/Documentation/devicetree/bindings/arm/samsung.txt
+++ b/Documentation/devicetree/bindings/arm/samsung.txt
@@ -4,6 +4,7 @@ Samsung Exynos4 S5PV310 SoC based SMDKV310 eval board
 Samsung's Exynos4 family of application processors.
 
 Required root node properties:
-- compatible = samsung,smdkv310,samsung,s5pv310
+- compatible = samsung,smdkv310,samsung,s5pv310, samsung,exynos4210'.
 (a) samsung,smdkv310 - for Samsung's SMDKV310 eval board.
 (b) samsung,s5pv310  - for boards based on S5PV310 SoC.
+   (c) samsung,exynos4210 - for boards based on Exynos4210 processor.
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index 1435fc3..412e0c5 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -186,6 +186,17 @@ config MACH_NURI
help
  Machine support for Samsung Mobile NURI Board.
 
+config MACH_EXYNOS4_DT
+   bool Samsung's Exynos4 Machine with DT support
+   select CPU_EXYNOS4210
+   select USE_OF
+   select S3C_DEV_WDT
+   select S3C_DEV_HSMMC
+   select S3C_DEV_HSMMC2
+   select EXYNOS4_SETUP_SDHCI
+   help
+ Machine support for Samsung Exynos4 machine with device tree enabled.
+
 endmenu
 
 comment Configuration for HSMMC bus width
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 60fe5ec..6491e5b 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_MACH_SMDKV310)   += mach-smdkv310.o
 obj-$(CONFIG_MACH_ARMLEX4210)  += mach-armlex4210.o
 obj-$(CONFIG_MACH_UNIVERSAL_C210)  += mach-universal_c210.o
 obj-$(CONFIG_MACH_NURI)+= mach-nuri.o
+obj-$(CONFIG_MACH_EXYNOS4_DT)  += mach-exynos4-dt.o
 
 # device support
 
diff --git a/arch/arm/mach-exynos4/mach-exynos4-dt.c 
b/arch/arm/mach-exynos4/mach-exynos4-dt.c
new file mode 100644
index 000..34267d8
--- /dev/null
+++ b/arch/arm/mach-exynos4/mach-exynos4-dt.c
@@ -0,0 +1,94 @@
+/*
+ * Samsung's Exynos4210 device tree enabled machine.
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ * Copyright (c) 2010-2011 Linaro Ltd.
+ * www.linaro.org
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include linux/serial_core.h
+#include linux/platform_device.h
+#include linux/io.h
+#include linux/of_platform.h
+#include linux/irq.h
+
+#include asm/mach/arch.h
+#include asm/mach-types.h
+
+#include plat/regs-serial.h
+#include plat/exynos4.h
+#include plat/cpu.h
+#include plat/sdhci.h
+
+#include mach/map.h
+
+static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
+   .cd_type= S3C_SDHCI_CD_INTERNAL,
+   .clk_type   = S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
+   .max_width  = 8,
+   .host_caps  = MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
+   .cd_type= S3C_SDHCI_CD_INTERNAL,
+   .clk_type   = S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
+   .max_width  = 8,
+   .host_caps  = MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
+   OF_DEV_AUXDATA(samsung,s3c-sdhci, EXYNOS4_PA_HSMMC(2),
+   s3c-sdhci.2, s3c_hsmmc2_def_platdata),
+   OF_DEV_AUXDATA(samsung,s3c-sdhci, EXYNOS4_PA_HSMMC(0),
+   s3c-sdhci.0, s3c_hsmmc0_def_platdata),
+   OF_DEV_AUXDATA(samsung,s5pv210-uart, S5P_PA_UART0,
+   s5pv210-uart.0, NULL),
+   OF_DEV_AUXDATA(samsung,s5pv210-uart, S5P_PA_UART1,
+   s5pv210-uart.1, NULL),
+   {},
+};
+
+static void __init exynos4_dt_map_io(void)
+{
+   s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+   s3c24xx_init_clocks(2400);
+}
+
+static const struct of_device_id intc_of_match[] __initconst = {
+   { .compatible = samsung,exynos4-gic, },

[PATCH 1/3] ARM: S5P64X0: Add HSMMC setup for host Controller

[Rajeshwari Shinde]

From: rajeshwari.s rajeshwar...@samsung.com

Adds support for HSMMC for S5P64X0 platform, performs
setup for host controller and related GPIO.

Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Rajeshwari.S rajeshwar...@samsung.com
---
 arch/arm/mach-s5p64x0/Kconfig|   31 
 arch/arm/mach-s5p64x0/Makefile   |2 +
 arch/arm/mach-s5p64x0/setup-sdhci-gpio.c |  121 ++
 arch/arm/mach-s5p64x0/setup-sdhci.c  |   54 +
 4 files changed, 208 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
 create mode 100644 arch/arm/mach-s5p64x0/setup-sdhci.c

diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index 017af4c..ed823b0 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -26,6 +26,17 @@ config S5P64X0_SETUP_I2C1
help
  Common setup code for i2c bus 1.
 
+config S5P64X0_SETUP_SDHCI
+   bool
+   select S5P64X0_SETUP_SDHCI_GPIO
+   help
+ Internal helper functions for S5P64X0 based SDHCI systems
+
+config S5P64X0_SETUP_SDHCI_GPIO
+   bool
+   help
+ Common setup code for SDHCI gpio.
+
 # machine support
 
 config MACH_SMDK6440
@@ -34,11 +45,15 @@ config MACH_SMDK6440
select S3C_DEV_I2C1
select S3C_DEV_RTC
select S3C_DEV_WDT
+   select S3C_DEV_HSMMC
+   select S3C_DEV_HSMMC1
+   select S3C_DEV_HSMMC2
select S3C64XX_DEV_SPI
select SAMSUNG_DEV_ADC
select SAMSUNG_DEV_PWM
select SAMSUNG_DEV_TS
select S5P64X0_SETUP_I2C1
+   select S5P64X0_SETUP_SDHCI
help
  Machine support for the Samsung SMDK6440
 
@@ -48,12 +63,28 @@ config MACH_SMDK6450
select S3C_DEV_I2C1
select S3C_DEV_RTC
select S3C_DEV_WDT
+   select S3C_DEV_HSMMC
+   select S3C_DEV_HSMMC1
+   select S3C_DEV_HSMMC2
select S3C64XX_DEV_SPI
select SAMSUNG_DEV_ADC
select SAMSUNG_DEV_PWM
select SAMSUNG_DEV_TS
select S5P64X0_SETUP_I2C1
+   select S5P64X0_SETUP_SDHCI
help
  Machine support for the Samsung SMDK6450
 
+menu Use 8-bit SDHCI bus width
+
+config S5P64X0_SD_CH1_8BIT
+   bool SDHCI Channel 1 (Slot 1)
+   depends on MACH_SMDK6450 || MACH_SMDK6440
+   default n
+   help
+ Support SDHCI Channel 1 8-bit bus.
+ If selected, Channel 2 is disabled.
+
+endmenu
+
 endif
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
index ae6bf6f..60ff9b4 100644
--- a/arch/arm/mach-s5p64x0/Makefile
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -28,3 +28,5 @@ obj-y += dev-audio.o
 obj-$(CONFIG_S3C64XX_DEV_SPI)  += dev-spi.o
 
 obj-$(CONFIG_S5P64X0_SETUP_I2C1)   += setup-i2c1.o
+obj-$(CONFIG_S5P64X0_SETUP_SDHCI)  += setup-sdhci.o
+obj-$(CONFIG_S5P64X0_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c 
b/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
new file mode 100644
index 000..31541b3
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
@@ -0,0 +1,121 @@
+/* linux/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * S5P64X0 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include linux/platform_device.h
+#include linux/io.h
+
+#include mach/gpio.h
+#include mach/regs-gpio.h
+
+#include plat/gpio-cfg.h
+#include plat/sdhci.h
+
+
+void s5p6440_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
+{
+   struct s3c_sdhci_platdata *pdata = dev-dev.platform_data;
+
+   /* Set all the necessary GPG pins to special-function 2 */
+   s3c_gpio_cfgrange_nopull(S5P6440_GPG(0), 2 + width, S3C_GPIO_SFN(2));
+
+   /* Set GPG[6] pin to special-function 2 - MMC0 CDn */
+   if (pdata-cd_type == S3C_SDHCI_CD_INTERNAL) {
+   s3c_gpio_setpull(S5P6440_GPG(6), S3C_GPIO_PULL_UP);
+   s3c_gpio_cfgpin(S5P6440_GPG(6), S3C_GPIO_SFN(2));
+   }
+}
+
+void s5p6440_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
+{
+   struct s3c_sdhci_platdata *pdata = dev-dev.platform_data;
+
+   /* Set GPH[0:1] pins to special-function 2 - CLK and CMD */
+   s3c_gpio_cfgrange_nopull(S5P6440_GPH(0), 2 , S3C_GPIO_SFN(2));
+
+   switch (width) {
+   case 8:
+   /* Set data pins GPH[6:9] special-function 2 */
+   s3c_gpio_cfgrange_nopull(S5P6440_GPH(6), 4, S3C_GPIO_SFN(2));
+   case 4:
+   /* set data pins GPH[2:5] special-function 2 */
+   s3c_gpio_cfgrange_nopull(S5P6440_GPH(2), 4, S3C_GPIO_SFN(2));
+   default:
+   

[PATCH 3/3] ARM: S5P64X0: Enable SDHCI support

[Rajeshwari Shinde]

From: rajeshwari.s rajeshwar...@samsung.com

Enables SDHCI supports for S5P6440 and S5P6450.

Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Rajeshwari.S rajeshwar...@samsung.com
---
 arch/arm/mach-s5p64x0/mach-smdk6440.c |   27 +++
 arch/arm/mach-s5p64x0/mach-smdk6450.c |   27 +++
 2 files changed, 54 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c 
b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 2d559f1..78c744f 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -23,6 +23,7 @@
 #include linux/clk.h
 #include linux/gpio.h
 #include linux/pwm_backlight.h
+#include linux/mmc/host.h
 
 #include asm/mach/arch.h
 #include asm/mach/map.h
@@ -46,6 +47,7 @@
 #include plat/adc.h
 #include plat/ts.h
 #include plat/s5p-time.h
+#include plat/sdhci.h
 
 #define SMDK6440_UCON_DEFAULT  (S3C2410_UCON_TXILEVEL |\
S3C2410_UCON_RXILEVEL | \
@@ -141,6 +143,28 @@ static struct platform_device *smdk6440_devices[] 
__initdata = {
s5p6440_device_iis,
s3c_device_timer[1],
smdk6440_backlight_device,
+   s3c_device_hsmmc0,
+   s3c_device_hsmmc1,
+   s3c_device_hsmmc2,
+};
+
+static struct s3c_sdhci_platdata smdk6440_hsmmc0_pdata __initdata = {
+   .cd_type= S3C_SDHCI_CD_NONE,
+   .clk_type   = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct s3c_sdhci_platdata smdk6440_hsmmc1_pdata __initdata = {
+   .cd_type= S3C_SDHCI_CD_INTERNAL,
+#if defined(CONFIG_S5P64X0_SD_CH1_8BIT)
+   .max_width  = 8,
+   .host_caps  = MMC_CAP_8_BIT_DATA,
+#endif
+   .clk_type   = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct s3c_sdhci_platdata smdk6440_hsmmc2_pdata __initdata = {
+   .cd_type= S3C_SDHCI_CD_NONE,
+   .clk_type   = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
 
 static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = {
@@ -194,6 +218,9 @@ static void __init smdk6440_machine_init(void)
i2c_register_board_info(1, smdk6440_i2c_devs1,
ARRAY_SIZE(smdk6440_i2c_devs1));
 
+   s3c_sdhci0_set_platdata(smdk6440_hsmmc0_pdata);
+   s3c_sdhci1_set_platdata(smdk6440_hsmmc1_pdata);
+   s3c_sdhci2_set_platdata(smdk6440_hsmmc2_pdata);
platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices));
 }
 
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c 
b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index d19c469..099ca20 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -23,6 +23,7 @@
 #include linux/clk.h
 #include linux/gpio.h
 #include linux/pwm_backlight.h
+#include linux/mmc/host.h
 
 #include asm/mach/arch.h
 #include asm/mach/map.h
@@ -46,6 +47,7 @@
 #include plat/adc.h
 #include plat/ts.h
 #include plat/s5p-time.h
+#include plat/sdhci.h
 
 #define SMDK6450_UCON_DEFAULT  (S3C2410_UCON_TXILEVEL |\
S3C2410_UCON_RXILEVEL | \
@@ -159,9 +161,31 @@ static struct platform_device *smdk6450_devices[] 
__initdata = {
s5p6450_device_iis0,
s3c_device_timer[1],
smdk6450_backlight_device,
+   s3c_device_hsmmc0,
+   s3c_device_hsmmc1,
+   s3c_device_hsmmc2,
/* s5p6450_device_spi0 will be added */
 };
 
+static struct s3c_sdhci_platdata smdk6450_hsmmc0_pdata __initdata = {
+   .cd_type= S3C_SDHCI_CD_NONE,
+   .clk_type   = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct s3c_sdhci_platdata smdk6450_hsmmc1_pdata __initdata = {
+   .cd_type= S3C_SDHCI_CD_NONE,
+#if defined(CONFIG_S5P64X0_SD_CH1_8BIT)
+   .max_width  = 8,
+   .host_caps  = MMC_CAP_8_BIT_DATA,
+#endif
+   .clk_type   = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct s3c_sdhci_platdata smdk6450_hsmmc2_pdata __initdata = {
+   .cd_type= S3C_SDHCI_CD_NONE,
+   .clk_type   = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
 static struct s3c2410_platform_i2c s5p6450_i2c0_data __initdata = {
.flags  = 0,
.slave_addr = 0x10,
@@ -213,6 +237,9 @@ static void __init smdk6450_machine_init(void)
i2c_register_board_info(1, smdk6450_i2c_devs1,
ARRAY_SIZE(smdk6450_i2c_devs1));
 
+   s3c_sdhci0_set_platdata(smdk6450_hsmmc0_pdata);
+   s3c_sdhci1_set_platdata(smdk6450_hsmmc1_pdata);
+   s3c_sdhci2_set_platdata(smdk6450_hsmmc2_pdata);
platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices));
 }
 
-- 
1.7.0.4

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[PATCH 2/3] ARM: S5P64X0: Initialize default SDHCI devices and platform data

[Rajeshwari Shinde]

From: rajeshwari.s rajeshwar...@samsung.com

Adds initialization of the default sdhci devices and platform
data for S5P6440 and S5P6450.

Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Rajeshwari.S rajeshwar...@samsung.com
---
 arch/arm/mach-s5p64x0/cpu.c|9 +++
 arch/arm/plat-samsung/include/plat/sdhci.h |   78 
 2 files changed, 87 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s5p64x0/cpu.c b/arch/arm/mach-s5p64x0/cpu.c
index a5c0095..c9da808 100644
--- a/arch/arm/mach-s5p64x0/cpu.c
+++ b/arch/arm/mach-s5p64x0/cpu.c
@@ -38,6 +38,7 @@
 #include plat/s5p6440.h
 #include plat/s5p6450.h
 #include plat/adc-core.h
+#include plat/sdhci.h
 
 /* Initial IO mappings */
 
@@ -109,6 +110,10 @@ void __init s5p6440_map_io(void)
/* initialize any device information early */
s3c_adc_setname(s3c64xx-adc);
 
+   s5p6440_default_sdhci0();
+   s5p6440_default_sdhci1();
+   s5p6440_default_sdhci2();
+
iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
 }
@@ -118,6 +123,10 @@ void __init s5p6450_map_io(void)
/* initialize any device information early */
s3c_adc_setname(s3c64xx-adc);
 
+   s5p6450_default_sdhci0();
+   s5p6450_default_sdhci1();
+   s5p6450_default_sdhci2();
+
iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
 }
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h 
b/arch/arm/plat-samsung/include/plat/sdhci.h
index 058e096..0882291 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -126,6 +126,12 @@ extern void exynos4_setup_sdhci0_cfg_gpio(struct 
platform_device *, int w);
 extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
 extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
+extern void s5p6440_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
+extern void s5p6440_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
+extern void s5p6440_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
+extern void s5p6450_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
+extern void s5p6450_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
+extern void s5p6450_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
 
 /* S3C2416 SDHCI setup */
 
@@ -390,4 +396,76 @@ static inline void exynos4_default_sdhci3(void) { }
 
 #endif /* CONFIG_EXYNOS4_SETUP_SDHCI */
 
+/* S5P64X0 SDHCI setup */
+#ifdef CONFIG_S5P64X0_SETUP_SDHCI
+extern char *s5p64x0_hsmmc_clksrcs[4];
+
+extern void s5p64x0_setup_sdhci_cfg_card(struct platform_device *dev,
+   void __iomem *r,
+   struct mmc_ios *ios,
+   struct mmc_card *card);
+
+static inline void s5p6440_default_sdhci0(void)
+{
+#ifdef CONFIG_S3C_DEV_HSMMC
+   s3c_hsmmc0_def_platdata.clocks = s5p64x0_hsmmc_clksrcs;
+   s3c_hsmmc0_def_platdata.cfg_gpio = s5p6440_setup_sdhci0_cfg_gpio;
+   s3c_hsmmc0_def_platdata.cfg_card = s5p64x0_setup_sdhci_cfg_card;
+#endif /* CONFIG_S3C_DEV_HSMMC */
+}
+
+static inline void s5p6440_default_sdhci1(void)
+{
+#ifdef CONFIG_S3C_DEV_HSMMC1
+   s3c_hsmmc1_def_platdata.clocks = s5p64x0_hsmmc_clksrcs;
+   s3c_hsmmc1_def_platdata.cfg_gpio = s5p6440_setup_sdhci1_cfg_gpio;
+   s3c_hsmmc1_def_platdata.cfg_card = s5p64x0_setup_sdhci_cfg_card;
+#endif /* CONFIG_S3C_DEV_HSMMC1 */
+}
+
+static inline void s5p6440_default_sdhci2(void)
+{
+#ifdef CONFIG_S3C_DEV_HSMMC2
+   s3c_hsmmc2_def_platdata.clocks = s5p64x0_hsmmc_clksrcs;
+   s3c_hsmmc2_def_platdata.cfg_gpio = s5p6440_setup_sdhci2_cfg_gpio;
+   s3c_hsmmc2_def_platdata.cfg_card = s5p64x0_setup_sdhci_cfg_card;
+#endif /* CONFIG_S3C_DEV_HSMMC2 */
+}
+
+static inline void s5p6450_default_sdhci0(void)
+{
+#ifdef CONFIG_S3C_DEV_HSMMC
+   s3c_hsmmc0_def_platdata.clocks = s5p64x0_hsmmc_clksrcs;
+   s3c_hsmmc0_def_platdata.cfg_gpio = s5p6450_setup_sdhci0_cfg_gpio;
+   s3c_hsmmc0_def_platdata.cfg_card = s5p64x0_setup_sdhci_cfg_card;
+#endif /* CONFIG_S3C_DEV_HSMMC */
+}
+
+static inline void s5p6450_default_sdhci1(void)
+{
+#ifdef CONFIG_S3C_DEV_HSMMC1
+   s3c_hsmmc1_def_platdata.clocks = s5p64x0_hsmmc_clksrcs;
+   s3c_hsmmc1_def_platdata.cfg_gpio = s5p6450_setup_sdhci1_cfg_gpio;
+   s3c_hsmmc1_def_platdata.cfg_card = s5p64x0_setup_sdhci_cfg_card;
+#endif /* CONFIG_S3C_DEV_HSMMC1 */
+}
+
+static inline void s5p6450_default_sdhci2(void)
+{
+#ifdef CONFIG_S3C_DEV_HSMMC2
+   s3c_hsmmc2_def_platdata.clocks = s5p64x0_hsmmc_clksrcs;
+   s3c_hsmmc2_def_platdata.cfg_gpio = s5p6450_setup_sdhci2_cfg_gpio;
+   

Re: [PATCH 1/6] serial: samsung: Keep a copy of platform data in driver's private data

[Grant Likely]

On Mon, Jun 20, 2011 at 5:02 AM, Thomas Abraham
thomas.abra...@linaro.org wrote:
 The driver depends on pdev-dev.platform_data to retrive information
 about the platform data even after the initialization. To add device
 tree support, this has to be changed in way that the platform data
 is avialable from driver's private data. This patch adds support
 for keeping a copy of the plaform data in s3c24xx_uart_info and using
 it when needed after the initialization.

 Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
 ---
  drivers/tty/serial/s5pv210.c |   12 ++--
  drivers/tty/serial/samsung.c |   24 
  drivers/tty/serial/samsung.h |    4 +++-
  3 files changed, 33 insertions(+), 7 deletions(-)

Hi Thomas.

Don't forget you need to cc Alan Cox and the linux-serial mailing list
for tty driver patches.

Comments below...


 diff --git a/drivers/tty/serial/s5pv210.c b/drivers/tty/serial/s5pv210.c
 index d6b2423..3b2021a 100644
 --- a/drivers/tty/serial/s5pv210.c
 +++ b/drivers/tty/serial/s5pv210.c
 @@ -27,9 +27,13 @@
  static int s5pv210_serial_setsource(struct uart_port *port,
                                        struct s3c24xx_uart_clksrc *clk)
  {
 -       struct s3c2410_uartcfg *cfg = port-dev-platform_data;
 +       struct s3c24xx_uart_port *ourport;
 +       struct s3c2410_uartcfg *cfg;
        unsigned long ucon = rd_regl(port, S3C2410_UCON);

 +       ourport = container_of(port, struct s3c24xx_uart_port, port);
 +       cfg = ourport-info-cfg;
 +
        if ((cfg-clocks_size) == 1)
                return 0;

 @@ -50,9 +54,13 @@ static int s5pv210_serial_setsource(struct uart_port *port,
  static int s5pv210_serial_getsource(struct uart_port *port,
                                        struct s3c24xx_uart_clksrc *clk)
  {
 -       struct s3c2410_uartcfg *cfg = port-dev-platform_data;
 +       struct s3c24xx_uart_port *ourport;
 +       struct s3c2410_uartcfg *cfg;
        u32 ucon = rd_regl(port, S3C2410_UCON);

 +       ourport = container_of(port, struct s3c24xx_uart_port, port);
 +       cfg = ourport-info-cfg;
 +
        clk-divisor = 1;

        if ((cfg-clocks_size) == 1)
 diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
 index 7ead421..77d900f 100644
 --- a/drivers/tty/serial/samsung.c
 +++ b/drivers/tty/serial/samsung.c
 @@ -42,6 +42,7 @@
  #include linux/delay.h
  #include linux/clk.h
  #include linux/cpufreq.h
 +#include linux/slab.h

  #include asm/irq.h

 @@ -169,10 +170,13 @@ static inline struct s3c24xx_uart_info 
 *s3c24xx_port_to_info(struct uart_port *p

  static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port 
 *port)
  {
 +       struct s3c24xx_uart_port *ourport;
 +
        if (port-dev == NULL)
                return NULL;

 -       return (struct s3c2410_uartcfg *)port-dev-platform_data;
 +       ourport = container_of(port, struct s3c24xx_uart_port, port);
 +       return ourport-info-cfg;
  }

  static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
 @@ -1053,7 +1057,7 @@ static int s3c24xx_serial_init_port(struct 
 s3c24xx_uart_port *ourport,
                                    struct platform_device *platdev)
  {
        struct uart_port *port = ourport-port;
 -       struct s3c2410_uartcfg *cfg;
 +       struct s3c2410_uartcfg *cfg = platdev-dev.platform_data;
        struct resource *res;
        int ret;

 @@ -1062,14 +1066,24 @@ static int s3c24xx_serial_init_port(struct 
 s3c24xx_uart_port *ourport,
        if (platdev == NULL)
                return -ENODEV;

 -       cfg = s3c24xx_dev_to_cfg(platdev-dev);
 -
        if (port-mapbase != 0)
                return 0;

 +       if (cfg) {
 +               memcpy((void *)info-cfg, cfg, sizeof(struct 
 s3c2410_uartcfg));

info-cfg = *cfg; should be sufficient.

 +               info-cfg.clocks = kzalloc(sizeof(struct s3c24xx_uart_clksrc) 
 *
 +                                       cfg-clocks_size, GFP_KERNEL);
 +               if (!info-cfg.clocks)
 +                       return -ENOMEM;
 +               memcpy(info-cfg.clocks, cfg-clocks,
 +                       sizeof(struct s3c24xx_uart_clksrc) * 
 cfg-clocks_size);
 +       }

ewwh. There has to be a better way to do this.  Part of the point of
putting a copy of pdata into the private data structure is to simplify
the driver so that kzallocing wouldn't be necessary.  With that clock
table, the driver actually gets more complex because both DT and
non-DT paths now need to kzalloc a clock array.

From what I can tell, the list of clocks on all mainlined platforms is
a static array of one or two entries; min  max baud are always set to
0, and names are one of:
- uclk  pclk
- uclk
- uclk1
- fclk (with divisor either 10 or 0)
- pclk_low  uclk1

You could also make the clock structure a static array of 2 elements
in the private data structure.  That would simplify both this code and
the followon DT patch.

Also, peaking forward at what the 2nd patch does, I think that it

Re: [PATCH 2/6] serial: samsung: Add device tree support for s5pv210 uart driver

[Grant Likely]

On Mon, Jun 20, 2011 at 5:02 AM, Thomas Abraham
thomas.abra...@linaro.org wrote:
 For device tree based probe, the dependecy on pdev-id to attach a
 corresponding default port info to the driver's private data is
 removed. The fifosize parameter is obtained from the device tree
 node and the next available instance of port info is updated
 with the fifosize value and attached to the driver's private data.

 The samsung uart core driver is also modified to parse the device
 tree node and pick up the platform data from the node.

 Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
 ---
  .../bindings/tty/serial/samsung_uart.txt           |   50 +++
  drivers/tty/serial/s5pv210.c                       |   27 ++-
  drivers/tty/serial/samsung.c                       |   90 
 
  3 files changed, 166 insertions(+), 1 deletions(-)
  create mode 100644 
 Documentation/devicetree/bindings/tty/serial/samsung_uart.txt

 diff --git a/Documentation/devicetree/bindings/tty/serial/samsung_uart.txt 
 b/Documentation/devicetree/bindings/tty/serial/samsung_uart.txt
 new file mode 100644
 index 000..4c0783d
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/tty/serial/samsung_uart.txt
 @@ -0,0 +1,50 @@
 +* Samsung's UART Controller
 +
 +The Samsung's UART controller is used for serial communications on all of
 +Samsung's s3c24xx, s3c64xx and s5p series application processors.
 +
 +Required properties:
 +- compatible : should be specific to the application processor
 +       - samsung,s5pv210-uart , for s5pc110, s5pv210 and Exynos4 family.
 +       - samsung,s3c6400-uart, for s3c64xx, s5p64xx and s5pc100.
 +       - samsung,s3c2410-uart, for s3c2410.
 +       - samsung,s3c2412-uart, for s3c2412.
 +       - samsung,s3c2440-uart, for s3c244x.
 +
 +- reg :        base physical address of the controller and length of memory 
 mapped
 +       region.
 +
 +- interrupts : Three interrupt numbers should be specified in the following
 +       order - TX interrupt, RX interrupt, Error Interrupt.
 +
 +- hwport : Instance number of the UART controller in the processor.
 +       (ToDo: Remove this from the driver).
 +
 +- flags : Not used, but set value as 0. (ToDo: Remove this flag from driver).

If they are to be removed, then you should drop them from the documentation.

 +
 +- uart_flags : Additional serial core flags to passed to the serial core
 +       when the driver is registred. For example: UPF_CONS_FLOW.

Underscores are discouraged in property and node names.  Use '-' instead.

For custom properties, you should prefix the property name with 'samsung,'.

This looks very much like directly encoding the Linux flags into the
device tree.  The binding should be completely contained within
itself, and not refer to OS implementation details.  It is fine to use
the same values that Linux happens to use, but they need to still be
explicitly documented as to what they mean.  Also, a 'flags' property
usually isn't very friendly to mere-mortals when the explicit
behaviour can be enabled with the presence of a named property.  For
example; something like a samsung,uart-has-rtscts to enable rts/cts.

 +
 +- has_fracval : Set to 1, if the controller supports fractional part of
 +       for the baud divisor, otherwise, set to 0.

Boolean stuff often doesn't need a value.  If the property is present,
it is a '1'.  If it isn't, then it is a '0'.

 +
 +- ucon_default : Default board specific setting of UCON register.
 +
 +- ulcon_default : Default board specific setting of ULCON register.
 +
 +- ufcon_default : Default board specific setting of UFCON register.

I think I've commented on this before, but I do try to avoid direct
coding registers into the DT.  That said, sometimes there really isn't
a nice human-friendly way of encoding things and direct register
values is the best approach.

 +
 +- uart_clksrc : One or more child nodes representing the clock sources that
 +       could be used to derive the buad rate. Each of these child nodes
 +       has four required properties.
 +
 +       - name : Name of the parent clock.
 +       - divisor : divisor from the clock to the uart controller.
 +       - min_baud : Minimum baud rate for which this clock can be used.
 +                       Set to zero, if there is no limitation.
 +       - max_buad : Maximum baud rate for which this clock can be used.

typo: s/buad/baud/

 +                       Set to zero, if there is no limitation.

This looks to be directly encoding the current Linux implementation
details into the device tree (it is a direct copy of the config
structure members), and it doesn't use the common clock binding.  It's
fine to use sub nodes for each clock attachment, particularly because
it looks like the uart is able to apply it's own divisor to the clock
input, but I would definitely encode the data using the existing
struct clock binding.

 +
 +Optional properties:
 +- fifosize: Size of the tx/rx fifo used in the controller. If 

Re: [PATCH 4/6] mmc: sdhci-s3c: Add support for device tree based probe

[Grant Likely]

On Mon, Jun 20, 2011 at 5:02 AM, Thomas Abraham
thomas.abra...@linaro.org wrote:
 Add of_match_table to enable sdhci-s3c driver to be probed when a compatible
 sdhci device node is found in device tree.

 Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
 ---
 This is temporary patch. sdhci-s3c driver has to be moved to sdhci-pltfm
 based driver.

... and the binding needs to be documented.  :-)

g.


  drivers/mmc/host/sdhci-s3c.c |   11 +++
  1 files changed, 11 insertions(+), 0 deletions(-)

 diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
 index 69e3ee3..5ccbee0 100644
 --- a/drivers/mmc/host/sdhci-s3c.c
 +++ b/drivers/mmc/host/sdhci-s3c.c
 @@ -629,6 +629,16 @@ static int sdhci_s3c_resume(struct platform_device *dev)
  #define sdhci_s3c_resume NULL
  #endif

 +#ifdef CONFIG_OF
 +static const struct of_device_id s3c_sdhci_match[] = {
 +       { .compatible = samsung,s3c-sdhci },
 +       {},
 +};
 +MODULE_DEVICE_TABLE(of, s3c_sdhci_match);
 +#else
 +#define s3c_sdhci_match NULL
 +#endif
 +
  static struct platform_driver sdhci_s3c_driver = {
        .probe          = sdhci_s3c_probe,
        .remove         = __devexit_p(sdhci_s3c_remove),
 @@ -637,6 +647,7 @@ static struct platform_driver sdhci_s3c_driver = {
        .driver         = {
                .owner  = THIS_MODULE,
                .name   = s3c-sdhci,
 +               .of_match_table = s3c_sdhci_match,
        },
  };

 --
 1.6.6.rc2


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-- 
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Secret Lab Technologies Ltd.
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Re: [PATCH 6/6] arm: exynos4: Add a new Exynos4 device tree enabled machine

[Grant Likely]

On Mon, Jun 20, 2011 at 5:02 AM, Thomas Abraham
thomas.abra...@linaro.org wrote:
 Basic Exynos4 machine with device tree support that can boot on a Exynos4
 based smdkv310 board and bring up the console.

 Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
 ---
  Documentation/devicetree/bindings/arm/samsung.txt |    3 +-
  arch/arm/mach-exynos4/Kconfig                     |   11 +++
  arch/arm/mach-exynos4/Makefile                    |    1 +
  arch/arm/mach-exynos4/mach-exynos4-dt.c           |   94 
 +
  4 files changed, 108 insertions(+), 1 deletions(-)
  create mode 100644 arch/arm/mach-exynos4/mach-exynos4-dt.c

 diff --git a/Documentation/devicetree/bindings/arm/samsung.txt 
 b/Documentation/devicetree/bindings/arm/samsung.txt
 index 594cb97..80d29bb 100644
 --- a/Documentation/devicetree/bindings/arm/samsung.txt
 +++ b/Documentation/devicetree/bindings/arm/samsung.txt
 @@ -4,6 +4,7 @@ Samsung Exynos4 S5PV310 SoC based SMDKV310 eval board
     Samsung's Exynos4 family of application processors.

  Required root node properties:
 -    - compatible = samsung,smdkv310,samsung,s5pv310
 +    - compatible = samsung,smdkv310,samsung,s5pv310, 
 samsung,exynos4210'.
         (a) samsung,smdkv310 - for Samsung's SMDKV310 eval board.
         (b) samsung,s5pv310  - for boards based on S5PV310 SoC.
 +       (c) samsung,exynos4210 - for boards based on Exynos4210 processor.
 diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
 index 1435fc3..412e0c5 100644
 --- a/arch/arm/mach-exynos4/Kconfig
 +++ b/arch/arm/mach-exynos4/Kconfig
 @@ -186,6 +186,17 @@ config MACH_NURI
        help
          Machine support for Samsung Mobile NURI Board.

 +config MACH_EXYNOS4_DT
 +       bool Samsung's Exynos4 Machine with DT support
 +       select CPU_EXYNOS4210
 +       select USE_OF
 +       select S3C_DEV_WDT
 +       select S3C_DEV_HSMMC
 +       select S3C_DEV_HSMMC2
 +       select EXYNOS4_SETUP_SDHCI
 +       help
 +         Machine support for Samsung Exynos4 machine with device tree 
 enabled.
 +
  endmenu

  comment Configuration for HSMMC bus width
 diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
 index 60fe5ec..6491e5b 100644
 --- a/arch/arm/mach-exynos4/Makefile
 +++ b/arch/arm/mach-exynos4/Makefile
 @@ -36,6 +36,7 @@ obj-$(CONFIG_MACH_SMDKV310)           += mach-smdkv310.o
  obj-$(CONFIG_MACH_ARMLEX4210)          += mach-armlex4210.o
  obj-$(CONFIG_MACH_UNIVERSAL_C210)      += mach-universal_c210.o
  obj-$(CONFIG_MACH_NURI)                        += mach-nuri.o
 +obj-$(CONFIG_MACH_EXYNOS4_DT)          += mach-exynos4-dt.o

  # device support

 diff --git a/arch/arm/mach-exynos4/mach-exynos4-dt.c 
 b/arch/arm/mach-exynos4/mach-exynos4-dt.c
 new file mode 100644
 index 000..34267d8
 --- /dev/null
 +++ b/arch/arm/mach-exynos4/mach-exynos4-dt.c
 @@ -0,0 +1,94 @@
 +/*
 + * Samsung's Exynos4210 device tree enabled machine.
 + *
 + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 + *             http://www.samsung.com
 + * Copyright (c) 2010-2011 Linaro Ltd.
 + *             www.linaro.org
 + *
 + * This program is free software; you can redistribute it and/or modify
 + * it under the terms of the GNU General Public License version 2 as
 + * published by the Free Software Foundation.
 +*/
 +
 +#include linux/serial_core.h
 +#include linux/platform_device.h
 +#include linux/io.h
 +#include linux/of_platform.h
 +#include linux/irq.h
 +
 +#include asm/mach/arch.h
 +#include asm/mach-types.h
 +
 +#include plat/regs-serial.h
 +#include plat/exynos4.h
 +#include plat/cpu.h
 +#include plat/sdhci.h
 +
 +#include mach/map.h
 +
 +static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
 +       .cd_type                = S3C_SDHCI_CD_INTERNAL,
 +       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 +#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
 +       .max_width              = 8,
 +       .host_caps              = MMC_CAP_8_BIT_DATA,
 +#endif
 +};
 +
 +static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
 +       .cd_type                = S3C_SDHCI_CD_INTERNAL,
 +       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 +#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
 +       .max_width              = 8,
 +       .host_caps              = MMC_CAP_8_BIT_DATA,
 +#endif
 +};
 +
 +static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
 +       OF_DEV_AUXDATA(samsung,s3c-sdhci, EXYNOS4_PA_HSMMC(2),
 +                               s3c-sdhci.2, s3c_hsmmc2_def_platdata),
 +       OF_DEV_AUXDATA(samsung,s3c-sdhci, EXYNOS4_PA_HSMMC(0),
 +                               s3c-sdhci.0, s3c_hsmmc0_def_platdata),
 +       OF_DEV_AUXDATA(samsung,s5pv210-uart, S5P_PA_UART0,
 +                               s5pv210-uart.0, NULL),
 +       OF_DEV_AUXDATA(samsung,s5pv210-uart, S5P_PA_UART1,
 +                               s5pv210-uart.1, NULL),
 +       {},
 +};
 +
 +static void __init exynos4_dt_map_io(void)
 +{
 +   

Re: [PATCH] mmc: dw_mmc: protect a sequence of request and request-done.

[Chris Ball]

Hi,

On Mon, Jun 20 2011, Will Newton wrote:
 On Mon, Jun 20, 2011 at 9:24 AM, Seungwon Jeon tgih@samsung.com wrote:
 Response timeout(RTO), Response crc error(RCRC) and Response error(RE)
 signals come with command done(CD) and can be raised preceding command
 done(CD). That is these error interrupts and CD can be handled in
 separate dw_mci_interrupt(). If mmc_request_done() is called because of
 response timeout before command done is occured, next request can be
 sent, but CD of current request is not finished. This can bring about
 a broken sequence of request and request-done.

 And Data error interrupt(DRTO, DCRC, SBE, EBE) and data transfer
 over(DTO) are same reanson.

 Signed-off-by: Seungwon Jeon tgih@samsung.com

 Acked-by: Will Newton will.new...@imgtec.com

Pushed to mmc-next for 3.1, thanks.

- Chris.
-- 
Chris Ball   c...@laptop.org   http://printf.net/
One Laptop Per Child
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Re: [PATCH v2 1/5] ARM: EXYNOS4: Change clock name for FIMD

[Sylwester Nawrocki]

Hi Inki

On 06/20/2011 12:09 PM, daeinki wrote:
 Hi, Mr. Han and Sylwester.
 below is my opinion.
 
 JinGoo Han 쓴 글:
...
 Please, refer to the LCD contoller clock table as follows:
   - s3c2440 uses 's3c2410fb.c', not 's3c-fb.c' since  LCD controller IP is 
 different.
 However, s3c2443 uses 's3c-fb.c'. So I add s3c2443 to table instead of 
 s3c2440.
   - s3c6410 has SCLK_LCD, but, clock name is not defined.
   - Exynos4 does not use name HCLK.

| LCD controller||
| (IP core) clock   | LCD pixel clock|
 --++---+
 s3c2443   |  HCLK (lcd)   | x  |  DISPCLK (display-if) |
 --++---+
 s3c6410   |  HCLK (lcd)   | x  |  SCLK_LCD  (N/A)  |
 --++---+
 s5pc100   |  HCLK (lcd)   | x  |  SCLK_LCD  (sclk_lcd) |
 --++---+
 s5pv210   |  HCLK_DSYS (lcd)  | x  |  SCLK_FIMD (sclk_fimd)|
 --+---++
 exynos4   |  ACLK_160 (fimd)  | O  |  SCLK_FIMD (sclk_fimd)|
 --++---+
...
 I think we could try to create two clock connection ids to the framebuffer
 device in the first place, e.g. bus_ck, pix_ck.
 And then think about how handle that in the driver.

 But this requires conversion to the omap-style clock registration method,
 something like in the attached patch. The patch is only for s5pv210 and
 and compile tested only as I didn't have any board to test it here.
 It's based on for-next branch at http://tinyurl.com/6yzravy I think there
 might be more issues to convert the old s3c24xx platforms, nevertheless
 the attached patch should not affect them.
...

 when someone adds new board file with new SoC, he doesn't need to know
 this SoC chip has hclk and sclk_fimd or only sclk_fimd(such as exynos4).
 using implicit clock means it should know that this SoC chip has both
 clocks(bus clock, sclk_fimd) or only sclk_fimd.
 
 for example, if any driver needs fimd clock frequency then this driver
 should know that this SoC chip is exynos4 or not and has both clock
 source(bus clock, soure clock fimd) or not(only source clock fimd)
 so I think we shoule see only a clock lcd regardless of which clock is
 used and if exynos4 then sclk_fimd would be set by machine code.
 
 and Sylwester,
 it appears that your patch has one issue about clk_get function call.
 your patch adds bus_ck to list head clocks of plat-samsung/clock.c

Why do you think so ? In fact the clocks list in plat-samsung/clock.c
is not used any more, AFAIU it should have been removed altogether with
clk_get/clk_put functions in Thomas' clkdev patches. 
When you comment out the line declaring the list everything compiles fine
there.

 and pix_ck to list head clocks of drivers/clk/clkdev.c and I am
 afraid that if some machine(such as s3c24xx, s3c64xx and s5pc1xx) has
 CLKDEV_LOOKUP configuration then clk_get() would fail to get clock
 object because in this case, clock lookup could be done through list
 head clocks of driver/clk/clkdev.c.(it's right from
 plat-samsung/clock.c) so I think it needs more patch for resolving this

As I indicated earlier the framebuffer driver would have to be modified
to support newly introduced clock _connection_ names.
We could (temporarily) name one of those clock connections lcd,
to avoid additional trouble on SoCs that still use a one-to-one
platform clock name - clock connection id mapping.

 issue also and do you think it's a good way to use only one clock name
 lcd?... in fact, this might be so much slight issue. :)

Do you mean using using one name in the code for different clock names
in the datasheets ? I suppose it was because of the API limitations and
hope it will change for the better. :)

Cheers,
Sylwester

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Re: [PATCH 0/7] ARM: EXYNOS4: Adds External GIC

[Kyungmin Park]

Hi,

There are some boards which use the EVT0 chip. some SMDKV310 and
Universal-C210.
With this changes, it can't use these boards.

Do you want to remove EVT0 based boards?

Thank you,
Kyungmin Park

On Mon, Jun 20, 2011 at 4:34 PM, Changhwan Youn chaos.y...@samsung.com wrote:
 This patch adds implementation External GIC on EXYNOS4 SoC.

 Note: need to update timer codes for supporting old type of
 EXYNOS4 SoCs.

 [PATCH 1/7] ARM: EXYNOS4: Add external GIC io memory mapping
 [PATCH 2/7] ARM: EXYNOS4: modify interrupt mappings for external GIC
 [PATCH 3/7] ARM: EXYNOS4: set the affinity of mct1 interrupt using IRQ_MCT_L1
 [PATCH 4/7] ARM: GIC: move gic_chip_data structure declaration to header
 [PATCH 5/7] ARM: EXYNOS4: Add support external GIC
 [PATCH 6/7] ARM: EXYNOS4: Remove clock event timers using ARM private timers
 [PATCH 7/7] ARM: EXYNOS4: Add chained enrty/exit function to uart interrupt 
 handler
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Re: [PATCH v2 1/5] ARM: EXYNOS4: Change clock name for FIMD

[daeinki]

Hi Sylwester

You are right, no problem if clkdev is used instead of 
plat-samsung/clock.c. I didn't aware of recently trend.(I couldn't 
afford to having interest in open source) and I will look over clkdev 
feature Thomas introduced.


Thank you.

Sylwester Nawrocki 쓴 글:

Hi Inki

On 06/20/2011 12:09 PM, daeinki wrote:

Hi, Mr. Han and Sylwester.
below is my opinion.

JinGoo Han 쓴 글:

...

Please, refer to the LCD contoller clock table as follows:
  - s3c2440 uses 's3c2410fb.c', not 's3c-fb.c' since  LCD controller IP is 
different.
However, s3c2443 uses 's3c-fb.c'. So I add s3c2443 to table instead of 
s3c2440.
  - s3c6410 has SCLK_LCD, but, clock name is not defined.
  - Exynos4 does not use name HCLK.

   | LCD controller||
   | (IP core) clock   | LCD pixel clock|
--++---+
s3c2443   |  HCLK (lcd)   | x  |  DISPCLK (display-if) |
--++---+
s3c6410   |  HCLK (lcd)   | x  |  SCLK_LCD  (N/A)  |
--++---+
s5pc100   |  HCLK (lcd)   | x  |  SCLK_LCD  (sclk_lcd) |
--++---+
s5pv210   |  HCLK_DSYS (lcd)  | x  |  SCLK_FIMD (sclk_fimd)|
--+---++
exynos4   |  ACLK_160 (fimd)  | O  |  SCLK_FIMD (sclk_fimd)|
--++---+

...

I think we could try to create two clock connection ids to the framebuffer
device in the first place, e.g. bus_ck, pix_ck.
And then think about how handle that in the driver.

But this requires conversion to the omap-style clock registration method,
something like in the attached patch. The patch is only for s5pv210 and
and compile tested only as I didn't have any board to test it here.
It's based on for-next branch at http://tinyurl.com/6yzravy I think there
might be more issues to convert the old s3c24xx platforms, nevertheless
the attached patch should not affect them.

...


when someone adds new board file with new SoC, he doesn't need to know
this SoC chip has hclk and sclk_fimd or only sclk_fimd(such as exynos4).
using implicit clock means it should know that this SoC chip has both
clocks(bus clock, sclk_fimd) or only sclk_fimd.

for example, if any driver needs fimd clock frequency then this driver
should know that this SoC chip is exynos4 or not and has both clock
source(bus clock, soure clock fimd) or not(only source clock fimd)
so I think we shoule see only a clock lcd regardless of which clock is
used and if exynos4 then sclk_fimd would be set by machine code.

and Sylwester,
it appears that your patch has one issue about clk_get function call.
your patch adds bus_ck to list head clocks of plat-samsung/clock.c


Why do you think so ? In fact the clocks list in plat-samsung/clock.c
is not used any more, AFAIU it should have been removed altogether with
clk_get/clk_put functions in Thomas' clkdev patches. 
When you comment out the line declaring the list everything compiles fine

there.


and pix_ck to list head clocks of drivers/clk/clkdev.c and I am
afraid that if some machine(such as s3c24xx, s3c64xx and s5pc1xx) has
CLKDEV_LOOKUP configuration then clk_get() would fail to get clock
object because in this case, clock lookup could be done through list
head clocks of driver/clk/clkdev.c.(it's right from
plat-samsung/clock.c) so I think it needs more patch for resolving this


As I indicated earlier the framebuffer driver would have to be modified
to support newly introduced clock _connection_ names.
We could (temporarily) name one of those clock connections lcd,
to avoid additional trouble on SoCs that still use a one-to-one
platform clock name - clock connection id mapping.


issue also and do you think it's a good way to use only one clock name
lcd?... in fact, this might be so much slight issue. :)


Do you mean using using one name in the code for different clock names
in the datasheets ? I suppose it was because of the API limitations and
hope it will change for the better. :)

Cheers,
Sylwester




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[PATCH v2 2/5] Samsung SoC ADC: Channel selection for S5PV210, S5PC110, and Exynos4

[MyungJoo Ham]

In S5PV210/S5PC110/Exynos4, ADCMUX channel selection uses ADCMUX
register, not ADCCON register. This patch corrects the behavior of
Samsung-ADC for such cpus.

Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
--
v2: No changes from v1. Resubmitted as a series of patches
---
 arch/arm/plat-samsung/adc.c   |   24 +---
 arch/arm/plat-samsung/include/plat/regs-adc.h |1 +
 2 files changed, 18 insertions(+), 7 deletions(-)

diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index 938f6e9..0233c69 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -41,8 +41,10 @@
 
 enum s3c_cpu_type {
TYPE_S3C24XX,
-   TYPE_S3C64XX
+   TYPE_S3C64XX,
+   TYPE_S5P,
 };
+#define S3C64XX_OR_LATER(type) ((type) == TYPE_S3C64XX || (type) == TYPE_S5P)
 
 struct s3c_adc_client {
struct platform_device  *pdev;
@@ -93,6 +95,7 @@ static inline void s3c_adc_select(struct adc_device *adc,
  struct s3c_adc_client *client)
 {
unsigned con = readl(adc-regs + S3C2410_ADCCON);
+   enum s3c_cpu_type cpu = platform_get_device_id(adc-pdev)-driver_data;
 
client-select_cb(client, 1);
 
@@ -100,8 +103,12 @@ static inline void s3c_adc_select(struct adc_device *adc,
con = ~S3C2410_ADCCON_STDBM;
con = ~S3C2410_ADCCON_STARTMASK;
 
-   if (!client-is_ts)
-   con |= S3C2410_ADCCON_SELMUX(client-channel);
+   if (!client-is_ts) {
+   if (cpu == TYPE_S5P)
+   writel(client-channel  0xf, adc-regs + S5P_ADCMUX);
+   else
+   con |= S3C2410_ADCCON_SELMUX(client-channel);
+   }
 
writel(con, adc-regs + S3C2410_ADCCON);
 }
@@ -287,8 +294,8 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
 
client-nr_samples--;
 
-   if (cpu == TYPE_S3C64XX) {
-   /* S3C64XX ADC resolution is 12-bit */
+   if (S3C64XX_OR_LATER(cpu)) {
+   /* S3C64XX/S5P ADC resolution is 12-bit */
data0 = 0xfff;
data1 = 0xfff;
} else {
@@ -314,7 +321,7 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
}
 
 exit:
-   if (cpu == TYPE_S3C64XX) {
+   if (S3C64XX_OR_LATER(cpu)) {
/* Clear ADC interrupt */
writel(0, adc-regs + S3C64XX_ADCCLRINT);
}
@@ -388,7 +395,7 @@ static int s3c_adc_probe(struct platform_device *pdev)
clk_enable(adc-clk);
 
tmp = adc-prescale | S3C2410_ADCCON_PRSCEN;
-   if (platform_get_device_id(pdev)-driver_data == TYPE_S3C64XX) {
+   if (S3C64XX_OR_LATER(platform_get_device_id(pdev)-driver_data)) {
/* Enable 12-bit ADC resolution */
tmp |= S3C64XX_ADCCON_RESSEL;
}
@@ -478,6 +485,9 @@ static struct platform_device_id s3c_adc_driver_ids[] = {
}, {
.name   = s3c64xx-adc,
.driver_data= TYPE_S3C64XX,
+   }, {
+   .name   = s5p-adc,
+   .driver_data= TYPE_S5P,
},
{ }
 };
diff --git a/arch/arm/plat-samsung/include/plat/regs-adc.h 
b/arch/arm/plat-samsung/include/plat/regs-adc.h
index 7554c4f..035e8c3 100644
--- a/arch/arm/plat-samsung/include/plat/regs-adc.h
+++ b/arch/arm/plat-samsung/include/plat/regs-adc.h
@@ -21,6 +21,7 @@
 #define S3C2410_ADCDAT1   S3C2410_ADCREG(0x10)
 #define S3C64XX_ADCUPDNS3C2410_ADCREG(0x14)
 #define S3C64XX_ADCCLRINT  S3C2410_ADCREG(0x18)
+#define S5P_ADCMUX S3C2410_ADCREG(0x1C)
 #define S3C64XX_ADCCLRINTPNDNUPS3C2410_ADCREG(0x20)
 
 
-- 
1.7.4.1

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[PATCH v2 0/5] Update Samsung-SoC ADC (regulator / recent CPU support)

[MyungJoo Ham]

Patch 1/5: Add regulator support in ADC driver.
If CONFIG_REGULATOR is enabled, vdd regulator for the ADC driver
(e.g., s5p-adc) should exist for the adc driver.

Patch 2/5: Channel selection method for S5PC110 and Exynos4
Recent Samsung SoCs have different register addresses for
channel selection. Use s5p-adc to support such chips.

Patch 3/5: Support ADC at Exynos4
Define register addresses and device name for Exynos4

Patch 4/5: Support ADC at S5PC110/S5PV210
Correct ADC device name for S5PC110/S5PV210

Patch 5/5: Header file correction (plat/devs.h)
The long-overdue bugfix for compiler errors. ADC for Exynos4 fails to
be compiled without this patch.

MyungJoo Ham (5):
  Samsung SoC ADC: use regulator (VDD for ADC).
  Samsung SoC ADC: Channel selection for S5PV210, S5PC110, and Exynos4
  ARM: Exynos4: Support ADC
  ARM: S5PC110/S5PV210: Support ADC
  Samsung SoC: header file revised to prevent declaring duplicated.

 arch/arm/mach-exynos4/Kconfig |1 +
 arch/arm/mach-exynos4/cpu.c   |4 ++
 arch/arm/mach-exynos4/include/mach/irqs.h |8 
 arch/arm/mach-exynos4/include/mach/map.h  |5 ++
 arch/arm/mach-s5pv210/cpu.c   |2 +-
 arch/arm/plat-samsung/adc.c   |   55 +++-
 arch/arm/plat-samsung/include/plat/devs.h |5 ++
 arch/arm/plat-samsung/include/plat/regs-adc.h |1 +
 8 files changed, 68 insertions(+), 13 deletions(-)

-- 
1.7.4.1

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[PATCH v2 3/5] ARM: Exynos4: Support ADC

[MyungJoo Ham]

Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
--
v2: No changes from v1. Resubmitted as a series of patches
---
 arch/arm/mach-exynos4/Kconfig |1 +
 arch/arm/mach-exynos4/cpu.c   |4 
 arch/arm/mach-exynos4/include/mach/irqs.h |8 
 arch/arm/mach-exynos4/include/mach/map.h  |5 +
 4 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index 1435fc3..61fdf68 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -183,6 +183,7 @@ config MACH_NURI
select EXYNOS4_SETUP_SDHCI
select EXYNOS4_SETUP_USB_PHY
select SAMSUNG_DEV_PWM
+   select SAMSUNG_DEV_ADC
help
  Machine support for Samsung Mobile NURI Board.
 
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 9babe44..c9af2f9 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -19,7 +19,9 @@
 
 #include plat/cpu.h
 #include plat/clock.h
+#include plat/devs.h
 #include plat/exynos4.h
+#include plat/adc-core.h
 #include plat/sdhci.h
 #include plat/devs.h
 #include plat/fimc-core.h
@@ -128,6 +130,8 @@ void __init exynos4_map_io(void)
exynos4_default_sdhci2();
exynos4_default_sdhci3();
 
+   s3c_adc_setname(s5p-adc);
+
s3c_fimc_setname(0, exynos4-fimc);
s3c_fimc_setname(1, exynos4-fimc);
s3c_fimc_setname(2, exynos4-fimc);
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h 
b/arch/arm/mach-exynos4/include/mach/irqs.h
index 5d03730..aa62d3f 100644
--- a/arch/arm/mach-exynos4/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -73,6 +73,11 @@
 #define IRQ_SYSMMU_MFC_M1_0COMBINER_IRQ(5, 6)
 #define IRQ_SYSMMU_PCIE_0  COMBINER_IRQ(5, 7)
 
+#define IRQ_ADC0COMBINER_IRQ(19, 0)
+#define IRQ_PEN0COMBINER_IRQ(19, 1)
+#define IRQ_ADC1COMBINER_IRQ(19, 2)
+#define IRQ_PEN1COMBINER_IRQ(19, 3)
+
 #define IRQ_PDMA0  COMBINER_IRQ(21, 0)
 #define IRQ_PDMA1  COMBINER_IRQ(21, 1)
 
@@ -143,6 +148,9 @@
 
 #define MAX_COMBINER_NR54
 
+#define IRQ_ADCIRQ_ADC0
+#define IRQ_TC IRQ_PEN0
+
 #define S5P_IRQ_EINT_BASE  COMBINER_IRQ(MAX_COMBINER_NR, 0)
 
 #define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE + 0)
diff --git a/arch/arm/mach-exynos4/include/mach/map.h 
b/arch/arm/mach-exynos4/include/mach/map.h
index 0009e77..d5ba95b 100644
--- a/arch/arm/mach-exynos4/include/mach/map.h
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -108,6 +108,9 @@
 
 #define EXYNOS4_PA_IIC(x)  (0x1386 + ((x) * 0x1))
 
+#define EXYNOS4_PA_ADC 0x1391
+#define EXYNOS4_PA_ADC10x13911000
+
 #define EXYNOS4_PA_AC970x139A
 
 #define EXYNOS4_PA_SPDIF   0x139B
@@ -130,6 +133,8 @@
 #define S3C_PA_IIC5EXYNOS4_PA_IIC(5)
 #define S3C_PA_IIC6EXYNOS4_PA_IIC(6)
 #define S3C_PA_IIC7EXYNOS4_PA_IIC(7)
+#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
+#define SAMSUNG_PA_ADC1EXYNOS4_PA_ADC1
 #define S3C_PA_RTC EXYNOS4_PA_RTC
 #define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
 
-- 
1.7.4.1

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[PATCH v2 4/5] ARM: S5PC110/S5PV210: Support ADC

[MyungJoo Ham]

Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
--
v2: No changes from v1. Resubmitted as a series of patches
---
 arch/arm/mach-s5pv210/cpu.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 61e6c24..8b68e30 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -126,7 +126,7 @@ void __init s5pv210_map_io(void)
s5pv210_default_sdhci2();
s5pv210_default_sdhci3();
 
-   s3c_adc_setname(s3c64xx-adc);
+   s3c_adc_setname(s5p-adc);
 
s3c_cfcon_setname(s5pv210-pata);
 
-- 
1.7.4.1

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[PATCH v2 5/5] Samsung SoC: header file revised to prevent declaring duplicated.

[MyungJoo Ham]

There has been no #ifndef - #define - #endif protection for this header
file.

To compile EXYNOS4 with adc support without compiler errors, this patch is 
essential.

Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
--
v2: No changes from v1. Resubmitted as a series of patches
---
 arch/arm/plat-samsung/include/plat/devs.h |5 +
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/devs.h 
b/arch/arm/plat-samsung/include/plat/devs.h
index 4af108f..3c87779 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -12,6 +12,9 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
 */
+#ifndef __PLAT_DEVS_H
+#define __PLAT_DEVS_H __FILE__
+
 #include linux/platform_device.h
 
 struct s3c24xx_uart_resources {
@@ -159,3 +162,5 @@ extern struct platform_device s3c_device_ac97;
  */
 extern void *s3c_set_platdata(void *pd, size_t pdsize,
  struct platform_device *pdev);
+
+#endif /* __PLAT_DEVS_H */
-- 
1.7.4.1

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[PATCH v2 1/5] Samsung SoC ADC: use regulator (VDD for ADC).

[MyungJoo Ham]

This patch allows the Samsung ADC driver to enable VDD regulator at
probe and resume and to disable at exit and suspend.
In a platform where ADC's VDD regulator is not always-on, this control
is required although this patch does not provide fine-grained power
control (turning on the regulator only when being accessed).

However, if VDD regulator (vdd for the adc device) is not provided,
the regulator control will not be activated because there are platforms
that do not provide regulator for ADC device.

arch_initcall has been modified to module_init in order to allow
regulators to be available at probe.

Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com

--
changes from v1
- Removed macro defining the name of regulator.
- Handle error from regulator_enable.
- Do not allow not to have the regulator if CONFIG_REGULATOR.
- Seperate a patch dealing with arch_initcall-module_init
---
 arch/arm/plat-samsung/adc.c |   31 ++-
 1 files changed, 26 insertions(+), 5 deletions(-)

diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index e8f2be2..938f6e9 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -21,6 +21,7 @@
 #include linux/clk.h
 #include linux/interrupt.h
 #include linux/io.h
+#include linux/regulator/consumer.h
 
 #include plat/regs-adc.h
 #include plat/adc.h
@@ -71,6 +72,7 @@ struct adc_device {
unsigned int prescale;
 
int  irq;
+   struct regulator*vdd;
 };
 
 static struct adc_device *adc_dev;
@@ -338,17 +340,24 @@ static int s3c_adc_probe(struct platform_device *pdev)
adc-pdev = pdev;
adc-prescale = S3C2410_ADCCON_PRSCVL(49);
 
+   adc-vdd = regulator_get(dev, vdd);
+   if (IS_ERR(adc-vdd)) {
+   dev_err(dev, operating without regulator \vdd\ .\n);
+   ret = PTR_ERR(adc-vdd);
+   goto err_alloc;
+   }
+
adc-irq = platform_get_irq(pdev, 1);
if (adc-irq = 0) {
dev_err(dev, failed to get adc irq\n);
ret = -ENOENT;
-   goto err_alloc;
+   goto err_reg;
}
 
ret = request_irq(adc-irq, s3c_adc_irq, 0, dev_name(dev), adc);
if (ret  0) {
dev_err(dev, failed to attach adc irq\n);
-   goto err_alloc;
+   goto err_reg;
}
 
adc-clk = clk_get(dev, adc);
@@ -372,6 +381,10 @@ static int s3c_adc_probe(struct platform_device *pdev)
goto err_clk;
}
 
+   ret = regulator_enable(adc-vdd);
+   if (!ret)
+   goto err_ioremap;
+
clk_enable(adc-clk);
 
tmp = adc-prescale | S3C2410_ADCCON_PRSCEN;
@@ -388,12 +401,15 @@ static int s3c_adc_probe(struct platform_device *pdev)
 
return 0;
 
+ err_ioremap:
+   iounmap(adc-regs);
  err_clk:
clk_put(adc-clk);
 
  err_irq:
free_irq(adc-irq, adc);
-
+ err_reg:
+   regulator_put(adc-vdd);
  err_alloc:
kfree(adc);
return ret;
@@ -406,6 +422,8 @@ static int __devexit s3c_adc_remove(struct platform_device 
*pdev)
iounmap(adc-regs);
free_irq(adc-irq, adc);
clk_disable(adc-clk);
+   regulator_disable(adc-vdd);
+   regulator_put(adc-vdd);
clk_put(adc-clk);
kfree(adc);
 
@@ -428,6 +446,7 @@ static int s3c_adc_suspend(struct platform_device *pdev, 
pm_message_t state)
disable_irq(adc-irq);
spin_unlock_irqrestore(adc-lock, flags);
clk_disable(adc-clk);
+   regulator_disable(adc-vdd);
 
return 0;
 }
@@ -435,14 +454,16 @@ static int s3c_adc_suspend(struct platform_device *pdev, 
pm_message_t state)
 static int s3c_adc_resume(struct platform_device *pdev)
 {
struct adc_device *adc = platform_get_drvdata(pdev);
+   int ret;
 
+   ret = regulator_enable(adc-vdd);
clk_enable(adc-clk);
enable_irq(adc-irq);
 
writel(adc-prescale | S3C2410_ADCCON_PRSCEN,
   adc-regs + S3C2410_ADCCON);
 
-   return 0;
+   return ret;
 }
 
 #else
@@ -485,4 +506,4 @@ static int __init adc_init(void)
return ret;
 }
 
-arch_initcall(adc_init);
+module_init(adc_init);
-- 
1.7.4.1

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[PATCH v2 1/4] Exynos4 NURI: configure regulators and PMIC

[MyungJoo Ham]

Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com

--
Changes from v1. Thanks so much for your valuable comments, Mark.
- Removed unnecessary initialization data
- Add __initdata where necessary
- Corrected a regulator name for ADC
---
 arch/arm/mach-exynos4/mach-nuri.c |  622 -
 1 files changed, 621 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-exynos4/mach-nuri.c 
b/arch/arm/mach-exynos4/mach-nuri.c
index 642702b..13b881f 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -17,6 +17,7 @@
 #include linux/gpio.h
 #include linux/regulator/machine.h
 #include linux/regulator/fixed.h
+#include linux/mfd/max8997.h
 #include linux/mmc/host.h
 #include linux/fb.h
 #include linux/pwm_backlight.h
@@ -344,9 +345,624 @@ static void __init nuri_tsp_init(void)
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
 }
 
+static struct regulator_consumer_supply nuri_max8997_ldo1_consumer[] = {
+   REGULATOR_SUPPLY(vdd, s5p-adc), /* Used by CPU's ADC drv */
+};
+static struct regulator_consumer_supply nuri_max8997_ldo3_consumer[] = {
+   REGULATOR_SUPPLY(vdd11, s5p-mipi-csis.0), /* MIPI */
+};
+static struct regulator_consumer_supply nuri_max8997_ldo4_consumer[] = {
+   REGULATOR_SUPPLY(vdd18, s5p-mipi-csis.0), /* MIPI */
+};
+static struct regulator_consumer_supply nuri_max8997_ldo5_consumer[] = {
+   REGULATOR_SUPPLY(vhsic, modemctl), /* MODEM */
+};
+static struct regulator_consumer_supply nuri_max8997_ldo7_consumer[] = {
+   REGULATOR_SUPPLY(dig_18, 0-001f), /* HCD803 */
+};
+static struct regulator_consumer_supply nuri_max8997_ldo8_consumer[] = {
+   REGULATOR_SUPPLY(vusb_d, NULL), /* Used by CPU */
+   REGULATOR_SUPPLY(vdac, NULL), /* Used by CPU */
+};
+static struct regulator_consumer_supply nuri_max8997_ldo11_consumer[] = {
+   REGULATOR_SUPPLY(vcc, platform-lcd), /* U804 LVDS */
+};
+static struct regulator_consumer_supply nuri_max8997_ldo12_consumer[] = {
+   REGULATOR_SUPPLY(vddio, 6-003c), /* HDC802 */
+};
+static struct regulator_consumer_supply nuri_max8997_ldo13_consumer[] = {
+   REGULATOR_SUPPLY(vmmc, s3c-sdhci.2), /* TFLASH */
+};
+static struct regulator_consumer_supply nuri_max8997_ldo14_consumer[] = {
+   REGULATOR_SUPPLY(inmotor, max8997-haptic),
+};
+static struct regulator_consumer_supply nuri_max8997_ldo15_consumer[] = {
+   REGULATOR_SUPPLY(avdd, 3-004a), /* Touch Screen */
+};
+static struct regulator_consumer_supply nuri_max8997_ldo16_consumer[] = {
+   REGULATOR_SUPPLY(d_sensor, 0-001f), /* HDC803 */
+};
+static struct regulator_consumer_supply nuri_max8997_ldo18_consumer[] = {
+   REGULATOR_SUPPLY(vdd, 3-004a), /* Touch Screen */
+};
+static struct regulator_consumer_supply nuri_max8997_buck1_consumer[] = {
+   REGULATOR_SUPPLY(vdd_arm, NULL), /* CPUFREQ */
+};
+static struct regulator_consumer_supply nuri_max8997_buck2_consumer[] = {
+   REGULATOR_SUPPLY(vdd_int, NULL), /* CPUFREQ */
+};
+static struct regulator_consumer_supply nuri_max8997_buck3_consumer[] = {
+   REGULATOR_SUPPLY(vdd, mali_dev.0), /* G3D of Exynos 4 */
+};
+static struct regulator_consumer_supply nuri_max8997_buck4_consumer[] = {
+   REGULATOR_SUPPLY(core, 0-001f), /* HDC803 */
+};
+static struct regulator_consumer_supply nuri_max8997_buck6_consumer[] = {
+   REGULATOR_SUPPLY(dig_28, 0-001f), /* pin 7 of HDC803 */
+};
+static struct regulator_consumer_supply nuri_max8997_esafeout1_consumer[] = {
+   REGULATOR_SUPPLY(usb_vbus, NULL), /* CPU's USB OTG */
+};
+static struct regulator_consumer_supply nuri_max8997_esafeout2_consumer[] = {
+   REGULATOR_SUPPLY(usb_vbus, modemctl), /* VBUS of Modem */
+};
+
+static struct regulator_consumer_supply nuri_max8997_charger_consumer[] = {
+   REGULATOR_SUPPLY(vinchg1, charger-manager.0),
+};
+static struct regulator_consumer_supply nuri_max8997_chg_toff_consumer[] = {
+   REGULATOR_SUPPLY(vinchg_stop, NULL), /* for jack interrupt handlers */
+};
+
+static struct regulator_consumer_supply nuri_max8997_32khz_ap_consumer[] = {
+   REGULATOR_SUPPLY(gps_clk, bcm4751),
+   REGULATOR_SUPPLY(bt_clk, bcm4330-b1),
+   REGULATOR_SUPPLY(wifi_clk, bcm433-b1),
+};
+
+static struct regulator_init_data __initdata nuri_max8997_ldo1_data = {
+   .constraints= {
+   .name   = VADC_3.3V_C210,
+   .min_uV = 330,
+   .max_uV = 330,
+   .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+   .apply_uV   = 1,
+   .state_mem  = {
+   .disabled   = 1,
+   },
+   },
+   .num_consumer_supplies  = ARRAY_SIZE(nuri_max8997_ldo1_consumer),
+   .consumer_supplies  = nuri_max8997_ldo1_consumer,
+};
+
+static struct regulator_init_data __initdata nuri_max8997_ldo2_data = {
+   .constraints= {
+   

[PATCH v2 4/4] Exynos4 NURI: support for NTC thermistor

[MyungJoo Ham]

Signed-off-by: MyungJoo Ham myungjoo@samsung.com
---
 arch/arm/mach-exynos4/mach-nuri.c |   46 +
 1 files changed, 46 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos4/mach-nuri.c 
b/arch/arm/mach-exynos4/mach-nuri.c
index 51f55b4..dc6fc36 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -16,6 +16,7 @@
 #include linux/i2c-gpio.h
 #include linux/gpio_keys.h
 #include linux/gpio.h
+#include linux/platform_data/ntc_thermistor.h
 #include linux/power/max17042_battery.h
 #include linux/regulator/machine.h
 #include linux/regulator/fixed.h
@@ -1006,6 +1007,50 @@ static void __init nuri_ehci_init(void)
s5p_ehci_set_platdata(pdata);
 }
 
+/* NTC Thermistor */
+static struct platform_device nuri_ncp15wb473_thermistor;
+static int read_thermistor_uV(void)
+{
+   static struct s3c_adc_client *adc;
+   int val;
+   s64 converted;
+
+   if (!adc) {
+   adc = s3c_adc_register(nuri_ncp15wb473_thermistor,
+   NULL, NULL, 0);
+   if (IS_ERR_OR_NULL(adc)) {
+   pr_err(%s: Cannot get adc.\n, __func__);
+   return adc ? PTR_ERR(adc) : -ENODEV;
+   }
+   }
+
+   if (IS_ERR_OR_NULL(adc))
+   return adc ? PTR_ERR(adc) : -ENODEV;
+
+   val = s3c_adc_read(adc, 6);
+
+   converted = 330LL * (s64) val;
+   converted = 12;
+
+   pr_emerg(%s: %d - %llduV\n, __func__, val, converted);
+   return converted;
+}
+
+static struct ntc_thermistor_platform_data ncp15wb473_pdata = {
+   .read_uV= read_thermistor_uV,
+   .pullup_uV  = 330, /* VADC_3.3V_C210 */
+   .pullup_ohm = 10, /* R613 in SLP 7 0105 */
+   .pulldown_ohm   = 10, /* R615 in SLP 7 0105 */
+   .connect= NTC_CONNECTED_GROUND,
+};
+
+static struct platform_device nuri_ncp15wb473_thermistor = {
+   .name   = ncp15wb473,
+   .dev= {
+   .platform_data = ncp15wb473_pdata,
+   },
+};
+
 static struct platform_device *nuri_devices[] __initdata = {
/* Samsung Platform Devices */
emmc_fixed_voltage,
@@ -1024,6 +1069,7 @@ static struct platform_device *nuri_devices[] __initdata 
= {
nuri_gpio_keys,
nuri_lcd_device,
nuri_backlight_device,
+   nuri_ncp15wb473_thermistor,
 };
 
 static void __init nuri_map_io(void)
-- 
1.7.4.1

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[PATCH v2 3/4] Exynos4 NURI: configure ADC.

[MyungJoo Ham]

Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
 arch/arm/mach-exynos4/mach-nuri.c |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos4/mach-nuri.c 
b/arch/arm/mach-exynos4/mach-nuri.c
index 25b9bcb..51f55b4 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -29,6 +29,7 @@
 #include asm/mach/arch.h
 #include asm/mach-types.h
 
+#include plat/adc.h
 #include plat/regs-serial.h
 #include plat/exynos4.h
 #include plat/cpu.h
@@ -1017,6 +1018,7 @@ static struct platform_device *nuri_devices[] __initdata 
= {
s3c_device_i2c3,
s3c_device_i2c5,
i2c9_gpio,
+   s3c_device_adc,
 
/* NURI Devices */
nuri_gpio_keys,
-- 
1.7.4.1

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[PATCH v2 2/4] Exynos4 NURI: configure MAX17042 fuel gauge

[MyungJoo Ham]

Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
 arch/arm/mach-exynos4/mach-nuri.c |   33 +
 1 files changed, 33 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos4/mach-nuri.c 
b/arch/arm/mach-exynos4/mach-nuri.c
index 13b881f..25b9bcb 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -13,8 +13,10 @@
 #include linux/input.h
 #include linux/i2c.h
 #include linux/i2c/atmel_mxt_ts.h
+#include linux/i2c-gpio.h
 #include linux/gpio_keys.h
 #include linux/gpio.h
+#include linux/power/max17042_battery.h
 #include linux/regulator/machine.h
 #include linux/regulator/fixed.h
 #include linux/mfd/max8997.h
@@ -954,6 +956,11 @@ static void __init nuri_pmic_init(void)
gpio_request(gpio, AP_PMIC_IRQ);
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+   gpio = EXYNOS4_GPX2(3);
+   gpio_request(gpio, FUEL_ALERT);
+   s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+   s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
 }
 
 /* GPIO I2C 5 (PMIC) */
@@ -965,6 +972,29 @@ static struct i2c_board_info i2c5_devs[] __initdata = {
},
 };
 
+static struct max17042_platform_data nuri_battery_platform_data = {
+};
+
+/* GPIO I2C 9 (Fuel Gauge) */
+static struct i2c_gpio_platform_data i2c9_gpio_data = {
+   .sda_pin= EXYNOS4_GPY4(0),  /* XM0ADDR_8 */
+   .scl_pin= EXYNOS4_GPY4(1),  /* XM0ADDR_9 */
+};
+static struct platform_device i2c9_gpio = {
+   .name   = i2c-gpio,
+   .id = 9,
+   .dev= {
+   .platform_data  = i2c9_gpio_data,
+   },
+};
+enum { I2C9_MAX17042};
+static struct i2c_board_info i2c9_devs[] __initdata = {
+   [I2C9_MAX17042] = {
+   I2C_BOARD_INFO(max17042, 0x36),
+   .platform_data = nuri_battery_platform_data,
+   },
+};
+
 /* USB EHCI */
 static struct s5p_ehci_platdata nuri_ehci_pdata;
 
@@ -986,6 +1016,7 @@ static struct platform_device *nuri_devices[] __initdata = 
{
s5p_device_ehci,
s3c_device_i2c3,
s3c_device_i2c5,
+   i2c9_gpio,
 
/* NURI Devices */
nuri_gpio_keys,
@@ -1012,6 +1043,8 @@ static void __init nuri_machine_init(void)
s3c_i2c5_set_platdata(NULL);
i2c5_devs[I2C5_MAX8997].irq = gpio_to_irq(EXYNOS4_GPX0(7));
i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
+   i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3));
+   i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
 
nuri_ehci_init();
clk_xusbxti.rate = 2400;
-- 
1.7.4.1

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Re: Re: [PATCH v2 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 FIMD and LTE480WV platform-lcd

[JinGoo Han]

Hi, Tushar Behera.

 -Original Message-
 From: linux-samsung-soc-ow...@vger.kernel.org [mailto:linux-samsung-soc-
 ow...@vger.kernel.org] On Behalf Of Tushar Behera
 Sent: Tuesday, June 21, 2011 12:47 PM
 To: Jingoo Han
 Cc: Kukjin Kim; Paul Mundt; linux-samsung-soc@vger.kernel.org; Jonghun Han;
 Anand Kumar N; Thomas Abraham; Sylwester Nawrocki; Marek Szyprowski;
 Kyungmin Park; Inki Dae; ARM Linux; Ben Dooks
 Subject: Re: [PATCH v2 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4
 FIMD and LTE480WV platform-lcd
 
 Hi,
 
 On Friday 17 June 2011 06:32 PM, Jingoo Han wrote:
  From: Jonghun Hanjonghun@samsung.com
 
  This patch adds support EXYNOS4 FIMD0 and LTE480WV LCD pannel.
 
  Signed-off-by: Jonghun Hanjonghun@samsung.com
  Signed-off-by: Jingoo Hanjg1@samsung.com
  ---
arch/arm/mach-exynos4/mach-smdkc210.c |   74
 +
arch/arm/mach-exynos4/mach-smdkv310.c |   74
 +
2 files changed, 148 insertions(+), 0 deletions(-)
 
 
 There are variants of SMDKV310 boards that don't use LTE480WV LCD panel.
 Won't it be better to provide an option of selecting the LCD panel
 through config file and adding the panel code accordingly?

 Also, the panel code can be consolidated at a single location and used
 in appropriate machine files.
 
Do you have a patch about that?
If you make a patch about your suggestion, please submit it.
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Re: Re: [PATCH v2 1/5] ARM: EXYNOS4: Change clock name for FIMD

[JinGoo Han]

 -Original Message-
 From: Sylwester Nawrocki [mailto:s.nawro...@samsung.com]
 Sent: Monday, June 20, 2011 6:48 PM
 To: jg1@samsung.com
 Cc: Sylwester Nawrocki; Kukjin Kim; Paul Mundt; linux-samsung-
 s...@vger.kernel.org; Jong-Hun Han; ANAND KUMAR N; THOMAS P ABRAHAM; Marek
 Szyprowski; Kyungmin Park; In-Ki Dae; ARM Linux; Ben Dooks
 Subject: Re: [PATCH v2 1/5] ARM: EXYNOS4: Change clock name for FIMD
 
 Hi JinGoo,
 
 On 06/20/2011 09:14 AM, JinGoo Han wrote:
  Hi, Sylwester Nawrocki.
  I appreciate your review and suggestion.
 
  Please, refer to the LCD contoller clock table as follows:
 
 ok, thanks for the update.
 
   - s3c2440 uses 's3c2410fb.c', not 's3c-fb.c' since  LCD controller IP is
 different.
 However, s3c2443 uses 's3c-fb.c'. So I add s3c2443 to table instead of
 s3c2440.
 
 Yes, I was aware of that. My bad to put s3c2440 in the table.
 
   - s3c6410 has SCLK_LCD, but, clock name is not defined.
   - Exynos4 does not use name HCLK.
 
| LCD controller||
| (IP core) clock   | LCD pixel clock|
  --++---+
  s3c2443   |  HCLK (lcd)   | x  |  DISPCLK (display-if) |
  --++---+
  s3c6410   |  HCLK (lcd)   | x  |  SCLK_LCD  (N/A)  |
  --++---+
  s5pc100   |  HCLK (lcd)   | x  |  SCLK_LCD  (sclk_lcd) |
  --++---+
  s5pv210   |  HCLK_DSYS (lcd)  | x  |  SCLK_FIMD (sclk_fimd)|
  --+---++
  exynos4   |  ACLK_160 (fimd)  | O  |  SCLK_FIMD (sclk_fimd)|
  --++---+
  ^^^
 In mach-exynos4/clock.c this clock is described as ACLK_133 (lcd)
I cannot find it.
Let me know where 'fimd' is described as ACLK_133.
Anyway, according to datasheet, this clock is described as ACLK_160.
 
 
  s3c2443, s3c6410, s5pc100 and s5pv210 don't use 'sclk_lcd' or
 'sclk_fimd'.
  'lcd' clock is also used to generate the LCD pixel clock.
 
  My point is that LCD controller clock should be named lcd for
 consistence.
 
 Yes, I agree. After thinking about it a bit more I was going to propose
 that too.
 
  If there is not mux for lcd pixel clock in case of exynos4, sclk_fimd
 will be set
  in machine directory.
 
 OK, you patch for s3c-fb driver looks like a significant improvement
 comparing
 to the original one. But I think we should remove the callback into
 machine
 code.
 The driver could just directly be doing clk_get(dev, sclk_fimd); If this
 succeeds and clksel option is not set in the IP variant then the driver
 should
 treat sclk_fimd as pixel clock, i.e. it will set its frequency and
 enable it.
 It should not care about setting the parent for sclk_fimd, this should
 be done before s3c-fb probe is called.
 
 The problem is that I don't know what to do it the bootloader does not set
 a parent clock for sclk_fimd..
 The board code could just get sclk_fimd and set mout_mpll as its parent,
 like
 it's done in your patch:
 [PATCH v2 3/5] ARM: EXYNOS4: Add platform device and helper functions for
 FIMD
 (except passing a pointer to the driver).
 
 However there have been objections to put such things in the board code in
 the past.
 In case of camera clocks we used to have internally a function in the
 machine
 file setting the parent clocks, until bootloader was modified to configure
 them.
 
 
  As you mentioned, I also think that we need to create two clock
 connection ids
  such as  bus_ck, pix_ck in order to use SCLK_LCD or SCLK_FIMD.
  Moreover, 'lcd' in s5pv210 should be changed to 'fimd' according to
 s5pv210 datasheet.
 
 Yeah, that makes sense.
 
  However, it requires many works to convert.
 
 It's a bit laborious. But it's doable.
 
 
  So, I think that 'two clock connection ids' patch would be submitted
 later,
  after committing the patches that I submitted on last Friday.
 
 I agree with that, given that the callback is removed from the platform
 data
 structure.
OK. The callback will be removed from the platform data structure.
 We need to get ourselves onto path of migration to the device tree and
 IMHO
 adding more callbacks to board code is a step in opposite direction.
 
 
 Thanks,
 S.

[PATCH] ARM: EXYNOS4: Fix secondary CPU boot after wake-up

[Inderpal Singh]

1. After wake-up, the system-wide flags register loses its value.
   Hence, write the address of secondary startup function to
   successfully boot the secondary CPU.

2. Changes SGI1 to SGI0 for secondary CPU boot up

Signed-off-by: Inderpal Singh inderpa...@samsung.com
---
1. The below patch is mandatory to boot secondary CPU after wake-up from sleep
http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/4850

2. The change SGI1 to SGI0 for secondary CPU boot up is done as discussed 
at following link
http://comments.gmane.org/gmane.linux.kernel.samsung-soc/4877

 arch/arm/mach-exynos4/platsmp.c |9 -
 1 files changed, 8 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index c5e65a0..061260c 100644
--- a/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -101,11 +101,18 @@ int __cpuinit boot_secondary(unsigned int cpu, struct 
task_struct *idle)
write_pen_release(cpu);
 
/*
+   * After wake-up, the system-wide flags register loses its value.
+   * Hence, write the address of secondary startup function again.
+   */ 
+   __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), 
S5P_VA_SYSRAM);
+
+
+   /*
 * Send the secondary CPU a soft interrupt, thereby causing
 * the boot monitor to read the system wide flags register,
 * and branch to the address found there.
 */
-   gic_raise_softirq(cpumask_of(cpu), 1);
+   gic_raise_softirq(cpumask_of(cpu), 0);
 
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
-- 
1.7.1

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