Re: [PATCH 11/13] ARM: gpio: consolidate trivial gpiolib implementations
2011/8/9 Russell King - ARM Linux li...@arm.linux.org.uk: Consolidate 24 trivial gpiolib implementions out of mach/gpio.h into asm/gpio.h. This is basically the include of asm-generic/gpio.h and the definition of gpio_get_value, gpio_set_value, and gpio_cansleep as described in Documentation/gpio.txt Signed-off-by: Russell King rmk+ker...@arm.linux.org.uk reaks compile of plat-nomadik due to missing u32, feel free to fold in the below fix. With that it's Tested-by: Linus Walleij linus.wall...@linaro.org for Nomadik, U300 and Ux500. From 2e4496fc7643d804ccf50a8efe1a0304210176d1 Mon Sep 17 00:00:00 2001 From: Linus Walleij linus.wall...@linaro.org Date: Wed, 10 Aug 2011 09:51:16 +0200 Subject: [PATCH] plat-nomadik: small fixup for gpio.h Removing the generic gpio.h broke compilation of the Nomadik GPIO driver since it implicitly got u32 from it. Explicitly include linux/kernel.h so we get u32 defined. Signed-off-by: Linus Walleij linus.wall...@linaro.org --- arch/arm/plat-nomadik/include/plat/gpio.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/plat-nomadik/include/plat/gpio.h b/arch/arm/plat-nomadik/include/plat/gpio.h index cf0b78b..b894a53 100644 --- a/arch/arm/plat-nomadik/include/plat/gpio.h +++ b/arch/arm/plat-nomadik/include/plat/gpio.h @@ -12,6 +12,8 @@ #ifndef __ASM_PLAT_GPIO_H #define __ASM_PLAT_GPIO_H +#include linux/kernel.h + /* * nmk_gpio and NMK_GPIO stand for Nomadik GPIO, leaving * the gpio namespace for generic and cross-machine functions -- 1.7.3.2 Thanks, Linus Walleij -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM:EXYNOS4: Add the missing clock of EXYNOS4210 to remove leakage power
Singed-off-by: Chanwoo Choi cw00.c...@samsung.com
Singed-off-by: Donggeun Kim dg77@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos4/clock.c | 295 +
arch/arm/mach-exynos4/include/mach/regs-pmu.h |6 +
2 files changed, 301 insertions(+), 0 deletions(-)
mode change 100644 = 100755 arch/arm/mach-exynos4/clock.c
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
old mode 100644
new mode 100755
index 851dea0..c49474a
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -123,6 +123,36 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int
enable)
return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
}
+static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
+}
+
+static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
+}
+
+static int exynos4_clk_ip_leftbus_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKGATE_IP_LEFTBUS, clk, enable);
+}
+
+static int exynos4_clk_ip_rightbus_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKGATE_IP_RIGHTBUS, clk, enable);
+}
+
+static int exynos4_clk_ip_g3d_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKGATE_IP_G3D, clk, enable);
+}
+
+static int exynos4_clk_ip_gps_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKGATE_IP_GPS, clk, enable);
+}
+
/* Core list of CMU_CPU side */
static struct clksrc_clk clk_mout_apll = {
@@ -385,6 +415,10 @@ static struct clk init_clocks_off[] = {
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit= (1 5),
}, {
+ .name = jpeg,
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit= (1 6),
+ }, {
.name = fimc,
.devname= exynos4-fimc.0,
.enable = exynos4_clk_ip_cam_ctrl,
@@ -415,11 +449,49 @@ static struct clk init_clocks_off[] = {
.enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit= (1 0),
}, {
+ .name = mie,
+ .devname= exynos4-mie.0,
+ .enable = exynos4_clk_ip_lcd0_ctrl,
+ .ctrlbit= (1 1),
+ }, {
+ .name = mie,
+ .devname= exynos4-mie.1,
+ .enable = exynos4_clk_ip_lcd1_ctrl,
+ .ctrlbit= (1 1),
+ }, {
+ .name = mdnie,
+ .devname= exynos4-mdnie.0,
+ .enable = exynos4_clk_ip_lcd0_ctrl,
+ .ctrlbit= (1 2),
+ }, {
+ .name = mdnie,
+ .devname= exynos4-mdnie.1,
+ .enable = exynos4_clk_ip_lcd1_ctrl,
+ .ctrlbit= (1 2),
+ }, {
+ .name = dsim,
+ .devname= exynos4-dsim.0,
+ .enable = exynos4_clk_ip_lcd0_ctrl,
+ .ctrlbit= (1 3),
+ }, {
+ .name = dsim,
+ .devname= exynos4-dsim.1,
+ .enable = exynos4_clk_ip_lcd1_ctrl,
+ .ctrlbit= (1 3),
+ }, {
+ .name = pciephy,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit= (1 2),
+ }, {
.name = sataphy,
.parent = clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit= (1 3),
}, {
+ .name = tsi,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit= (1 4),
+ }, {
.name = hsmmc,
.devname= s3c-sdhci.0,
.parent = clk_aclk_133.clk,
@@ -449,6 +521,51 @@ static struct clk init_clocks_off[] = {
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit= (1 9),
}, {
+ .name = srom,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit= (1 11),
+ }, {
+ .name = pcie,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit= (1 14),
+ }, {
+ .name = onenand,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit= (1 15),
+ }, {
+ .name = nfcon,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit
[PATCH 0/2] Update uart irq handling for s3c64xx and later SoC's
s3c64xx and later SoC's include the uart interrupt mask and pending registers in the uart controller, unlike their s3c24xx predecessor. This allows the uart irq handling to be moved from the platform code to the driver. This patchset does this change and removes all the macros that will not be required with this update. Thomas Abraham (2): serial: samsung: Add unified interrupt handler for s3c64xx and later SoC's ARM: SAMSUNG: Remove uart irq handling from plaform code arch/arm/Kconfig |1 - arch/arm/mach-s3c64xx/dev-uart.c | 60 ++--- arch/arm/mach-s3c64xx/include/mach/irqs.h| 30 -- arch/arm/mach-s3c64xx/irq.c | 25 - arch/arm/plat-s5p/Kconfig|1 - arch/arm/plat-s5p/dev-uart.c | 84 +++--- arch/arm/plat-s5p/include/plat/irqs.h| 35 --- arch/arm/plat-s5p/irq.c | 34 --- arch/arm/plat-samsung/Kconfig|5 - arch/arm/plat-samsung/Makefile |1 - arch/arm/plat-samsung/include/plat/regs-serial.h |5 + arch/arm/plat-samsung/irq-uart.c | 96 --- drivers/tty/serial/samsung.c | 107 +++--- drivers/tty/serial/samsung.h |1 + 14 files changed, 121 insertions(+), 364 deletions(-) delete mode 100644 arch/arm/plat-samsung/irq-uart.c -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] ARM: SAMSUNG: Remove uart irq handling from plaform code
With uart tx/rx/err interrupt handling moved into the driver for s3c64xx
and later SoC's, the uart interrupt handling in plaform code can be removed.
The uart device irq resources is reduced to one and the related unused
macros are removed.
Suggested-by: Grant Likely grant.lik...@secretlab.ca
CC: Ben Dooks ben-li...@fluff.org
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/Kconfig |1 -
arch/arm/mach-s3c64xx/dev-uart.c | 60 ++
arch/arm/mach-s3c64xx/include/mach/irqs.h| 30 ---
arch/arm/mach-s3c64xx/irq.c | 25 --
arch/arm/plat-s5p/Kconfig|1 -
arch/arm/plat-s5p/dev-uart.c | 84 +++
arch/arm/plat-s5p/include/plat/irqs.h| 35
arch/arm/plat-s5p/irq.c | 34
arch/arm/plat-samsung/Kconfig|5 -
arch/arm/plat-samsung/Makefile |1 -
arch/arm/plat-samsung/include/plat/regs-serial.h |5 +
arch/arm/plat-samsung/irq-uart.c | 96 --
12 files changed, 25 insertions(+), 352 deletions(-)
delete mode 100644 arch/arm/plat-samsung/irq-uart.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2c71a8f..94228f7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -723,7 +723,6 @@ config ARCH_S3C64XX
select ARCH_REQUIRE_GPIOLIB
select SAMSUNG_CLKSRC
select SAMSUNG_IRQ_VIC_TIMER
- select SAMSUNG_IRQ_UART
select S3C_GPIO_TRACK
select S3C_GPIO_PULL_UPDOWN
select S3C_GPIO_CFG_S3C24XX
diff --git a/arch/arm/mach-s3c64xx/dev-uart.c b/arch/arm/mach-s3c64xx/dev-uart.c
index f797f74..c681b99 100644
--- a/arch/arm/mach-s3c64xx/dev-uart.c
+++ b/arch/arm/mach-s3c64xx/dev-uart.c
@@ -37,21 +37,10 @@ static struct resource s3c64xx_uart0_resource[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = IRQ_S3CUART_RX0,
- .end= IRQ_S3CUART_RX0,
+ .start = IRQ_UART0,
+ .end= IRQ_UART0,
.flags = IORESOURCE_IRQ,
},
- [2] = {
- .start = IRQ_S3CUART_TX0,
- .end= IRQ_S3CUART_TX0,
- .flags = IORESOURCE_IRQ,
-
- },
- [3] = {
- .start = IRQ_S3CUART_ERR0,
- .end= IRQ_S3CUART_ERR0,
- .flags = IORESOURCE_IRQ,
- }
};
static struct resource s3c64xx_uart1_resource[] = {
@@ -61,19 +50,8 @@ static struct resource s3c64xx_uart1_resource[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = IRQ_S3CUART_RX1,
- .end= IRQ_S3CUART_RX1,
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
- .start = IRQ_S3CUART_TX1,
- .end= IRQ_S3CUART_TX1,
- .flags = IORESOURCE_IRQ,
-
- },
- [3] = {
- .start = IRQ_S3CUART_ERR1,
- .end= IRQ_S3CUART_ERR1,
+ .start = IRQ_UART1,
+ .end= IRQ_UART1,
.flags = IORESOURCE_IRQ,
},
};
@@ -85,19 +63,8 @@ static struct resource s3c6xx_uart2_resource[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = IRQ_S3CUART_RX2,
- .end= IRQ_S3CUART_RX2,
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
- .start = IRQ_S3CUART_TX2,
- .end= IRQ_S3CUART_TX2,
- .flags = IORESOURCE_IRQ,
-
- },
- [3] = {
- .start = IRQ_S3CUART_ERR2,
- .end= IRQ_S3CUART_ERR2,
+ .start = IRQ_UART2,
+ .end= IRQ_UART2,
.flags = IORESOURCE_IRQ,
},
};
@@ -109,19 +76,8 @@ static struct resource s3c64xx_uart3_resource[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = IRQ_S3CUART_RX3,
- .end= IRQ_S3CUART_RX3,
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
- .start = IRQ_S3CUART_TX3,
- .end= IRQ_S3CUART_TX3,
- .flags = IORESOURCE_IRQ,
-
- },
- [3] = {
- .start = IRQ_S3CUART_ERR3,
- .end= IRQ_S3CUART_ERR3,
+ .start = IRQ_UART3,
+ .end= IRQ_UART3,
.flags = IORESOURCE_IRQ,
},
};
diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h
b/arch/arm/mach-s3c64xx/include/mach/irqs.h
index c026f67..443f85b 100644
--- a/arch/arm/mach-s3c64xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h
@@ -27,36 +27,6 @@
#define IRQ_VIC0_BASE S3C_IRQ(0)
#define IRQ_VIC1_BASE S3C_IRQ(32)
-/* UART interrupts, each UART has 4 intterupts per channel so
- * use
[PATCH 0/2] Remove hw_addr dma leftovers from S3C24xx machs
While trying to sort the dma for S3C2416 I stumbled open the hw_addr declarations in the other dma.c files. It took me a while to figure out that they seem to be some sort of leftover, i.e. they are used in dma-pl080.c of the old Samsung kernels based on 2.6.21 but nowhere in current kernels. Therefore I think removing this stuff is appropriate. The patches apply against current linux-next and are compile-tested against s3c2410_defconfig and mini2440_defconfig. Heiko Stuebner (2): Remove hw_addr from s3c24XX dma channel declarations Remove s3c24xx_dma_addr definition arch/arm/mach-s3c2410/dma.c | 14 --- arch/arm/mach-s3c2412/dma.c | 18 -- arch/arm/mach-s3c2440/dma.c | 17 - arch/arm/mach-s3c2443/dma.c | 27 -- arch/arm/plat-samsung/include/plat/dma-s3c24xx.h |6 - 5 files changed, 0 insertions(+), 82 deletions(-) -- 1.7.5.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] Remove hw_addr from s3c24XX dma channel declarations
According to commit c4806174c516d26bf4a72db1789cfc96e4950d07
(ARM: S3C2412: DMA: Remove I2S FIFO address) the S3C DMA API does not
make use of hw_addr.to/from declared for some of the channels in
mach-s3c24XX/dma.c
Grepping through the kernel also did non reveal any new users of
these properties since the mentioned commit.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
arch/arm/mach-s3c2410/dma.c | 14 --
arch/arm/mach-s3c2412/dma.c | 18 --
arch/arm/mach-s3c2440/dma.c | 17 -
arch/arm/mach-s3c2443/dma.c | 27 ---
4 files changed, 0 insertions(+), 76 deletions(-)
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index 0d8e043..dbe43df 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -47,38 +47,26 @@ static struct s3c24xx_dma_map __initdata
s3c2410_dma_mappings[] = {
.channels[0]= S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
.channels[2]= S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
.channels[3]= S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
- .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
- .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
},
[DMACH_SPI0] = {
.name = spi0,
.channels[1]= S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
- .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
- .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
},
[DMACH_SPI1] = {
.name = spi1,
.channels[3]= S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
- .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
- .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
},
[DMACH_UART0] = {
.name = uart0,
.channels[0]= S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
- .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
- .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
},
[DMACH_UART1] = {
.name = uart1,
.channels[1]= S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
- .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
- .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
},
[DMACH_UART2] = {
.name = uart2,
.channels[3]= S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
- .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
- .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
},
[DMACH_TIMER] = {
.name = timer,
@@ -90,12 +78,10 @@ static struct s3c24xx_dma_map __initdata
s3c2410_dma_mappings[] = {
.name = i2s-sdi,
.channels[1]= S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
.channels[2]= S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
- .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
},
[DMACH_I2S_OUT] = {
.name = i2s-sdo,
.channels[2]= S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
- .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
},
[DMACH_USB_EP1] = {
.name = usb-ep1,
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index 7abecfc..c61e326 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -50,64 +50,46 @@ static struct s3c24xx_dma_map __initdata
s3c2412_dma_mappings[] = {
.name = sdi,
.channels = MAP(S3C2412_DMAREQSEL_SDI),
.channels_rx= MAP(S3C2412_DMAREQSEL_SDI),
- .hw_addr.to = S3C2410_PA_SDI + S3C2410_SDIDATA,
- .hw_addr.from = S3C2410_PA_SDI + S3C2410_SDIDATA,
},
[DMACH_SPI0] = {
.name = spi0,
.channels = MAP(S3C2412_DMAREQSEL_SPI0TX),
.channels_rx= MAP(S3C2412_DMAREQSEL_SPI0RX),
- .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
- .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
},
[DMACH_SPI1] = {
.name = spi1,
.channels = MAP(S3C2412_DMAREQSEL_SPI1TX),
.channels_rx= MAP(S3C2412_DMAREQSEL_SPI1RX),
- .hw_addr.to = S3C2410_PA_SPI + S3C2412_SPI1 +
S3C2410_SPTDAT,
- .hw_addr.from = S3C2410_PA_SPI + S3C2412_SPI1 +
S3C2410_SPRDAT,
},
[DMACH_UART0] = {
.name = uart0,
.channels = MAP(S3C2412_DMAREQSEL_UART0_0),
.channels_rx= MAP(S3C2412_DMAREQSEL_UART0_0),
- .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
-
Re: [PATCH 1/2] serial: samsung: Add unified interrupt handler for s3c64xx and later SoC's
On Wed, 10 Aug 2011 15:51:19 +0530 Thomas Abraham thomas.abra...@linaro.org wrote: s3c64xx and later SoC's include the interrupt mask and pending registers in the uart controller, unlike the s3c24xx SoC's which have these registers in the interrupt controller. When the mask and pending registers are part of the uart controller, a unified interrupt handler can handle the tx/rx interrupt. With this, the static reservation of interrupt numbers for the uart tx/rx/err interrupts in the linux irq space is not required and simplifies adding device tree support. Really only hardware changes so for the tty touching aspect of it Acked-by: Alan Cox a...@linux.intel.com -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC][PATCH 2/2] spi: s3c64xx: Use clkdev for bus clock lookup
Hi Jassi, On Tue, Aug 9, 2011 at 6:13 PM, Jassi Brar jassisinghb...@gmail.com wrote: On Tue, Aug 9, 2011 at 7:28 PM, Padmavathi Venna padm...@samsung.com wrote: SPI driver is modified to lookup the bus clock using the alias name instead of getting clock name and clock number from platform data. Cool. Driver is modified to get the best source clock among the available source clocks for the required frequency. I am not sure if this driver should be deciding which clock is 'best' for it. Because ... 1) Usually it's the board designer who decides which clock to run at what speed based upon target device. So ideally, based upon use-case the driver should simply get the 'best' clock from board via platform in a format that is compliant to the 'generic clock api'. As per your comment I modified the code for board designer to supply the required list of source clocks. If this list is NULL then it uses the all available clock sources. I will resubmit this patch. 2) We are not changing source clock rates(and we should not). So the 'best' clock found, might still be way off in accuracy. And when we can't anyway guarantee accuracy, why not leave the decision to the board designer who might, say, select the source clock good enough to be useful to more than one controller yet not absolutely accurate for any ? Yes. We are not getting the accurate frequency but we are able to get best frequency. 3) It keeps enabled 3 unused clocks all the time. I modified the code to enable only the best source clock. I will resubmit this patch. diff --git a/drivers/spi/spi_s3c64xx.c b/drivers/spi/spi_s3c64xx.c index 8945e20..d7c979d 100644 --- a/drivers/spi/spi_s3c64xx.c +++ b/drivers/spi/spi_s3c64xx.c @@ -132,6 +132,9 @@ #define RXBUSY (12) #define TXBUSY (13) +#define MAX_SPI_BUS_CLK (4) +#define MAX_PSR (256) Btw, #define MAX_SPI_BUS_CLK 4 #define MAX_PSR 256 is safe ... even safer than with two on! Modified. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC][PATCH 1/2] S5PV210: SPI: Add clkdev support
Hi Sylwester,
On Tue, Aug 9, 2011 at 7:12 PM, Sylwester Nawrocki
s.nawro...@samsung.com wrote:
[corrected Jassi's email address]
On 08/09/2011 03:57 PM, Padmavathi Venna wrote:
Create a clkdev alias for spi bus clock and modify the spi
driver to lookup the clock using the alias name instead of
passing clock name and clock number from SPI platform data.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
This patch is tested for S5PV210 platform and similar
changes can be adopted for rest of the Samsung's s3c
and s5p platforms, if this approach is accepted.
It is a bit surprising to me how you do intend to use the clock aliases.
Are we seriously going to be creating clock con_id aliases for most
of the available devices ? It doesn't sound sane to me..
We don't need to create the alias names for all the devices. But we need
to create only for those which need clock information from platform data.
As far as I know we need to create for spi,hsmmc,uart and iis.
Wouldn't it be possible to avoid the aliases by correcting the clock
registration process ?
Yes it is possible but we don't have the flexibility to create the alias names
only for the required clocks.
arch/arm/mach-s5pv210/dev-spi.c | 31
++---
arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | 7 +
2 files changed, 27 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-s5pv210/dev-spi.c
b/arch/arm/mach-s5pv210/dev-spi.c
...
-void __init s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
+void __init s5pv210_spi_set_info(int cntrlr, int num_cs)
{
struct s3c64xx_spi_info *pd;
+ struct device *dev;
+ char devname[16], clk_alias_name[16];
+ int ret, i;
/* Reject invalid configuration */
- if (!num_cs || src_clk_nr 0
- || src_clk_nr S5PV210_SPI_SRCCLK_SCLK) {
+ if (!num_cs) {
printk(KERN_ERR %s: Invalid SPI configuration\n, __func__);
return;
}
@@ -159,9 +162,11 @@ void __init s5pv210_spi_set_info(int cntrlr, int
src_clk_nr, int num_cs)
switch (cntrlr) {
case 0:
pd = s5pv210_spi0_pdata;
+ dev = s5pv210_device_spi0.dev;
break;
case 1:
pd = s5pv210_spi1_pdata;
+ dev = s5pv210_device_spi1.dev;
break;
default:
printk(KERN_ERR %s: Invalid SPI controller(%d)\n,
@@ -169,7 +174,23 @@ void __init s5pv210_spi_set_info(int cntrlr, int
src_clk_nr, int num_cs)
return;
}
+ sprintf(devname, s3c64xx-spi.%d, cntrlr);
+
+ for (i = 0; i ARRAY_SIZE(spi_src_clks); i++) {
+ sprintf(clk_alias_name, clk_spi_bus%d, i);
+
+ if (!strcmp(spi_src_clks[i], pclk))
+ ret = clk_add_alias(clk_alias_name, devname,
+ spi_src_clks[i], NULL);
+ else
+ ret = clk_add_alias(clk_alias_name, devname,
+ spi_src_clks[i], dev);
+ if (ret) {
+ printk(KERN_ERR failed to create alias for
+ SPI%d source clock%d\n, cntrlr, i);
+ continue;
+ }
+ }
+
pd-num_cs = num_cs;
- pd-src_clk_nr = src_clk_nr;
- pd-src_clk_name = spi_src_clks[src_clk_nr];
}
...
--
Thanks,
Sylwester
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[RFC][PATCH V2 1/2] S5PV210: SPI: Add clkdev support
Create a clkdev alias for spi bus clock and modify the spi
driver to lookup the clock using the alias name instead of
passing clock name and clock number from SPI platform data.
Board designer has the option to pass the list of bus clocks
that are going to be used with SPI controller.If that list of
clocks are null then it uses all the available clocks.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
This patch is tested for S5PV210 platform and similar
changes can be adopted for rest of the Samsung's s3c
and s5p platforms, if this approach is accepted.
arch/arm/mach-s5pv210/dev-spi.c | 38 +++---
arch/arm/plat-samsung/include/plat/s3c64xx-spi.h |7 +---
2 files changed, 34 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-s5pv210/dev-spi.c b/arch/arm/mach-s5pv210/dev-spi.c
index eaf9a7b..503a3f4 100644
--- a/arch/arm/mach-s5pv210/dev-spi.c
+++ b/arch/arm/mach-s5pv210/dev-spi.c
@@ -11,6 +11,7 @@
#include linux/platform_device.h
#include linux/dma-mapping.h
#include linux/gpio.h
+#include linux/clk.h
#include mach/dma.h
#include mach/map.h
@@ -145,13 +146,16 @@ struct platform_device s5pv210_device_spi1 = {
},
};
-void __init s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
+void __init s5pv210_spi_set_info(int cntrlr, int num_cs, char *list[])
{
struct s3c64xx_spi_info *pd;
+ struct device *dev;
+ char devname[16], clk_alias_name[16];
+ int ret, i;
+ char **clk_list;
/* Reject invalid configuration */
- if (!num_cs || src_clk_nr 0
- || src_clk_nr S5PV210_SPI_SRCCLK_SCLK) {
+ if (!num_cs) {
printk(KERN_ERR %s: Invalid SPI configuration\n, __func__);
return;
}
@@ -159,9 +163,11 @@ void __init s5pv210_spi_set_info(int cntrlr, int
src_clk_nr, int num_cs)
switch (cntrlr) {
case 0:
pd = s5pv210_spi0_pdata;
+ dev = s5pv210_device_spi0.dev;
break;
case 1:
pd = s5pv210_spi1_pdata;
+ dev = s5pv210_device_spi1.dev;
break;
default:
printk(KERN_ERR %s: Invalid SPI controller(%d)\n,
@@ -169,7 +175,29 @@ void __init s5pv210_spi_set_info(int cntrlr, int
src_clk_nr, int num_cs)
return;
}
+ sprintf(devname, s3c64xx-spi.%d, cntrlr);
+
+ if (list)
+ clk_list = list;
+ else
+ clk_list = spi_src_clks;
+
+ for (i = 0; i = S5PV210_SPI_SRCCLK_SCLK ; i++) {
+ sprintf(clk_alias_name, clk_spi_bus%d, i);
+
+ if (clk_list[i]) {
+ if (!strcmp(clk_list[i], pclk))
+ ret = clk_add_alias(clk_alias_name, devname,
+ clk_list[i], NULL);
+ else
+ ret = clk_add_alias(clk_alias_name, devname,
+ clk_list[i], dev);
+ if (ret) {
+ printk(KERN_ERR failed to create alias for
+SPI%d source clock%d\n, cntrlr, i);
+ continue;
+ }
+ }
+ }
pd-num_cs = num_cs;
- pd-src_clk_nr = src_clk_nr;
- pd-src_clk_name = spi_src_clks[src_clk_nr];
}
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index 4c16fa3..acdd337 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -30,8 +30,6 @@ struct s3c64xx_spi_csinfo {
/**
* struct s3c64xx_spi_info - SPI Controller defining structure
- * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
- * @src_clk_name: Platform name of the corresponding clock.
* @clk_from_cmu: If the SPI clock/prescalar control block is present
* by the platform's clock-management-unit and not in SPI controller.
* @num_cs: Number of CS this controller emulates.
@@ -42,8 +40,6 @@ struct s3c64xx_spi_csinfo {
* @tx_st_done: Depends on tx fifo_lvl field
*/
struct s3c64xx_spi_info {
- int src_clk_nr;
- char *src_clk_name;
bool clk_from_cmu;
int num_cs;
@@ -61,7 +57,6 @@ struct s3c64xx_spi_info {
* s3c64xx_spi_set_info - SPI Controller configure callback by the board
* initialization code.
* @cntrlr: SPI controller number the configuration is for.
- * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
* @num_cs: Number of elements in the 'cs' array.
*
* Call this from machine init code for each SPI Controller that
@@ -69,7 +64,7 @@ struct s3c64xx_spi_info {
*/
extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
extern void
[RFC][PATCH V2 2/2] spi: s3c64xx: Use clkdev for bus clock lookup
SPI driver is modified to lookup the bus clock using the
alias name instead of getting clock name and clock
number from platform data.
Driver is modified to get the best source clock among the
available source clocks for the required frequency.At a time
it enables only the required clock for the required frequency.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
drivers/spi/spi_s3c64xx.c | 164 ++---
1 files changed, 110 insertions(+), 54 deletions(-)
diff --git a/drivers/spi/spi_s3c64xx.c b/drivers/spi/spi_s3c64xx.c
index 8945e20..6c4fc1b 100644
--- a/drivers/spi/spi_s3c64xx.c
+++ b/drivers/spi/spi_s3c64xx.c
@@ -132,6 +132,9 @@
#define RXBUSY(12)
#define TXBUSY(13)
+#define MAX_SPI_BUS_CLK 4
+#define MAX_PSR 256
+
/**
* struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
* @clk: Pointer to the spi clock.
@@ -172,6 +175,9 @@ struct s3c64xx_spi_driver_data {
unsignedstate;
unsignedcur_mode, cur_bpw;
unsignedcur_speed;
+ struct clk *bus_clk_list[MAX_SPI_BUS_CLK];
+ unsignedcur_clk;
+ unsignedold_spd;
};
static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
@@ -411,6 +417,65 @@ static inline void disable_cs(struct
s3c64xx_spi_driver_data *sdd,
cs-set_level(cs-line, spi-mode SPI_CS_HIGH ? 0 : 1);
}
+static int s3c64xx_spi_best_clk_src(struct spi_device *spi)
+{
+ struct s3c64xx_spi_driver_data *sdd;
+ struct clk *clksrc;
+ unsigned long rate;
+ unsigned int delta;
+ unsigned int best = UINT_MAX;
+ int psr, div, i, best_div, best_src;
+
+ sdd = spi_master_get_devdata(spi-master);
+
+ for (i = 0; i MAX_SPI_BUS_CLK; i++) {
+ clksrc = sdd-bus_clk_list[i];
+ if (!clksrc)
+ delta = UINT_MAX;
+ else {
+ rate = clk_get_rate(clksrc);
+ for (psr = 0; psr MAX_PSR; psr++) {
+ div = (2 * (psr + 1));
+ if ((rate / div) = spi-max_speed_hz)
+ break;
+ }
+
+ if (psr == MAX_PSR
+ ((rate / div) spi-max_speed_hz)) {
+ dev_dbg(spi-dev, clock%d can't support
+required frequency\n, i);
+ continue;
+ } else {
+ delta = spi-max_speed_hz - (rate / div);
+ dev_dbg(spi-dev, clk %d: rate %lu,
+want %u, got %lu div:%d delta:%u\n,
+ i, rate, spi-max_speed_hz,
+ rate / div, div, delta);
+ }
+ }
+
+ if (delta best) {
+ best = delta;
+ best_src = i;
+ best_div = div;
+ }
+ }
+
+ if (best == UINT_MAX) {
+ dev_err(spi-dev, no clock can support required
+ frequency\n);
+ return -EINVAL;
+ }
+
+ if (sdd-cur_clk != best_src) {
+ clk_disable(sdd-src_clk);
+ sdd-cur_clk = best_src;
+ sdd-src_clk = sdd-bus_clk_list[best_src];
+ clk_enable(sdd-src_clk);
+ }
+ return best_div;
+}
+
static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
{
struct s3c64xx_spi_info *sci = sdd-cntrlr_info;
@@ -470,6 +535,9 @@ static void s3c64xx_spi_config(struct
s3c64xx_spi_driver_data *sdd)
clk_enable(sdd-src_clk);
} else {
/* Configure Clock */
+ writel(sdd-cur_clk S3C64XX_SPI_CLKSEL_SRCSHFT,
+ regs + S3C64XX_SPI_CLK_CFG);
+
val = readl(regs + S3C64XX_SPI_CLK_CFG);
val = ~S3C64XX_SPI_PSR_MASK;
val |= ((clk_get_rate(sdd-src_clk) / sdd-cur_speed / 2 - 1)
@@ -845,6 +913,7 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
struct spi_message *msg;
unsigned long flags;
int err = 0;
+ int div;
if (cs == NULL || cs-set_level == NULL) {
dev_err(spi-dev, No CS for SPI(%d)\n, spi-chip_select);
@@ -884,38 +953,18 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
goto setup_exit;
}
- /* Check if we can provide the requested rate */
+ /* Get the best clock source for the requested rate */
if (!sci-clk_from_cmu) {
- u32 psr, speed;
-
- /* Max possible */
- speed = clk_get_rate(sdd-src_clk) / 2 / (0 + 1);
-
-
Re: [RFC][PATCH 1/2] S5PV210: SPI: Add clkdev support
Hi Padmavathi, On 08/10/2011 02:04 PM, padma venkat wrote: Hi Sylwester, On Tue, Aug 9, 2011 at 7:12 PM, Sylwester Nawrocki s.nawro...@samsung.com wrote: [corrected Jassi's email address] On 08/09/2011 03:57 PM, Padmavathi Venna wrote: Create a clkdev alias for spi bus clock and modify the spi driver to lookup the clock using the alias name instead of passing clock name and clock number from SPI platform data. Signed-off-by: Padmavathi Venna padm...@samsung.com --- This patch is tested for S5PV210 platform and similar changes can be adopted for rest of the Samsung's s3c and s5p platforms, if this approach is accepted. It is a bit surprising to me how you do intend to use the clock aliases. Are we seriously going to be creating clock con_id aliases for most of the available devices ? It doesn't sound sane to me.. We don't need to create the alias names for all the devices. But we need to create only for those which need clock information from platform data. As far as I know we need to create for spi,hsmmc,uart and iis. That's already a lot. Just to clarify, the clock names were originally passed in platform_data because they differ across SoCs the driver supports, right ? Or are there any other reasons ? The whole idea of the clkdev is not to require any information about the clocks in platform_data. You just need to be registering the clock identifiers *at the device*, not the clock names specific to the machine. The platform code takes care of the translation and the drivers only need to ask clkdev for the 'clock connection id', rather than the original machine clock name. You can do this by adding the aliases, but it's not optimal. You are adding the code which could well be avoided. Wouldn't it be possible to avoid the aliases by correcting the clock registration process ? Yes it is possible but we don't have the flexibility to create the alias names only for the required clocks. By registering proper clock connection ids you would not need the aliases at all. -- Regards, Sylwester -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC][PATCH 2/2] spi: s3c64xx: Use clkdev for bus clock lookup
On Wed, Aug 10, 2011 at 5:33 PM, padma venkat padma@gmail.com wrote: Hi Jassi, On Tue, Aug 9, 2011 at 6:13 PM, Jassi Brar jassisinghb...@gmail.com wrote: On Tue, Aug 9, 2011 at 7:28 PM, Padmavathi Venna padm...@samsung.com wrote: SPI driver is modified to lookup the bus clock using the alias name instead of getting clock name and clock number from platform data. Cool. Driver is modified to get the best source clock among the available source clocks for the required frequency. I am not sure if this driver should be deciding which clock is 'best' for it. Because ... 1) Usually it's the board designer who decides which clock to run at what speed based upon target device. So ideally, based upon use-case the driver should simply get the 'best' clock from board via platform in a format that is compliant to the 'generic clock api'. As per your comment I modified the code for board designer to supply the required list of source clocks. If this list is NULL then it uses the all available clock sources. I will resubmit this patch. No dear. Not a list of clocks (that is property of the platform - not a board). But get just one 'generic clock api' compliant clock from the board and use it. That will keep the driver simple for sure and IIUIC, in future anyways DT would specify source clock for each peripheral. Grant ? -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/4] serial: s5pv210: Add device tree support
Hi Ben,
On 3 August 2011 14:42, Ben Dooks ben-li...@fluff.org wrote:
On Wed, Aug 03, 2011 at 12:08:27AM +0100, Thomas Abraham wrote:
For device tree based probe, the dependecy on pdev-id to attach a
corresponding default port info to the driver's private data is
removed. The fifosize parameter is obtained from the device tree
node and the next available instance of port info is updated
with the fifosize value and attached to the driver's private data.
The default platform data is selected based on the compatible property.
CC: Ben Dooks ben-li...@fluff.org
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
.../devicetree/bindings/serial/samsung_uart.txt | 16 +++
drivers/tty/serial/s5pv210.c | 43
+++-
drivers/tty/serial/samsung.c | 5 ++-
3 files changed, 62 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/serial/samsung_uart.txt
[...]
/* device management */
static int s5p_serial_probe(struct platform_device *pdev)
{
- return s3c24xx_serial_probe(pdev, s5p_uart_inf[pdev-id]);
+ static unsigned int probe_index;
+ unsigned int port = pdev-id;
+ const struct of_device_id *match;
+ struct s3c2410_uartcfg *cfg;
+
+ if (pdev-dev.of_node) {
+ if (of_property_read_u32(pdev-dev.of_node,
+ samsung,uart-fifosize,
+ s5p_uart_inf[probe_index]-fifosize))
+ return -EINVAL;
I'd rather see the fifo size either being a property of the soc itself
or being inferred by the compatible field.
When using the compatible field to infer the fifosize of the
controller, the code looks as listed below.
struct s3c24xx_uart_dt_compat_data {
unsigned int fifosize;
struct s3c2410_uartcfg *uartcfg;
};
static struct s3c2410_uartcfg s5pv310_uart_defcfg = {
.ucon = 0x3c5,
.ufcon = 0x111,
.flags = NO_NEED_CHECK_CLKSRC,
.has_fracval = 1,
};
static struct s3c24xx_uart_dt_compat_data s5pv210_compat_fs256 = {
.fifosize = 256;
.uartcfg = s5pv310_uart_defcfg;
};
static struct s3c24xx_uart_dt_compat_data s5pv210_compat_fs64 = {
.fifosize = 64;
.uartcfg = s5pv310_uart_defcfg;
};
static struct s3c24xx_uart_dt_compat_data s5pv210_compat_fs16 = {
.fifosize = 16;
.uartcfg = s5pv310_uart_defcfg;
};
static const struct of_device_id s5pv210_uart_dt_match[] = {
{ .compatible = samsung,s5pv310-uart-fs256, .data =
s5pv210_compat_fs256 },
{ .compatible = samsung,s5pv310-uart-fs64, .data =
s5pv210_compat_fs64 },
{ .compatible = samsung,s5pv310-uart-fs16, .data =
s5pv210_compat_fs16 },
{},
};
MODULE_DEVICE_TABLE(of, s5pv210_uart_match);
This requires a new structure definition and additional data in the
driver. So I still prefer to use a property in the uart device node to
define the fifosize of the controller.
What would you be your preference? Or is there a better way to obtain
the fifosize?
Thanks,
Thomas.
.driver = {
.name = s5pv210-uart,
.owner = THIS_MODULE,
+ .of_match_table = s5pv210_uart_dt_match,
I think maybe doing something like
.of_match_table = of_match_ptr(5pv210_uart_dt_match),
so we can avoid having the #else and #define 5pv210_uart_dt_match NULL
in a number of places.
},
};
--
Ben Dooks, b...@fluff.org, http://www.fluff.org/ben/
Large Hadron Colada: A large Pina Colada that makes the universe disappear.
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[PATCH 0/4] ARM: EXYNOS4: Support generic Power domain framework for EXYNOS4210
The following patch set use the generic Power domain Framework instead of power domain code depend of Samsung SoC. Chanwoo Choi (4): ARM: EXYNOS4: Support for generic I/O power domains on EXYNOS4210 ARM: EXYNOS4: Support for generic Clock manipulation PM callbacks ARM: EXYNOS4: Delete the power-domain code depend on Samsung SoC ARM: EXYNOS4: Add power domain to use generic Power domain Framework arch/arm/mach-exynos4/Kconfig | 10 +- arch/arm/mach-exynos4/Makefile |4 +- arch/arm/mach-exynos4/dev-pd.c | 139 -- arch/arm/mach-exynos4/include/mach/pm-exynos4210.h | 52 ++ arch/arm/mach-exynos4/include/mach/regs-clock.h|8 + arch/arm/mach-exynos4/mach-nuri.c | 21 ++- arch/arm/mach-exynos4/mach-smdkc210.c | 26 ++- arch/arm/mach-exynos4/mach-smdkv310.c | 23 ++- arch/arm/mach-exynos4/mach-universal_c210.c| 21 ++- arch/arm/mach-exynos4/pm-exynos4210.c | 189 arch/arm/mach-exynos4/pm-runtime.c | 56 ++ arch/arm/plat-samsung/Kconfig |8 - arch/arm/plat-samsung/Makefile |4 - arch/arm/plat-samsung/include/plat/pd.h| 30 --- arch/arm/plat-samsung/pd.c | 95 -- 15 files changed, 377 insertions(+), 309 deletions(-) delete mode 100644 arch/arm/mach-exynos4/dev-pd.c create mode 100644 arch/arm/mach-exynos4/include/mach/pm-exynos4210.h create mode 100644 arch/arm/mach-exynos4/pm-exynos4210.c create mode 100644 arch/arm/mach-exynos4/pm-runtime.c delete mode 100644 arch/arm/plat-samsung/include/plat/pd.h delete mode 100644 arch/arm/plat-samsung/pd.c -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/4] ARM: EXYNOS4: Support for generic I/O power domains on EXYNOS4210
Use the generic power domains support to implement support for
power domain on EXYNOS4210.
I refer to the following patch to implement what configure
the clock-gating control register for block to turn off/on:
http://git.infradead.org/users/kmpark/linux-2.6-samsung/commit/39a81876d034dcbdc2a4c4c4b847b3b49e38870c
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos4/Kconfig |1 +
arch/arm/mach-exynos4/Makefile |1 +
arch/arm/mach-exynos4/include/mach/pm-exynos4210.h | 52 ++
arch/arm/mach-exynos4/include/mach/regs-clock.h|8 +
arch/arm/mach-exynos4/pm-exynos4210.c | 189
5 files changed, 251 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-exynos4/include/mach/pm-exynos4210.h
create mode 100644 arch/arm/mach-exynos4/pm-exynos4210.c
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index 64baca7..8d5e876 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -12,6 +12,7 @@ if ARCH_EXYNOS4
config CPU_EXYNOS4210
bool
select S3C_PL330_DMA
+ select PM_GENERIC_DOMAINS if PM
help
Enable EXYNOS4210 CPU support
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index b7fe1d7..97c31ce 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o
irq-combiner.o
obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o pmu.o
obj-$(CONFIG_PM) += pm.o sleep.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
+obj-$(CONFIG_CPU_EXYNOS4210) += pm-exynos4210.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-exynos4/include/mach/pm-exynos4210.h
b/arch/arm/mach-exynos4/include/mach/pm-exynos4210.h
new file mode 100644
index 000..e36425a
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/pm-exynos4210.h
@@ -0,0 +1,52 @@
+/* linux/arch/arm/mach-exynos4/include/mach/pm-exynos4210.h
+ *
+ * Exynos4210 Power management support
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef PM_EXYNOS4210_H
+#define PM_EXYNOS4210_H
+
+#include linux/pm_domain.h
+
+struct platform_device;
+
+struct exynos4210_pm_domain {
+ struct generic_pm_domain genpd;
+
+ const char *name;
+ void __iomem *base;
+ u32 clkgate_mask;
+ int boot_on;
+};
+
+static inline struct exynos4210_pm_domain *to_exynos4210_pd(
+ struct generic_pm_domain *pd)
+{
+ return container_of(pd, struct exynos4210_pm_domain, genpd);
+}
+
+#ifdef CONFIG_PM
+extern struct exynos4210_pm_domain exynos4210_pd_mfc;
+extern struct exynos4210_pm_domain exynos4210_pd_g3d;
+extern struct exynos4210_pm_domain exynos4210_pd_lcd0;
+extern struct exynos4210_pm_domain exynos4210_pd_lcd1;
+extern struct exynos4210_pm_domain exynos4210_pd_tv;
+extern struct exynos4210_pm_domain exynos4210_pd_cam;
+extern struct exynos4210_pm_domain exynos4210_pd_gps;
+
+extern void exynos4210_init_pm_domain(struct exynos4210_pm_domain
*exynos4210_pd);
+extern void exynos4210_add_device_to_domain(struct exynos4210_pm_domain
*exynos4210_pd,
+ struct platform_device *pdev);
+#else
+#define exynos4210_init_pm_domain(pd) do { } while(0)
+#define exynos4210_add_device_to_domain(pd, pdev) do { } while(0)
+#endif /* CONFIG_PM */
+
+#endif /* PM_EXYNOS4210_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h
b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index d493fdb..0d1c9ec 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -183,6 +183,14 @@
#define S5P_CLKDIV_BUS_GPLR_SHIFT (4)
#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 S5P_CLKDIV_BUS_GPLR_SHIFT)
+#define S5P_CLKGATE_BLOCK_CAM (1 0)
+#define S5P_CLKGATE_BLOCK_TV (1 1)
+#define S5P_CLKGATE_BLOCK_MFC (1 2)
+#define S5P_CLKGATE_BLOCK_G3D (1 3)
+#define S5P_CLKGATE_BLOCK_LCD0 (1 4)
+#define S5P_CLKGATE_BLOCK_LCD1 (1 5)
+#define S5P_CLKGATE_BLOCK_GPS (1 7)
+
/* Compatibility defines and inclusion */
#include mach/regs-pmu.h
diff --git a/arch/arm/mach-exynos4/pm-exynos4210.c
b/arch/arm/mach-exynos4/pm-exynos4210.c
new file mode 100644
index 000..d43c37f
--- /dev/null
+++ b/arch/arm/mach-exynos4/pm-exynos4210.c
@@ -0,0 +1,189 @@
+/* linux/arch/arm/mach-exynos4/pm-exynos4210.c
+ *
+ * Exynos4210 Power management support
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+
[PATCH 2/4] ARM: EXYNOS4: Support for generic Clock manipulation PM callbacks
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos4/Makefile |2 +-
arch/arm/mach-exynos4/pm-runtime.c | 56
2 files changed, 57 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-exynos4/pm-runtime.c
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 97c31ce..28cdb8b 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -5,7 +5,7 @@
#
# Licensed under GPLv2
-obj-y :=
+obj-y := pm-runtime.o
obj-m :=
obj-n :=
obj- :=
diff --git a/arch/arm/mach-exynos4/pm-runtime.c
b/arch/arm/mach-exynos4/pm-runtime.c
new file mode 100644
index 000..4fe9f73
--- /dev/null
+++ b/arch/arm/mach-exynos4/pm-runtime.c
@@ -0,0 +1,56 @@
+/* linux/arch/arm/mach-exynos4/pm-runtime.c
+
+ * Exynos4210 Power management support
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include linux/init.h
+#include linux/kernel.h
+#include linux/io.h
+#include linux/pm_runtime.h
+#include linux/platform_device.h
+#include linux/clk.h
+#include linux/bitmap.h
+#include linux/slab.h
+
+#ifdef CONFIG_PM_RUNTIME
+
+static int default_platform_runtime_idle(struct device *dev)
+{
+ return pm_runtime_suspend(dev);
+}
+
+static struct dev_pm_domain default_pm_domain = {
+ .ops = {
+ .runtime_suspend = pm_clk_suspend,
+ .runtime_resume = pm_clk_resume,
+ .runtime_idle = default_platform_runtime_idle,
+ USE_PLATFORM_PM_SLEEP_OPS
+ },
+};
+
+#define DEFAULT_PM_DOMAIN_PTR (default_pm_domain)
+
+#else
+
+#define DEFAULT_PM_DOMAIN_PTR NULL
+
+#endif /* CONFIG_PM_RUNTIME */
+
+static struct pm_clk_notifier_block platform_bus_notifier = {
+ .pm_domain = DEFAULT_PM_DOMAIN_PTR,
+ .con_ids = { NULL, },
+};
+
+static int __init exynos4_pm_runtime_init(void)
+{
+ pm_clk_add_notifier(platform_bus_type, platform_bus_notifier);
+ return 0;
+}
+core_initcall(exynos4_pm_runtime_init);
--
1.7.0.4
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[PATCH 3/4] ARM: EXYNOS4: Delete the power-domain code depend on Samsung SoC
This patch delete the power domain code depend on Samsung SoC
to use the generic Power domain framework for EXYNOS4210.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos4/Kconfig |9 --
arch/arm/mach-exynos4/Makefile |1 -
arch/arm/mach-exynos4/dev-pd.c | 139 ---
arch/arm/mach-exynos4/mach-nuri.c |3 -
arch/arm/mach-exynos4/mach-smdkc210.c |8 --
arch/arm/mach-exynos4/mach-smdkv310.c |8 --
arch/arm/mach-exynos4/mach-universal_c210.c |3 -
arch/arm/plat-samsung/Kconfig |8 --
arch/arm/plat-samsung/Makefile |4 -
arch/arm/plat-samsung/include/plat/pd.h | 30 --
arch/arm/plat-samsung/pd.c | 95 --
11 files changed, 0 insertions(+), 308 deletions(-)
delete mode 100644 arch/arm/mach-exynos4/dev-pd.c
delete mode 100644 arch/arm/plat-samsung/include/plat/pd.h
delete mode 100644 arch/arm/plat-samsung/pd.c
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index 8d5e876..66f1fad 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -32,11 +32,6 @@ config EXYNOS4_SETUP_FIMD0
help
Common setup code for FIMD0.
-config EXYNOS4_DEV_PD
- bool
- help
- Compile in platform device definitions for Power Domain
-
config EXYNOS4_DEV_SYSMMU
bool
help
@@ -125,7 +120,6 @@ config MACH_SMDKC210
select S3C_DEV_HSMMC3
select SAMSUNG_DEV_PWM
select SAMSUNG_DEV_BACKLIGHT
- select EXYNOS4_DEV_PD
select EXYNOS4_DEV_SYSMMU
select EXYNOS4_SETUP_FIMD0
select EXYNOS4_SETUP_I2C1
@@ -147,7 +141,6 @@ config MACH_SMDKV310
select SAMSUNG_DEV_BACKLIGHT
select EXYNOS4_DEV_AHCI
select SAMSUNG_DEV_KEYPAD
- select EXYNOS4_DEV_PD
select SAMSUNG_DEV_PWM
select EXYNOS4_DEV_SYSMMU
select EXYNOS4_SETUP_FIMD0
@@ -190,7 +183,6 @@ config MACH_UNIVERSAL_C210
select S3C_DEV_I2C5
select S5P_DEV_MFC
select S5P_DEV_ONENAND
- select EXYNOS4_DEV_PD
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C3
select EXYNOS4_SETUP_I2C5
@@ -211,7 +203,6 @@ config MACH_NURI
select S3C_DEV_I2C5
select S5P_DEV_MFC
select S5P_DEV_USB_EHCI
- select EXYNOS4_DEV_PD
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C3
select EXYNOS4_SETUP_I2C5
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 28cdb8b..99828b5 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -36,7 +36,6 @@ obj-$(CONFIG_MACH_NURI) += mach-nuri.o
obj-y += dev-audio.o
obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
-obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
obj-$(CONFIG_EXYNOS4_DEV_DWMCI)+= dev-dwmci.o
diff --git a/arch/arm/mach-exynos4/dev-pd.c b/arch/arm/mach-exynos4/dev-pd.c
deleted file mode 100644
index 3273f25..000
--- a/arch/arm/mach-exynos4/dev-pd.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/* linux/arch/arm/mach-exynos4/dev-pd.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS4 - Power Domain support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include linux/io.h
-#include linux/kernel.h
-#include linux/platform_device.h
-#include linux/delay.h
-
-#include mach/regs-pmu.h
-
-#include plat/pd.h
-
-static int exynos4_pd_enable(struct device *dev)
-{
- struct samsung_pd_info *pdata = dev-platform_data;
- u32 timeout;
-
- __raw_writel(S5P_INT_LOCAL_PWR_EN, pdata-base);
-
- /* Wait max 1ms */
- timeout = 10;
- while ((__raw_readl(pdata-base + 0x4) S5P_INT_LOCAL_PWR_EN)
- != S5P_INT_LOCAL_PWR_EN) {
- if (timeout == 0) {
- printk(KERN_ERR Power domain %s enable failed.\n,
- dev_name(dev));
- return -ETIMEDOUT;
- }
- timeout--;
- udelay(100);
- }
-
- return 0;
-}
-
-static int exynos4_pd_disable(struct device *dev)
-{
- struct samsung_pd_info *pdata = dev-platform_data;
- u32 timeout;
-
- __raw_writel(0, pdata-base);
-
- /* Wait max 1ms */
- timeout = 10;
- while (__raw_readl(pdata-base + 0x4) S5P_INT_LOCAL_PWR_EN) {
- if (timeout == 0) {
- printk(KERN_ERR Power domain %s disable failed.\n,
- dev_name(dev));
-
[PATCH 4/4] ARM: EXYNOS4: Add power domain to use generic Power domain Framework
This patch initializes the power domain of EXYNOS4210. The devices
which suppot runtime-PM have to be added in specific power domain.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos4/mach-nuri.c | 18 ++
arch/arm/mach-exynos4/mach-smdkc210.c | 18 ++
arch/arm/mach-exynos4/mach-smdkv310.c | 15 +++
arch/arm/mach-exynos4/mach-universal_c210.c | 18 ++
4 files changed, 69 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos4/mach-nuri.c
b/arch/arm/mach-exynos4/mach-nuri.c
index 4c358cb..5844c55 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -44,6 +44,7 @@
#include plat/mfc.h
#include mach/map.h
+#include mach/pm-exynos4210.h
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define NURI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL |\
@@ -1125,6 +1126,21 @@ static void __init nuri_reserve(void)
s5p_mfc_reserve_mem(0x4300, 8 20, 0x5100, 8 20);
}
+static void __init nuri_power_domain_init(void)
+{
+ /* Initialize Power domain */
+ exynos4210_init_pm_domain(exynos4210_pd_mfc);
+ exynos4210_init_pm_domain(exynos4210_pd_g3d);
+ exynos4210_init_pm_domain(exynos4210_pd_lcd0);
+ exynos4210_init_pm_domain(exynos4210_pd_lcd1);
+ exynos4210_init_pm_domain(exynos4210_pd_tv);
+ exynos4210_init_pm_domain(exynos4210_pd_cam);
+ exynos4210_init_pm_domain(exynos4210_pd_gps);
+
+ /* Add device to MFC power domain */
+ exynos4210_add_device_to_domain(exynos4210_pd_mfc, s5p_device_mfc);
+}
+
static void __init nuri_machine_init(void)
{
nuri_sdhci_init();
@@ -1145,6 +1161,8 @@ static void __init nuri_machine_init(void)
/* Last */
platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
+
+ nuri_power_domain_init();
}
MACHINE_START(NURI, NURI)
diff --git a/arch/arm/mach-exynos4/mach-smdkc210.c
b/arch/arm/mach-exynos4/mach-smdkc210.c
index 4d1976c..0a3b2a9 100644
--- a/arch/arm/mach-exynos4/mach-smdkc210.c
+++ b/arch/arm/mach-exynos4/mach-smdkc210.c
@@ -37,6 +37,7 @@
#include plat/backlight.h
#include mach/map.h
+#include mach/pm-exynos4210.h
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL |\
@@ -273,6 +274,21 @@ static void __init smdkc210_map_io(void)
s3c24xx_init_uarts(smdkc210_uartcfgs, ARRAY_SIZE(smdkc210_uartcfgs));
}
+static void __init smdkc210_power_domain_init(void)
+{
+ /* Initialize Power domain */
+ exynos4210_init_pm_domain(exynos4210_pd_mfc);
+ exynos4210_init_pm_domain(exynos4210_pd_g3d);
+ exynos4210_init_pm_domain(exynos4210_pd_lcd0);
+ exynos4210_init_pm_domain(exynos4210_pd_lcd1);
+ exynos4210_init_pm_domain(exynos4210_pd_tv);
+ exynos4210_init_pm_domain(exynos4210_pd_cam);
+ exynos4210_init_pm_domain(exynos4210_pd_gps);
+
+ /* Add device to LCD0 power domain */
+ exynos4210_add_device_to_domain(exynos4210_pd_lcd0, s5p_device_fimd0);
+}
+
static void __init smdkc210_machine_init(void)
{
s3c_i2c1_set_platdata(NULL);
@@ -289,6 +305,8 @@ static void __init smdkc210_machine_init(void)
s5p_fimd0_set_platdata(smdkc210_lcd0_pdata);
platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
+
+ smdkc210_power_domain_init();
}
MACHINE_START(SMDKC210, SMDKC210)
diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c
b/arch/arm/mach-exynos4/mach-smdkv310.c
index 8c2819b..320c7f3 100644
--- a/arch/arm/mach-exynos4/mach-smdkv310.c
+++ b/arch/arm/mach-exynos4/mach-smdkv310.c
@@ -33,6 +33,7 @@
#include plat/backlight.h
#include mach/map.h
+#include mach/pm-exynos4210.h
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL |\
@@ -225,6 +226,18 @@ static void __init smdkv310_map_io(void)
s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
}
+static void __init smdkv310_power_domain_init(void)
+{
+ /* Initialize Power domain */
+ exynos4210_init_pm_domain(exynos4210_pd_mfc);
+ exynos4210_init_pm_domain(exynos4210_pd_g3d);
+ exynos4210_init_pm_domain(exynos4210_pd_lcd0);
+ exynos4210_init_pm_domain(exynos4210_pd_lcd1);
+ exynos4210_init_pm_domain(exynos4210_pd_tv);
+ exynos4210_init_pm_domain(exynos4210_pd_cam);
+ exynos4210_init_pm_domain(exynos4210_pd_gps);
+}
+
static void __init smdkv310_machine_init(void)
{
s3c_i2c1_set_platdata(NULL);
@@ -242,6 +255,8 @@ static void __init smdkv310_machine_init(void)
samsung_bl_set(smdkv310_bl_gpio_info, smdkv310_bl_data);
platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
+
+
