[PATCH] ARM: EXYNOS: Make combiner_init function static

2012-07-06 Thread Sachin Kamat
Fixes the following warning:
arch/arm/mach-exynos/common.c:543:13:
warning: symbol 'combiner_init' was not declared. Should it be static?

Signed-off-by: Sachin Kamat 
---
 arch/arm/mach-exynos/common.c |3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 0ec1a91..66d71ba 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -540,7 +540,8 @@ static struct irq_domain_ops combiner_irq_domain_ops = {
.map= combiner_irq_domain_map,
 };
 
-void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
+static void __init combiner_init(void __iomem *combiner_base,
+   struct device_node *np)
 {
int i, irq, irq_base;
unsigned int max_nr, nr_irq;
-- 
1.7.4.1

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[PATCH 1/1] ARM: EXYNOS: Add missing static storage class specifier in pmu.c file

2012-07-06 Thread Sachin Kamat
arch/arm/mach-exynos/pmu.c:318:14: warning:
symbol 'exynos5_list_both_cnt_feed' was not declared. Should it be static?
arch/arm/mach-exynos/pmu.c:332:14: warning:
symbol 'exynos5_list_diable_wfi_wfe' was not declared. Should it be static?

Signed-off-by: Sachin Kamat 
---
 arch/arm/mach-exynos/pmu.c |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index bb4c522..3a48c85 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -315,7 +315,7 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = {
{ PMU_TABLE_END,},
 };
 
-void __iomem *exynos5_list_both_cnt_feed[] = {
+static void __iomem *exynos5_list_both_cnt_feed[] = {
EXYNOS5_ARM_CORE0_OPTION,
EXYNOS5_ARM_CORE1_OPTION,
EXYNOS5_ARM_COMMON_OPTION,
@@ -329,7 +329,7 @@ void __iomem *exynos5_list_both_cnt_feed[] = {
EXYNOS5_TOP_PWR_SYSMEM_OPTION,
 };
 
-void __iomem *exynos5_list_diable_wfi_wfe[] = {
+static void __iomem *exynos5_list_diable_wfi_wfe[] = {
EXYNOS5_ARM_CORE1_OPTION,
EXYNOS5_FSYS_ARM_OPTION,
EXYNOS5_ISP_ARM_OPTION,
-- 
1.7.4.1

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[PATCH 0/2] Add device tree and clock support for Gscaler.

2012-07-06 Thread Shaik Ameer Basha
This patch series adds clock support for Gscaler and device node
 entries for Gscaler on exynos5.

This patch is based Kukjin Kim's for-next branch.
 https://github.com/kgene/linux-samsung.git

Shaik Ameer Basha (2):
  ARM: EXYNOS5: Add clock support for Gscaler
  ARM: EXYNOS5: Add gscalar device from DT

 arch/arm/boot/dts/exynos5250.dtsi  |   31 
 arch/arm/mach-exynos/clock-exynos5.c   |   79 
 arch/arm/mach-exynos/mach-exynos5-dt.c |8 +++
 3 files changed, 118 insertions(+), 0 deletions(-)

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[PATCH 1/2] ARM: EXYNOS5: Add clock support for Gscaler

2012-07-06 Thread Shaik Ameer Basha
Add required clock support for Gscaler for exynos5

Signed-off-by: Abhilash Kesavan 
Signed-off-by: Leela Krishna Amudala 
Signed-off-by: Prathyush K 
Signed-off-by: Shaik Ameer Basha 
---
 arch/arm/mach-exynos/clock-exynos5.c |   79 ++
 1 files changed, 79 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/clock-exynos5.c 
b/arch/arm/mach-exynos/clock-exynos5.c
index fefa336..49f98cd 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -741,6 +741,26 @@ static struct clk exynos5_init_clocks_off[] = {
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit= (1 << 14),
}, {
+   .name   = "gscl",
+   .devname= "exynos-gsc.0",
+   .enable = exynos5_clk_ip_gscl_ctrl,
+   .ctrlbit= (1 << 0),
+   }, {
+   .name   = "gscl",
+   .devname= "exynos-gsc.1",
+   .enable = exynos5_clk_ip_gscl_ctrl,
+   .ctrlbit= (1 << 1),
+   }, {
+   .name   = "gscl",
+   .devname= "exynos-gsc.2",
+   .enable = exynos5_clk_ip_gscl_ctrl,
+   .ctrlbit= (1 << 2),
+   }, {
+   .name   = "gscl",
+   .devname= "exynos-gsc.3",
+   .enable = exynos5_clk_ip_gscl_ctrl,
+   .ctrlbit= (1 << 3),
+   }, {
.name   = SYSMMU_CLOCK_NAME,
.devname= SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
.enable = &exynos5_clk_ip_mfc_ctrl,
@@ -1116,6 +1136,61 @@ static struct clksrc_clk exynos5_clksrcs[] = {
},
 };
 
+/* For ACLK_300_gscl_mid */
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
+   .clk= {
+   .name   = "mout_aclk_300_gscl_mid",
+   },
+   .sources = &exynos5_clkset_aclk,
+   .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
+};
+
+/* For ACLK_300_gscl */
+struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
+   [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
+   [1] = &exynos5_clk_sclk_vpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
+   .sources= exynos5_clkset_aclk_300_gscl_list,
+   .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
+   .clk= {
+   .name   = "mout_aclk_300_gscl",
+   },
+   .sources = &exynos5_clkset_aclk_300_gscl,
+   .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_aclk_300_gscl = {
+   .clk= {
+   .name   = "dout_aclk_300_gscl",
+   .parent = &exynos5_clk_mout_aclk_300_gscl.clk,
+   },
+   .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 12, .size = 3 },
+};
+
+/* Possible clock sources for aclk_300_gscl_sub Mux */
+static struct clk *clk_src_gscl_300_list[] = {
+   [0] = &clk_ext_xtal_mux,
+   [1] = &exynos5_clk_dout_aclk_300_gscl.clk,
+};
+
+static struct clksrc_sources clk_src_gscl_300 = {
+   .sources= clk_src_gscl_300_list,
+   .nr_sources = ARRAY_SIZE(clk_src_gscl_300_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
+   .clk= {
+   .name   = "aclk_300_gscl",
+   },
+   .sources = &clk_src_gscl_300,
+   .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
+};
+
 /* Clock initialization code */
 static struct clksrc_clk *exynos5_sysclks[] = {
&exynos5_clk_mout_apll,
@@ -1139,6 +1214,10 @@ static struct clksrc_clk *exynos5_sysclks[] = {
&exynos5_clk_aclk_266,
&exynos5_clk_aclk_200,
&exynos5_clk_aclk_166,
+   &exynos5_clk_mout_aclk_300_gscl_mid,
+   &exynos5_clk_mout_aclk_300_gscl,
+   &exynos5_clk_dout_aclk_300_gscl,
+   &exynos5_clk_aclk_300_gscl,
&exynos5_clk_aclk_66_pre,
&exynos5_clk_aclk_66,
&exynos5_clk_dout_mmc0,
-- 
1.7.0.4

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[PATCH 2/2] ARM: EXYNOS5: Add gscalar device from DT

2012-07-06 Thread Shaik Ameer Basha
Adding all 4 gscalar devices from DT device list in machine file.

Signed-off-by: Abhilash Kesavan 
Signed-off-by: Leela Krishna Amudala 
Signed-off-by: Shaik Ameer Basha 
---
 arch/arm/boot/dts/exynos5250.dtsi  |   31 +++
 arch/arm/mach-exynos/mach-exynos5-dt.c |8 
 2 files changed, 39 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 4272b29..b945c00 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -23,6 +23,13 @@
compatible = "samsung,exynos5250";
interrupt-parent = <&gic>;
 
+   aliases {
+   gsc0 = &gsc_0;
+   gsc1 = &gsc_1;
+   gsc2 = &gsc_2;
+   gsc3 = &gsc_3;
+   };
+
gic:interrupt-controller@10481000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
@@ -424,4 +431,28 @@
#gpio-cells = <4>;
};
};
+
+   gsc_0:  gsc@0x13e0 {
+   compatible = "samsung,exynos-gsc";
+   reg = <0x13e0 0x1000>;
+   interrupts = <0 85 0>;
+   };
+
+   gsc_1:  gsc@0x13e1 {
+   compatible = "samsung,exynos-gsc";
+   reg = <0x13e1 0x1000>;
+   interrupts = <0 86 0>;
+   };
+
+   gsc_2:  gsc@0x13e2 {
+   compatible = "samsung,exynos-gsc";
+   reg = <0x13e2 0x1000>;
+   interrupts = <0 87 0>;
+   };
+
+   gsc_3:  gsc@0x13e3 {
+   compatible = "samsung,exynos-gsc";
+   reg = <0x13e3 0x1000>;
+   interrupts = <0 88 0>;
+   };
 };
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c 
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 7b1e11a..76b081c 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -50,6 +50,14 @@ static const struct of_dev_auxdata 
exynos5250_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
+   OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E0,
+   "exynos-gsc.0", NULL),
+   OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E1,
+   "exynos-gsc.1", NULL),
+   OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E2,
+   "exynos-gsc.2", NULL),
+   OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E3,
+   "exynos-gsc.3", NULL),
{},
 };
 
-- 
1.7.0.4

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Re: [PATCH 1/2] ARM: EXYNOS5: Add clock support for Gscaler

2012-07-06 Thread Sachin Kamat
Hi Shaik,

Some nits:

Patch subject: s/EXYNOS5/EXYNOS

On 6 July 2012 18:15, Shaik Ameer Basha  wrote:
> Add required clock support for Gscaler for exynos5
>
> Signed-off-by: Abhilash Kesavan 
> Signed-off-by: Leela Krishna Amudala 
> Signed-off-by: Prathyush K 
> Signed-off-by: Shaik Ameer Basha 
> ---
>  arch/arm/mach-exynos/clock-exynos5.c |   79 
> ++
>  1 files changed, 79 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/clock-exynos5.c 
> b/arch/arm/mach-exynos/clock-exynos5.c
> index fefa336..49f98cd 100644
> --- a/arch/arm/mach-exynos/clock-exynos5.c
> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> @@ -741,6 +741,26 @@ static struct clk exynos5_init_clocks_off[] = {
> .enable = exynos5_clk_ip_peric_ctrl,
> .ctrlbit= (1 << 14),
> }, {
> +   .name   = "gscl",
> +   .devname= "exynos-gsc.0",
> +   .enable = exynos5_clk_ip_gscl_ctrl,
> +   .ctrlbit= (1 << 0),
> +   }, {
> +   .name   = "gscl",
> +   .devname= "exynos-gsc.1",
> +   .enable = exynos5_clk_ip_gscl_ctrl,
> +   .ctrlbit= (1 << 1),
> +   }, {
> +   .name   = "gscl",
> +   .devname= "exynos-gsc.2",
> +   .enable = exynos5_clk_ip_gscl_ctrl,
> +   .ctrlbit= (1 << 2),
> +   }, {
> +   .name   = "gscl",
> +   .devname= "exynos-gsc.3",
> +   .enable = exynos5_clk_ip_gscl_ctrl,
> +   .ctrlbit= (1 << 3),
> +   }, {
> .name   = SYSMMU_CLOCK_NAME,
> .devname= SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
> .enable = &exynos5_clk_ip_mfc_ctrl,
> @@ -1116,6 +1136,61 @@ static struct clksrc_clk exynos5_clksrcs[] = {
> },
>  };
>
> +/* For ACLK_300_gscl_mid */
> +static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
> +   .clk= {
> +   .name   = "mout_aclk_300_gscl_mid",
> +   },
> +   .sources = &exynos5_clkset_aclk,
> +   .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
> +};
> +
> +/* For ACLK_300_gscl */
> +struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
> +   [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
> +   [1] = &exynos5_clk_sclk_vpll.clk,
> +};
> +
> +struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
> +   .sources= exynos5_clkset_aclk_300_gscl_list,
> +   .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
> +};
> +
> +static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
> +   .clk= {
> +   .name   = "mout_aclk_300_gscl",
> +   },
> +   .sources = &exynos5_clkset_aclk_300_gscl,
> +   .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
> +};
> +
> +static struct clksrc_clk exynos5_clk_dout_aclk_300_gscl = {
> +   .clk= {
> +   .name   = "dout_aclk_300_gscl",
> +   .parent = &exynos5_clk_mout_aclk_300_gscl.clk,
> +   },
> +   .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 12, .size = 3 },
> +};
> +
> +/* Possible clock sources for aclk_300_gscl_sub Mux */
> +static struct clk *clk_src_gscl_300_list[] = {
> +   [0] = &clk_ext_xtal_mux,
> +   [1] = &exynos5_clk_dout_aclk_300_gscl.clk,
> +};
> +
> +static struct clksrc_sources clk_src_gscl_300 = {
> +   .sources= clk_src_gscl_300_list,
> +   .nr_sources = ARRAY_SIZE(clk_src_gscl_300_list),
> +};
> +
> +static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
> +   .clk= {
> +   .name   = "aclk_300_gscl",
> +   },
> +   .sources = &clk_src_gscl_300,
> +   .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
> +};
> +
>  /* Clock initialization code */
>  static struct clksrc_clk *exynos5_sysclks[] = {
> &exynos5_clk_mout_apll,
> @@ -1139,6 +1214,10 @@ static struct clksrc_clk *exynos5_sysclks[] = {
> &exynos5_clk_aclk_266,
> &exynos5_clk_aclk_200,
> &exynos5_clk_aclk_166,
> +   &exynos5_clk_mout_aclk_300_gscl_mid,
> +   &exynos5_clk_mout_aclk_300_gscl,
> +   &exynos5_clk_dout_aclk_300_gscl,
> +   &exynos5_clk_aclk_300_gscl,
> &exynos5_clk_aclk_66_pre,
> &exynos5_clk_aclk_66,
> &exynos5_clk_dout_mmc0,

Please maintain the alphabetic order.

> --
> 1.7.0.4
>
> --
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-- 
With warm regards,
Sachin
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Mor

Re: [PATCH 2/2] ARM: EXYNOS5: Add gscalar device from DT

2012-07-06 Thread Sylwester Nawrocki

Hi Shaik,

On 07/06/2012 02:45 PM, Shaik Ameer Basha wrote:

Adding all 4 gscalar devices from DT device list in machine file.


nit: s/gscalar/gscaler

The above sentence doesn't quite parse though.


Signed-off-by: Abhilash Kesavan
Signed-off-by: Leela Krishna Amudala
Signed-off-by: Shaik Ameer Basha
---
  arch/arm/boot/dts/exynos5250.dtsi  |   31 +++
  arch/arm/mach-exynos/mach-exynos5-dt.c |8 
  2 files changed, 39 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 4272b29..b945c00 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -23,6 +23,13 @@
compatible = "samsung,exynos5250";
interrupt-parent =<&gic>;

+   aliases {
+   gsc0 =&gsc_0;
+   gsc1 =&gsc_1;
+   gsc2 =&gsc_2;
+   gsc3 =&gsc_3;
+   };
+


What are these aliases useful for ?
Also I think all DT related patches should be posted to
devicetree-disc...@lists.ozlabs.org as well.


gic:interrupt-controller@10481000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells =<3>;
@@ -424,4 +431,28 @@
#gpio-cells =<4>;
};
};
+
+   gsc_0:  gsc@0x13e0 {
+   compatible = "samsung,exynos-gsc";
+   reg =<0x13e0 0x1000>;
+   interrupts =<0 85 0>;
+   };
+
+   gsc_1:  gsc@0x13e1 {
+   compatible = "samsung,exynos-gsc";
+   reg =<0x13e1 0x1000>;
+   interrupts =<0 86 0>;
+   };
+
+   gsc_2:  gsc@0x13e2 {
+   compatible = "samsung,exynos-gsc";
+   reg =<0x13e2 0x1000>;
+   interrupts =<0 87 0>;
+   };
+
+   gsc_3:  gsc@0x13e3 {
+   compatible = "samsung,exynos-gsc";
+   reg =<0x13e3 0x1000>;
+   interrupts =<0 88 0>;
+   };
  };
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c 
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 7b1e11a..76b081c 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -50,6 +50,14 @@ static const struct of_dev_auxdata 
exynos5250_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
+   OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E0,
+   "exynos-gsc.0", NULL),
+   OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E1,
+   "exynos-gsc.1", NULL),
+   OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E2,
+   "exynos-gsc.2", NULL),
+   OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E3,
+   "exynos-gsc.3", NULL),


It's probably better to add relevant entry at 
arch/arm/mach-exynos/include/mach/map. It's just a one line, e.g.


/* x = 0...3 */
#define EXYNOS5_PA_GSC(x)   (0x13e0 + ((x) * 0x1))

And use it here instead of plain numbers.

--
Thanks,
Sylwester
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Re: [PATCH 2/2] ARM: EXYNOS5: Add gscalar device from DT

2012-07-06 Thread Sachin Kamat
Hi Shaik,


On 6 July 2012 18:15, Shaik Ameer Basha  wrote:
> Adding all 4 gscalar devices from DT device list in machine file.
>
> Signed-off-by: Abhilash Kesavan 
> Signed-off-by: Leela Krishna Amudala 
> Signed-off-by: Shaik Ameer Basha 
> ---
>  arch/arm/boot/dts/exynos5250.dtsi  |   31 +++
>  arch/arm/mach-exynos/mach-exynos5-dt.c |8 
>  2 files changed, 39 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
> b/arch/arm/boot/dts/exynos5250.dtsi
> index 4272b29..b945c00 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -23,6 +23,13 @@
> compatible = "samsung,exynos5250";
> interrupt-parent = <&gic>;
>
> +   aliases {
> +   gsc0 = &gsc_0;
> +   gsc1 = &gsc_1;
> +   gsc2 = &gsc_2;
> +   gsc3 = &gsc_3;
> +   };
> +
> gic:interrupt-controller@10481000 {
> compatible = "arm,cortex-a9-gic";
> #interrupt-cells = <3>;
> @@ -424,4 +431,28 @@
> #gpio-cells = <4>;
> };
> };
> +
> +   gsc_0:  gsc@0x13e0 {
> +   compatible = "samsung,exynos-gsc";
> +   reg = <0x13e0 0x1000>;
> +   interrupts = <0 85 0>;
> +   };
> +
> +   gsc_1:  gsc@0x13e1 {
> +   compatible = "samsung,exynos-gsc";
> +   reg = <0x13e1 0x1000>;
> +   interrupts = <0 86 0>;
> +   };
> +
> +   gsc_2:  gsc@0x13e2 {
> +   compatible = "samsung,exynos-gsc";
> +   reg = <0x13e2 0x1000>;
> +   interrupts = <0 87 0>;
> +   };
> +
> +   gsc_3:  gsc@0x13e3 {
> +   compatible = "samsung,exynos-gsc";
> +   reg = <0x13e3 0x1000>;
> +   interrupts = <0 88 0>;
> +   };
>  };


Please also update the documentaion for these bindings.


> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c 
> b/arch/arm/mach-exynos/mach-exynos5-dt.c
> index 7b1e11a..76b081c 100644
> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> @@ -50,6 +50,14 @@ static const struct of_dev_auxdata 
> exynos5250_auxdata_lookup[] __initconst = {
> OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
> OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
> OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
> +   OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E0,
> +   "exynos-gsc.0", NULL),
> +   OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E1,
> +   "exynos-gsc.1", NULL),
> +   OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E2,
> +   "exynos-gsc.2", NULL),
> +   OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E3,
> +   "exynos-gsc.3", NULL),
> {},
>  };
>
> --
> 1.7.0.4
>
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-- 
With warm regards,
Sachin
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