[PATCH] ARM: SAMSUNG: Fix HDMI related warnings
Silences the following warnings: arch/arm/plat-samsung/devs.c:765:31: warning: symbol 's5p_hdmi_def_platdata' was not declared. Should it be static? arch/arm/plat-samsung/devs.c:767:13: warning: symbol 's5p_hdmi_set_platdata' was not declared. Should it be static? Signed-off-by: Sachin Kamat sachin.ka...@linaro.org --- arch/arm/plat-samsung/devs.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 6ff45d5..565cea7 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c @@ -51,6 +51,7 @@ #include plat/ehci.h #include plat/fb.h #include plat/fb-s3c2410.h +#include plat/hdmi.h #include plat/hwmon.h #include plat/iic.h #include plat/keypad.h @@ -762,7 +763,7 @@ void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd) s5p_device_i2c_hdmiphy); } -struct s5p_hdmi_platform_data s5p_hdmi_def_platdata; +static struct s5p_hdmi_platform_data s5p_hdmi_def_platdata; void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info, struct i2c_board_info *mhl_info, int mhl_bus) -- 1.7.4.1 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v4 9/9] mmc: dw_mmc: add support for exynos specific implementation of dw-mshc
Hi Thomas,
Thank you for your effort.
Some reviews seems like to be omitted. Please check more.
On Sunday, August 26, 2012 Thomas Abraham thomas.abra...@linaro.org wrote:
Samsung Exynos SoC's extend the dw-mshc controller for additional clock and
bus
control. Add support for these extensions and include provide device tree
based
discovery suppory as well.
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
.../devicetree/bindings/mmc/exynos-dw-mshc.txt | 79 +++
drivers/mmc/host/Kconfig |9 +
drivers/mmc/host/Makefile |3 +-
drivers/mmc/host/dw_mmc-exynos.c | 247
4 files changed, 337 insertions(+), 1 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
create mode 100644 drivers/mmc/host/dw_mmc-exynos.c
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
new file mode 100644
index 000..a7a6039
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -0,0 +1,79 @@
+* Samsung Exynos specific extensions to the Synopsis Designware Mobile
+ Storage Host Controller
+
+The Synopsis designware mobile storage host controller is used to interface
+a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
+differences between the core Synopsis dw mshc controller properties described
+by synposis-dw-mshc.txt and the properties used by the Samsung Exynos
specific
+extensions to the Synopsis Designware Mobile Storage Host Controller.
+
+Required Properties:
+
+* compatible: should be
+ - samsung,exynos4210-dw-mshc: for controllers with Samsung Exynos4210
+ specific extentions.
+ - samsung,exynos4412-dw-mshc: for controllers with Samsung Exynos4412
+ specific extentions.
+ - samsung,exynos5250-dw-mshc: for controllers with Samsung Exynos5250
+ specific extentions.
+
+Optional Controller Properties:
+
+* samsung,dw-mshc-sdr-timing: Specifies the value of CUI clock divider, CIU
+ clock phase shift value in transmit mode and CIU clock phase shift value in
+ receive mode for single data rate mode operation. Refer notes of the valid
+ values below.
+
+* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock divider, CIU
+ clock phase shift value in transmit mode and CIU clock phase shift value in
+ receive mode for double data rate mode operation. Refer notes of the valid
+ values below. The order of the cells should be
+
+- First Cell:CIU clock divider value (applicable only for Exynos5
+ SoC's, should be zero for Exynos4 SoC's)
+- Second Cell: CIU clock phase shift value for tx mode.
+- Third Cell:CIU clock phase shift value for rx mode.
+
+ Valid values for SDR and DDR CIU clock timing for Exynos5250:
+
+- valid values for CIU clock divider, tx phase shift and rx phase shift
+ is 0 to 7.
+
+- When CIU clock divider value is set to 3, all possible 8 phase shift
+ values can be used.
+
+- If CIU clock divider value is 0 (that is divide by 1), both tx and rx
+ phase shift clocks should be 0.
+
+Example:
+
+ The MSHC controller node can be split into two portions, SoC specific and
+ board specific portions as listed below.
+
+ dwmmc0@1220 {
+ compatible = samsung,exynos5250-dw-mshc;
+ reg = 0x1220 0x1000;
+ interrupts = 0 75 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
+ dwmmc0@1220 {
+ num-slots = 1;
+ supports-highspeed;
+ broken-cd;
+ fifo-depth = 0x80;
+ card-detect-delay = 200;
+ samsung,dw-mshc-sdr-timing = 2 3 3;
+ samsung,dw-mshc-ddr-timing = 1 2 3;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ gpios = gpc0 0 2 0 3, gpc0 1 2 0 3,
+ gpc1 0 2 3 3, gpc1 1 2 3 3,
+ gpc1 2 2 3 3, gpc1 3 2 3 3,
+ gpc0 3 2 3 3, gpc0 4 2 3 3,
+ gpc0 5 2 3 3, gpc0 6 2 3 3;
+ };
+ };
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index aa131b3..70eec88 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -540,6 +540,15 @@ config MMC_DW_PLTFM
If unsure, say Y.
+config MMC_DW_EXYNOS
+ bool Exynos specific extentions for Synopsys DW Memory Card Interface
+ depends on MMC_DW
+ select MMC_DW_PLTFM
+ help
+ This selects support for Samsung Exynos SoC specific extensions to the
+ Synopsys DesignWare Memory Card Interface driver. Select this option
+ for platforms based on Exynos4 and Exynos5
Re: [PATCH v4 9/9] mmc: dw_mmc: add support for exynos specific implementation of dw-mshc
Hi Seungwon,
On 28 August 2012 12:36, Seungwon Jeon tgih@samsung.com wrote:
Hi Thomas,
Thank you for your effort.
Some reviews seems like to be omitted. Please check more.
On Sunday, August 26, 2012 Thomas Abraham thomas.abra...@linaro.org wrote:
Samsung Exynos SoC's extend the dw-mshc controller for additional clock and
bus
control. Add support for these extensions and include provide device tree
based
discovery suppory as well.
[...]
+static struct dw_mci_exynos_compatible {
+ char*compatible;
+ enum dw_mci_exynos_type ctrl_type;
+} exynos_compat[] = {
+ {
+ .compatible = samsung,exynos4210-dw-mshc,
+ .ctrl_type = DW_MCI_TYPE_EXYNOS4210,
+ }, {
+ .compatible = samsung,exynos4210-dw-mshc,
typo? exynos4412-dw-mshc is expected.
Yes, that was a typo. I will fix it.
[...]
+static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
+{
+ struct dw_mci_exynos_priv_data *priv = host-priv;
+ u8 drv;
+
+ /*
+ * Exynos4412 and Exynos5250 extends the use of CMD register with the
+ * use of bit 29 (which is reserved on standard MSHC controllers) for
+ * optionally bypassing the HOLD register for command and data. The
+ * HOLD register should be bypassed in case there is no phase shift
+ * applied on CMD/DATA that is sent to the card.
+ */
+ if (priv-ctrl_type == DW_MCI_TYPE_EXYNOS4412)
+ drv = SDMMC_CLKSEL_GET_DRV_WD2(mci_readl(host, CLKSEL));
As it has been mentioned previously, only exynos4210 uses 2-bit.
So SDMMC_CLKSEL_GET_DRV_WD3 will be right in exynos4412.
In the Exynos4412 user manual that I referred, the SelClk_Drv and
SelClk_Sample bit fields of the CLKSEL register are 2 bits wide. Could
you please confirm that these two bit-fields are infact 3 bits wide?
+ else if (priv-ctrl_type == DW_MCI_TYPE_EXYNOS5250)
+ drv = SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL));
+ else
+ return;
+ if (drv)
+ *cmdr |= SDMMC_CMD_USE_HOLD_REG;
+}
+
+static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
+{
+ struct dw_mci_exynos_priv_data *priv = host-priv;
+
+ if (ios-timing == MMC_TIMING_UHS_DDR50)
+ mci_writel(host, CLKSEL, priv-ddr_timing);
+ else
+ mci_writel(host, CLKSEL, priv-sdr_timing);
+
+ host-bus_hz = clk_get_rate(host-ciu_clk);
+ if (priv-ctrl_type == DW_MCI_TYPE_EXYNOS5250)
+ host-bus_hz /= SDMMC_CLKSEL_GET_DIVRATIO(
+ mci_readl(host, CLKSEL));
bus_hz should be recalculated for exynoxs4 as well.
Could you check the previous mailing?
Exynos4 does not have the additional clock divisor, as in Exynos5250.
Could you please explain why the bus_hz clock should be divided in
Exynos4?
+}
+
+static int dw_mci_exynos_parse_dt(struct dw_mci *host)
+{
+ struct dw_mci_exynos_priv_data *priv = host-priv;
+ u32 timing[3];
+
+ if (of_property_read_u32_array(host-dev-of_node,
+ samsung,dw-mshc-sdr-timing, timing, 3))
+ priv-sdr_timing = DW_MCI_DEF_SDR_TIMING;
+ else
+ priv-sdr_timing = SDMMC_CLKSEL_TIMING(timing[0],
+ timing[1], timing[2]);
+
+ if (of_property_read_u32_array(host-dev-of_node,
+ samsung,dw-mshc-ddr-timing, timing, 3))
+ priv-ddr_timing = DW_MCI_DEF_DDR_TIMING;
+ else
+ priv-ddr_timing = SDMMC_CLKSEL_TIMING(timing[0],
+ timing[1], timing[2]);
+ return 0;
DW_MCI_DEF_SDR_TIMING and DW_MCI_DEF_DDR_TIMING are board-specific timing
values.
So, these values can't be used commonly. It has been already discussed.
If this property is empty, returning error with message will be fine.
Currently just 0 is always returned.
Yes, you had mentioned this previously. But these are only default
values. In case, a board cannot work with these default values, the
board's dtsi file should provide the correct values by using these
bindings. What is your opinion on this, please let me know.
Thanks for your time reviewing this patch series.
Regards,
Thomas.
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[PATCH] ARM: EXYNOS: Fix incorrect help text
Changed Exynos4 - Exynos5. Signed-off-by: Sachin Kamat sachin.ka...@linaro.org --- arch/arm/mach-exynos/Kconfig |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index b5b4c8c..9369ff7 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -418,8 +418,8 @@ config MACH_EXYNOS5_DT select USE_OF select ARM_AMBA help - Machine support for Samsung Exynos4 machine with device tree enabled. - Select this if a fdt blob is available for the EXYNOS4 SoC based board. + Machine support for Samsung Exynos5 machine with device tree enabled. + Select this if a fdt blob is available for the EXYNOS5 SoC based board. if ARCH_EXYNOS4 -- 1.7.4.1 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: Exynos4: Turn off clocks for NAND, OneNAND and TSI controllers
On 24 August 2012 20:22, Chander Kashyap chander.kash...@linaro.org wrote:
The clocks for NAND, OneNAND and Transport Stream Interface(TSI)
controllers could be either enabled or disabled at boot. To ensure
that these are turned off until used, add them to the list of clocks
to be turned off during boot.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
---
arch/arm/mach-exynos/clock-exynos4.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mach-exynos/clock-exynos4.c
b/arch/arm/mach-exynos/clock-exynos4.c
index 2f51293..7cc5491 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -501,6 +501,10 @@ static struct clk exynos4_init_clocks_off[] = {
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit= (1 3),
}, {
+ .name = tsi,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit= (1 4),
+ }, {
.name = hsmmc,
.devname= exynos4-sdhci.0,
.parent = exynos4_clk_aclk_133.clk,
@@ -530,6 +534,14 @@ static struct clk exynos4_init_clocks_off[] = {
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit= (1 9),
}, {
+ .name = onenand,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit= (1 15),
+ }, {
+ .name = nfcon,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit= (1 16),
+ }, {
.name = dac,
.devname= s5p-sdo,
.enable = exynos4_clk_ip_tv_ctrl,
--
1.7.9.5
Reviewed-by: Thomas Abraham thomas.abra...@linaro.org
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[RESUBMIT PATCH] ASoC: SAMSUNG: Change Kconfig to support all SAMSUNG ASoC
All SAMSUNG ASoC needs SND_SOC_SAMSUNG configuration. This patch change Kconfig to support all SAMSUNG ASoC. Signed-off-by: Sangsu Park sangsu4u.p...@samsung.com --- sound/soc/samsung/Kconfig |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig index f17dd25..e7b8317 100644 --- a/sound/soc/samsung/Kconfig +++ b/sound/soc/samsung/Kconfig @@ -1,6 +1,6 @@ config SND_SOC_SAMSUNG tristate ASoC support for Samsung - depends on ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5P64X0 || ARCH_EXYNOS4 + depends on PLAT_SAMSUNG select S3C64XX_DMA if ARCH_S3C64XX select S3C2410_DMA if ARCH_S3C24XX help -- 1.7.1 On 08/28/12 8:00, Kukjin Kim wrote: On 08/27/12 11:08, Mark Brown wrote: On Mon, Aug 27, 2012 at 11:06:47AM -0700, Kukjin Kim wrote: Hmm, all of Samsung stuff is available...so how about? + depends on PLAT_SAMSUNG Yes, that's a very good idea! Mark, thanks. Sangsu, could you please re-submit as per my suggestion? Thanks. Kukjin, thanks. This is re-submit patch. In fact, I'd wanted to submit your idea :) Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] ARM: EXYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx
The GPEx gpios are specific to Exynos4210 and do not exist on Exynos4x12.
Redefine them to use the exact SoC name.
Based on ARM: EXYYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx by
Joonyoung Shim, see:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/100738.html
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mach-exynos/include/mach/gpio.h | 32 +++---
arch/arm/mach-exynos/mach-nuri.c | 16 +++
arch/arm/mach-exynos/mach-origen.c | 6 +++---
arch/arm/mach-exynos/mach-trats.c | 4 ++--
arch/arm/mach-exynos/mach-universal_c210.c | 32 +++---
arch/arm/mach-exynos/setup-fimc.c | 4 ++--
drivers/gpio/gpio-samsung.c| 20 +--
7 files changed, 57 insertions(+), 57 deletions(-)
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h
b/arch/arm/mach-exynos/include/mach/gpio.h
index eb24f1e..21c9bf1 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -26,11 +26,11 @@
#define EXYNOS4_GPIO_C1_NR (5)
#define EXYNOS4_GPIO_D0_NR (4)
#define EXYNOS4_GPIO_D1_NR (4)
-#define EXYNOS4_GPIO_E0_NR (5)
-#define EXYNOS4_GPIO_E1_NR (8)
-#define EXYNOS4_GPIO_E2_NR (6)
-#define EXYNOS4_GPIO_E3_NR (8)
-#define EXYNOS4_GPIO_E4_NR (8)
+#define EXYNOS4210_GPIO_E0_NR (5)
+#define EXYNOS4210_GPIO_E1_NR (8)
+#define EXYNOS4210_GPIO_E2_NR (6)
+#define EXYNOS4210_GPIO_E3_NR (8)
+#define EXYNOS4210_GPIO_E4_NR (8)
#define EXYNOS4_GPIO_F0_NR (8)
#define EXYNOS4_GPIO_F1_NR (8)
#define EXYNOS4_GPIO_F2_NR (8)
@@ -67,12 +67,12 @@ enum exynos4_gpio_number {
EXYNOS4_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0),
EXYNOS4_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1),
EXYNOS4_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),
- EXYNOS4_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
- EXYNOS4_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E0),
- EXYNOS4_GPIO_E2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E1),
- EXYNOS4_GPIO_E3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E2),
- EXYNOS4_GPIO_E4_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E3),
- EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E4),
+ EXYNOS4210_GPIO_E0_START= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
+ EXYNOS4210_GPIO_E1_START= EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E0),
+ EXYNOS4210_GPIO_E2_START= EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E1),
+ EXYNOS4210_GPIO_E3_START= EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E2),
+ EXYNOS4210_GPIO_E4_START= EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E3),
+ EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E4),
EXYNOS4_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0),
EXYNOS4_GPIO_F2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1),
EXYNOS4_GPIO_F3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
@@ -108,11 +108,11 @@ enum exynos4_gpio_number {
#define EXYNOS4_GPC1(_nr) (EXYNOS4_GPIO_C1_START + (_nr))
#define EXYNOS4_GPD0(_nr) (EXYNOS4_GPIO_D0_START + (_nr))
#define EXYNOS4_GPD1(_nr) (EXYNOS4_GPIO_D1_START + (_nr))
-#define EXYNOS4_GPE0(_nr) (EXYNOS4_GPIO_E0_START + (_nr))
-#define EXYNOS4_GPE1(_nr) (EXYNOS4_GPIO_E1_START + (_nr))
-#define EXYNOS4_GPE2(_nr) (EXYNOS4_GPIO_E2_START + (_nr))
-#define EXYNOS4_GPE3(_nr) (EXYNOS4_GPIO_E3_START + (_nr))
-#define EXYNOS4_GPE4(_nr) (EXYNOS4_GPIO_E4_START + (_nr))
+#define EXYNOS4210_GPE0(_nr) (EXYNOS4210_GPIO_E0_START + (_nr))
+#define EXYNOS4210_GPE1(_nr) (EXYNOS4210_GPIO_E1_START + (_nr))
+#define EXYNOS4210_GPE2(_nr) (EXYNOS4210_GPIO_E2_START + (_nr))
+#define EXYNOS4210_GPE3(_nr) (EXYNOS4210_GPIO_E3_START + (_nr))
+#define EXYNOS4210_GPE4(_nr) (EXYNOS4210_GPIO_E4_START + (_nr))
#define EXYNOS4_GPF0(_nr) (EXYNOS4_GPIO_F0_START + (_nr))
#define EXYNOS4_GPF1(_nr) (EXYNOS4_GPIO_F1_START + (_nr))
#define EXYNOS4_GPF2(_nr) (EXYNOS4_GPIO_F2_START + (_nr))
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index ea785fc..426bb79 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -268,7 +268,7 @@ static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
{
- int gpio = EXYNOS4_GPE1(5);
+ int gpio = EXYNOS4210_GPE1(5);
gpio_request(gpio, LVDS_nSHDN);
gpio_direction_output(gpio, power);
@@ -277,7 +277,7 @@ static void nuri_lcd_power_on(struct plat_lcd_data *pd,
unsigned int power)
static int nuri_bl_init(struct device *dev)
{
- return gpio_request_one(EXYNOS4_GPE2(3), GPIOF_OUT_INIT_LOW,
+ return gpio_request_one(EXYNOS4210_GPE2(3), GPIOF_OUT_INIT_LOW,
LCD_LD0_EN);
}
@@ -286,14 +286,14 @@ static int nuri_bl_notify(struct
[PATCH 2/3] gpio: samsung: Add support for Exynos4x12 SoCs
Based on patch gpio/exynos: Add support for Exynos4x12 SoC by Joonyoung Shim.
See: http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/100737.html
Exynos4x12 GPIO part1 and part2 have different layout than Exynos4210,
so the initialization code has to be modified to support Exynos4x12 SoC.
GPVx Exynos4x12 GPIO part4 is not supported yet.
In the Exynos4x12 GPIO part1 and part2, the interval of base register
offset is 0x20 but GPF0, GPJ0, GPK0 and GPM0 have different offsets. Same goes
for the interrupt reg offset of GPF0 and GPK0. Refer to the layout below.
- Exynos4x12 GPIO Part1
GPIOBase offset Interrupt reg offset
GPA00x000 0x00
GPA10x020 0x04
GPB 0x040 0x08
GPC00x060 0x0C
GPC10x080 0x10
GPD00x0A0 0x14
GPD10x0C0 0x18
...
GPF00x180 0x30
GPF10x1A0 0x34
GPF20x1C0 0x38
GPF30x1E0 0x3C
...
GPJ00x240 0x40
GPJ10x260 0x44
- Exynos4x12 GPIO Part2
...
GPK00x040 0x08
GPK10x060 0x0C
GPK20x080 0x10
GPK30x0A0 0x14
GPL00x0C0 0x18
GPL10x0E0 0x1C
GPL20x100 0x20
GPY00x120 x
GPY10x140 x
GPY20x160 x
GPY30x180 x
GPY40x1A0 x
GPY50x1C0 x
GPY60x1E0 x
...
GPM00x260 0x24
GPM10x280 0x28
GPM20x2A0 0x2C
GPM30x2C0 0x30
GPM40x2E0 0x34
GPX00xC00 x
GPX10xC20 x
GPX20xC40 x
GPX30xC60 x
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mach-exynos/include/mach/gpio.h | 28 ++-
arch/arm/mach-exynos/include/mach/irqs.h | 6 -
drivers/gpio/gpio-samsung.c | 330 ---
3 files changed, 326 insertions(+), 38 deletions(-)
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h
b/arch/arm/mach-exynos/include/mach/gpio.h
index 21c9bf1..2103d14 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -26,11 +26,13 @@
#define EXYNOS4_GPIO_C1_NR (5)
#define EXYNOS4_GPIO_D0_NR (4)
#define EXYNOS4_GPIO_D1_NR (4)
+
#define EXYNOS4210_GPIO_E0_NR (5)
#define EXYNOS4210_GPIO_E1_NR (8)
#define EXYNOS4210_GPIO_E2_NR (6)
#define EXYNOS4210_GPIO_E3_NR (8)
#define EXYNOS4210_GPIO_E4_NR (8)
+
#define EXYNOS4_GPIO_F0_NR (8)
#define EXYNOS4_GPIO_F1_NR (8)
#define EXYNOS4_GPIO_F2_NR (8)
@@ -44,6 +46,13 @@
#define EXYNOS4_GPIO_L0_NR (8)
#define EXYNOS4_GPIO_L1_NR (3)
#define EXYNOS4_GPIO_L2_NR (8)
+
+#define EXYNOS4X12_GPIO_M0_NR (8)
+#define EXYNOS4X12_GPIO_M1_NR (7)
+#define EXYNOS4X12_GPIO_M2_NR (5)
+#define EXYNOS4X12_GPIO_M3_NR (8)
+#define EXYNOS4X12_GPIO_M4_NR (8)
+
#define EXYNOS4_GPIO_X0_NR (8)
#define EXYNOS4_GPIO_X1_NR (8)
#define EXYNOS4_GPIO_X2_NR (8)
@@ -67,12 +76,20 @@ enum exynos4_gpio_number {
EXYNOS4_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0),
EXYNOS4_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1),
EXYNOS4_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),
+
EXYNOS4210_GPIO_E0_START= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
EXYNOS4210_GPIO_E1_START= EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E0),
EXYNOS4210_GPIO_E2_START= EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E1),
EXYNOS4210_GPIO_E3_START= EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E2),
EXYNOS4210_GPIO_E4_START= EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E3),
- EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E4),
+
+ EXYNOS4X12_GPIO_M0_START= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
+ EXYNOS4X12_GPIO_M1_START= EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M0),
+ EXYNOS4X12_GPIO_M2_START= EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M1),
+ EXYNOS4X12_GPIO_M3_START= EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M2),
+ EXYNOS4X12_GPIO_M4_START= EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M3),
+
+ EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M4),
EXYNOS4_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0),
EXYNOS4_GPIO_F2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1),
EXYNOS4_GPIO_F3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
@@ -108,11 +125,13 @@ enum exynos4_gpio_number {
#define EXYNOS4_GPC1(_nr) (EXYNOS4_GPIO_C1_START + (_nr))
#define EXYNOS4_GPD0(_nr) (EXYNOS4_GPIO_D0_START + (_nr))
#define EXYNOS4_GPD1(_nr) (EXYNOS4_GPIO_D1_START + (_nr))
+
#define EXYNOS4210_GPE0(_nr) (EXYNOS4210_GPIO_E0_START + (_nr))
#define EXYNOS4210_GPE1(_nr) (EXYNOS4210_GPIO_E1_START + (_nr))
#define EXYNOS4210_GPE2(_nr) (EXYNOS4210_GPIO_E2_START + (_nr))
#define EXYNOS4210_GPE3(_nr) (EXYNOS4210_GPIO_E3_START + (_nr))
[PATCH 3/3] ARM: EXYNOS: Add support for FIMC cam port B GPIO setup on Exynos4x12
Exynos4x12 SoCs use different GPIO pins for FIMC cam port B and this patch
modifies the setup code to take it into account.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mach-exynos/setup-fimc.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/mach-exynos/setup-fimc.c
b/arch/arm/mach-exynos/setup-fimc.c
index d74843e..4b0cce5 100644
--- a/arch/arm/mach-exynos/setup-fimc.c
+++ b/arch/arm/mach-exynos/setup-fimc.c
@@ -11,6 +11,7 @@
#include linux/gpio.h
#include plat/gpio-cfg.h
#include plat/camport.h
+#include plat/cpu.h
int exynos4_fimc_setup_gpio(enum s5p_camport_id id)
{
@@ -26,6 +27,22 @@ int exynos4_fimc_setup_gpio(enum s5p_camport_id id)
break;
case S5P_CAMPORT_B:
+ if (soc_is_exynos4212() || soc_is_exynos4412()) {
+ sfn = S3C_GPIO_SFN(3);
+
+ /* PCLK, DATA[0-6] */
+ ret = s3c_gpio_cfgrange_nopull(EXYNOS4X12_GPM0(0), 8,
sfn);
+ /* FIELD, DATA[7]*/
+ if (!ret)
+ ret =
s3c_gpio_cfgrange_nopull(EXYNOS4X12_GPM1(0),
+ 2, sfn);
+ /* VSYNC, HREF, CLKOUT*/
+ if (!ret)
+ ret =
s3c_gpio_cfgrange_nopull(EXYNOS4X12_GPM2(0),
+ 3, sfn);
+ return ret;
+ }
+
gpio8 = EXYNOS4210_GPE0(0); /* DATA[0:7] */
gpio5 = EXYNOS4210_GPE1(0); /* PCLK, VSYNC, HREF, CLKOUT, FIELD
*/
sfn = S3C_GPIO_SFN(3);
--
1.7.12
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Re: [PATCH] ARM: EXYNOS: Add MFC device tree support
Hi Karol,
Thanks for your comments.
Please find my response inline.
On Mon, Aug 20, 2012 at 11:47 AM, Karol Lewandowski k.lewando...@samsung.com
wrote:
On 08/16/2012 08:42 PM, Thomas Abraham wrote:
On 16 August 2012 18:01, Arun Kumar K arun.kk ... @public.gmane.org wrote:
+ - interrupts : MFC interupt number to the CPU.
+
+ - samsung,mfc-r : Base address of the first memory bank used by MFC
+ for DMA contiguous memory allocation.
+
+ - samsung,mfc-r-size : Size of the first memory bank.
It is not allowed to pass buffer base address and size from device
tree. Device tree node should describe only the MFC controller
hardware. Any memory management related information should be handled
outside of device tree. This helps the bindings to be reusable across
multiple operating systems.
The question is where elsewhere this should be described as this is strictly
board-dependent option (number and size of RAM banks are important here).
I agree that base addresses are bad, but I'm not aware of any functionality
that would allow driver (actually, its platform dependent part in
exynosN_reserve() function) to enumerate available memory banks and grab
memory chunks from two distinct banks.
My (lack of) knowledge ARM might be to blame here but I simply don't know
how to achieve this. Any suggestions?
As suggested by kgene, I will pass it from the board specific dts file.
On 08/16/2012 09:31 PM, Arun Kumar K wrote:
+static void s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
+ phys_addr_t lbase, unsigned int lsize) {
+
+ if (memblock_remove(lbase, lsize)) {
+ pr_err(Failed to reserve bank1 memory for MFC device\n);
+ WARN_ON(1);
+ }
+
+ if (memblock_remove(rbase, rsize)) {
+ pr_err(Failed to reserve bank2 memory for MFC device\n);
+ WARN_ON(1);
+ }
+}
non-static function with the same name is already defined in
arch/arm/plat-samsung/s5p-dev-mfc.c. Please don't duplicate it,
especially that you seem to be trying to do that twice!
Ok, I will use the existing function.
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index ef770bc..898d2de 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
...
+static void s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
+ phys_addr_t lbase, unsigned int lsize) {
+
+ if (memblock_remove(lbase, lsize)) {
+ pr_err(Failed to reserve bank1 memory for MFC device\n);
+ WARN_ON(1);
+ }
+
+ if (memblock_remove(rbase, rsize)) {
+ pr_err(Failed to reserve bank2 memory for MFC device\n);
+ WARN_ON(1);
+ }
+}
See above.
+
+static void __init exynos5_reserve(void)
+{
+ s5p_mfc_reserve_mem(0x4300, 8 20, 0x5100, 8 20);
I think it would make sense to make this memory reservation dependent
on mfc* node being present in DTS. It's to early to use of_* functions
(because tree is not populated at this stage) but fdt_* family of functions
work just fine.
As I can see the fdt_* functions are not used in any of the ARM based SoC
init codes. Though I can see some references in powerpc.
The implementation and includes are present in arch/arm/boot/compressed/
which I think cannot be used directly in mach-exynos unless we make some
comon makefile changes.
Please clarify whether its ok to use fdt_* functions to parse the dts in
exynos machine init or please point me to some sample implementations
which I can refer to.
Regards
Arun
Regards
Arun
RE: [PATCH v4 4/9] mmc: dw_mmc: lookup for optional biu and ciu clocks
On Sunday, August 26, 2012 Thomas Abraham thomas.abra...@linaro.org wrote:
Some platforms allow for clock gating and control of bus interface unit clock
and card interface unit clock. Add support for clock lookup of optional biu
and ciu clocks for clock gating and clock speed determination.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
drivers/mmc/host/dw_mmc.c | 42 +++---
include/linux/mmc/dw_mmc.h |4
2 files changed, 43 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index cd58063..679473c 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -1953,18 +1953,38 @@ int dw_mci_probe(struct dw_mci *host)
return -ENODEV;
}
- if (!host-pdata-bus_hz) {
+ host-biu_clk = clk_get(host-dev, biu);
+ if (IS_ERR(host-biu_clk))
+ dev_dbg(host-dev, biu clock not available\n);
+ else
+ clk_prepare_enable(host-biu_clk);
+
+ host-ciu_clk = clk_get(host-dev, ciu);
+ if (IS_ERR(host-ciu_clk))
+ dev_dbg(host-dev, ciu clock not available\n);
+ else
+ clk_prepare_enable(host-ciu_clk);
+
+ if (IS_ERR(host-ciu_clk))
+ host-bus_hz = host-pdata-bus_hz;
+ else
+ host-bus_hz = clk_get_rate(host-ciu_clk);
I have remained comment in [PATCH 3/9] mmc: dw_mmc: lookup for optional biu and
ciu clocks
Could I get your opinion?
Thanks,
Seungwon Jeon
+
+ if (!host-bus_hz) {
dev_err(host-dev,
Platform data must supply bus speed\n);
- return -ENODEV;
+ ret = -ENODEV;
+ goto err_clk;
}
- host-bus_hz = host-pdata-bus_hz;
host-quirks = host-pdata-quirks;
spin_lock_init(host-lock);
INIT_LIST_HEAD(host-queue);
+ host-dma_ops = host-pdata-dma_ops;
+ dw_mci_init_dma(host);
+
/*
* Get the host data width - this assumes that HCON has been set with
* the correct values.
@@ -2109,6 +2129,16 @@ err_dmaunmap:
regulator_disable(host-vmmc);
regulator_put(host-vmmc);
}
+
+err_clk:
+ if (!IS_ERR(host-ciu_clk)) {
+ clk_disable_unprepare(host-ciu_clk);
+ clk_put(host-ciu_clk);
+ }
+ if (!IS_ERR(host-biu_clk)) {
+ clk_disable_unprepare(host-biu_clk);
+ clk_put(host-biu_clk);
+ }
return ret;
}
EXPORT_SYMBOL(dw_mci_probe);
@@ -2142,6 +2172,12 @@ void dw_mci_remove(struct dw_mci *host)
regulator_put(host-vmmc);
}
+ if (!IS_ERR(host-ciu_clk))
+ clk_disable_unprepare(host-ciu_clk);
+ if (!IS_ERR(host-biu_clk))
+ clk_disable_unprepare(host-biu_clk);
+ clk_put(host-ciu_clk);
+ clk_put(host-biu_clk);
}
EXPORT_SYMBOL(dw_mci_remove);
diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
index a37a573..787ad56 100644
--- a/include/linux/mmc/dw_mmc.h
+++ b/include/linux/mmc/dw_mmc.h
@@ -78,6 +78,8 @@ struct mmc_data;
* @data_offset: Set the offset of DATA register according to VERID.
* @dev: Device associated with the MMC controller.
* @pdata: Platform data associated with the MMC controller.
+ * @biu_clk: Pointer to bus interface unit clock instance.
+ * @ciu_clk: Pointer to card interface unit clock instance.
* @slot: Slots sharing this MMC controller.
* @fifo_depth: depth of FIFO.
* @data_shift: log2 of FIFO item size.
@@ -158,6 +160,8 @@ struct dw_mci {
u16 data_offset;
struct device *dev;
struct dw_mci_board *pdata;
+ struct clk *biu_clk;
+ struct clk *ciu_clk;
struct dw_mci_slot *slot[MAX_MCI_SLOTS];
/* FIFO push and pull */
--
1.6.6.rc2
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RE: [PATCH v4 9/9] mmc: dw_mmc: add support for exynos specific implementation of dw-mshc
On Tuesday, August 28, 2012 Thomas Abraham thomas.abra...@linaro.org wrote:
Hi Seungwon,
On 28 August 2012 12:36, Seungwon Jeon tgih@samsung.com wrote:
Hi Thomas,
Thank you for your effort.
Some reviews seems like to be omitted. Please check more.
On Sunday, August 26, 2012 Thomas Abraham thomas.abra...@linaro.org wrote:
Samsung Exynos SoC's extend the dw-mshc controller for additional clock
and bus
control. Add support for these extensions and include provide device tree
based
discovery suppory as well.
[...]
+static struct dw_mci_exynos_compatible {
+ char*compatible;
+ enum dw_mci_exynos_type ctrl_type;
+} exynos_compat[] = {
+ {
+ .compatible = samsung,exynos4210-dw-mshc,
+ .ctrl_type = DW_MCI_TYPE_EXYNOS4210,
+ }, {
+ .compatible = samsung,exynos4210-dw-mshc,
typo? exynos4412-dw-mshc is expected.
Yes, that was a typo. I will fix it.
[...]
+static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
+{
+ struct dw_mci_exynos_priv_data *priv = host-priv;
+ u8 drv;
+
+ /*
+ * Exynos4412 and Exynos5250 extends the use of CMD register with the
+ * use of bit 29 (which is reserved on standard MSHC controllers) for
+ * optionally bypassing the HOLD register for command and data. The
+ * HOLD register should be bypassed in case there is no phase shift
+ * applied on CMD/DATA that is sent to the card.
+ */
+ if (priv-ctrl_type == DW_MCI_TYPE_EXYNOS4412)
+ drv = SDMMC_CLKSEL_GET_DRV_WD2(mci_readl(host, CLKSEL));
As it has been mentioned previously, only exynos4210 uses 2-bit.
So SDMMC_CLKSEL_GET_DRV_WD3 will be right in exynos4412.
In the Exynos4412 user manual that I referred, the SelClk_Drv and
SelClk_Sample bit fields of the CLKSEL register are 2 bits wide. Could
you please confirm that these two bit-fields are in fact 3 bits wide?
I think you are referring old manual. 3-bit is right.
I hope you find this.
+ else if (priv-ctrl_type == DW_MCI_TYPE_EXYNOS5250)
+ drv = SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL));
+ else
+ return;
+ if (drv)
+ *cmdr |= SDMMC_CMD_USE_HOLD_REG;
+}
+
+static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios
*ios)
+{
+ struct dw_mci_exynos_priv_data *priv = host-priv;
+
+ if (ios-timing == MMC_TIMING_UHS_DDR50)
+ mci_writel(host, CLKSEL, priv-ddr_timing);
+ else
+ mci_writel(host, CLKSEL, priv-sdr_timing);
+
+ host-bus_hz = clk_get_rate(host-ciu_clk);
+ if (priv-ctrl_type == DW_MCI_TYPE_EXYNOS5250)
+ host-bus_hz /= SDMMC_CLKSEL_GET_DIVRATIO(
+ mci_readl(host, CLKSEL));
bus_hz should be recalculated for exynoxs4 as well.
Could you check the previous mailing?
Exynos4 does not have the additional clock divisor, as in Exynos5250.
Could you please explain why the bus_hz clock should be divided in
Exynos4?
Yes, clock divisor is used in Exynos5250.
In case of Exynos4 SoC's, divider value(DIVRATIO) isn't exposed to register.
But SDCLKIN is divided by fixed divider value internally.
As mentioned previously, divider is used like below.
Exynos4210 : 2
Exynos4X12 : 4
+}
+
+static int dw_mci_exynos_parse_dt(struct dw_mci *host)
+{
+ struct dw_mci_exynos_priv_data *priv = host-priv;
+ u32 timing[3];
+
+ if (of_property_read_u32_array(host-dev-of_node,
+ samsung,dw-mshc-sdr-timing, timing, 3))
+ priv-sdr_timing = DW_MCI_DEF_SDR_TIMING;
+ else
+ priv-sdr_timing = SDMMC_CLKSEL_TIMING(timing[0],
+ timing[1], timing[2]);
+
+ if (of_property_read_u32_array(host-dev-of_node,
+ samsung,dw-mshc-ddr-timing, timing, 3))
+ priv-ddr_timing = DW_MCI_DEF_DDR_TIMING;
+ else
+ priv-ddr_timing = SDMMC_CLKSEL_TIMING(timing[0],
+ timing[1], timing[2]);
+ return 0;
DW_MCI_DEF_SDR_TIMING and DW_MCI_DEF_DDR_TIMING are board-specific timing
values.
So, these values can't be used commonly. It has been already discussed.
If this property is empty, returning error with message will be fine.
Currently just 0 is always returned.
Yes, you had mentioned this previously. But these are only default
values. In case, a board cannot work with these default values, the
board's dtsi file should provide the correct values by using these
bindings. What is your opinion on this, please let me know.
Is there any basis for these value which you chose?
If these can be acceptable for the most part, we can consider it for default
value.
But it depends on host of SOC and target board.
Thanks,
Seungwon Jeon
[PATCH] ARM: EXYNOS: Use non-secure MDMA1
Using secure MDMA1 on TrustZone-enabled boards causes early boot crash,
so use non-secure instead.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/dma.c | 2 +-
arch/arm/mach-exynos/include/mach/map.h | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index f60b66d..8858df5 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -261,7 +261,7 @@ static struct dma_pl330_platdata exynos_mdma1_pdata = {
};
static AMBA_AHB_DEVICE(exynos_mdma1, dma-pl330.2, 0x00041330,
- EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, exynos_mdma1_pdata);
+ EXYNOS4_PA_NS_MDMA1, {EXYNOS4_IRQ_MDMA1}, exynos_mdma1_pdata);
static int __init exynos_dma_init(void)
{
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-
exynos/include/mach/map.h
index 51943f2..5df5910 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -89,7 +89,8 @@
#define EXYNOS4_PA_L2CC0x10502000
#define EXYNOS4_PA_MDMA0 0x1081
-#define EXYNOS4_PA_MDMA1 0x1284
+#define EXYNOS4_PA_S_MDMA1 0x1284
+#define EXYNOS4_PA_NS_MDMA10x1285
#define EXYNOS4_PA_PDMA0 0x1268
#define EXYNOS4_PA_PDMA1 0x1269
#define EXYNOS5_PA_MDMA0 0x1080
--
1.7.12
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[PATCH] ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412
Exynos4412 uses different information register for each core. This patch
adjusts the bring-up code to take that into account.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/platsmp.c | 25 -
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 36c3984..1114ced 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -34,8 +34,19 @@
extern void exynos4_secondary_startup(void);
-#define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
- S5P_INFORM5 : S5P_VA_SYSRAM)
+static inline volatile void *cpu_boot_reg_base(void)
+{
+ if (soc_is_exynos4210() samsung_rev() == EXYNOS4210_REV_1_1)
+ return S5P_INFORM5;
+ return S5P_VA_SYSRAM;
+}
+
+static inline volatile void *cpu_boot_reg(int cpu)
+{
+ if (soc_is_exynos4412())
+ return cpu_boot_reg_base() + 4*cpu;
+ return cpu_boot_reg_base();
+}
/*
* control for which core is the next to come out of the secondary
@@ -138,7 +149,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct
task_struct *idle)
smp_rmb();
__raw_writel(virt_to_phys(exynos4_secondary_startup),
- CPU1_BOOT_REG);
+ cpu_boot_reg(cpu));
gic_raise_softirq(cpumask_of(cpu), 1);
if (pen_release == -1)
@@ -186,6 +197,8 @@ void __init smp_init_cpus(void)
void __init platform_smp_prepare_cpus(unsigned int max_cpus)
{
+ int i;
+
if (!soc_is_exynos5250())
scu_enable(scu_base_addr());
@@ -195,6 +208,8 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*/
- __raw_writel(virt_to_phys(exynos4_secondary_startup),
- CPU1_BOOT_REG);
+ for (i = 1; i max_cpus; ++i) {
+ __raw_writel(virt_to_phys(exynos4_secondary_startup),
+ cpu_boot_reg(i));
+ }
}
--
1.7.12
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Re: [PATCH v4 4/9] mmc: dw_mmc: lookup for optional biu and ciu clocks
On 28 August 2012 16:13, Seungwon Jeon tgih@samsung.com wrote:
On Sunday, August 26, 2012 Thomas Abraham thomas.abra...@linaro.org wrote:
Some platforms allow for clock gating and control of bus interface unit clock
and card interface unit clock. Add support for clock lookup of optional biu
and ciu clocks for clock gating and clock speed determination.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
drivers/mmc/host/dw_mmc.c | 42 +++---
include/linux/mmc/dw_mmc.h |4
2 files changed, 43 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index cd58063..679473c 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -1953,18 +1953,38 @@ int dw_mci_probe(struct dw_mci *host)
return -ENODEV;
}
- if (!host-pdata-bus_hz) {
+ host-biu_clk = clk_get(host-dev, biu);
+ if (IS_ERR(host-biu_clk))
+ dev_dbg(host-dev, biu clock not available\n);
+ else
+ clk_prepare_enable(host-biu_clk);
+
+ host-ciu_clk = clk_get(host-dev, ciu);
+ if (IS_ERR(host-ciu_clk))
+ dev_dbg(host-dev, ciu clock not available\n);
+ else
+ clk_prepare_enable(host-ciu_clk);
+
+ if (IS_ERR(host-ciu_clk))
+ host-bus_hz = host-pdata-bus_hz;
+ else
+ host-bus_hz = clk_get_rate(host-ciu_clk);
I have remained comment in [PATCH 3/9] mmc: dw_mmc: lookup for optional biu
and ciu clocks
Could I get your opinion?
Are you referring to the following comment.
I have posted similar patch some time back.
bus_hz represents input rate for cclk_in of mshc.
Host of samsung soc doesn't use input clock from system directly.
As you have introduced CLKSEL in your another patch, input clock can be
changed prior to cclk_in.
For non-samsung host, we don't need to consider this with generic way?
The biu and ciu clocks are generic clocks which a platform can
instantiate. The other option being to use the platform data to
specify the clock speed using pdata-bus_hz.
The use CLKSEL register is now moved into exynos specific code. So
non-samsung host is not affected in any way.
Thanks,
Thomas.
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Re: [PATCH v4 9/9] mmc: dw_mmc: add support for exynos specific implementation of dw-mshc
On 28 August 2012 16:13, Seungwon Jeon tgih@samsung.com wrote:
On Tuesday, August 28, 2012 Thomas Abraham thomas.abra...@linaro.org wrote:
Hi Seungwon,
On 28 August 2012 12:36, Seungwon Jeon tgih@samsung.com wrote:
[...]
+ /*
+ * Exynos4412 and Exynos5250 extends the use of CMD register with
the
+ * use of bit 29 (which is reserved on standard MSHC controllers)
for
+ * optionally bypassing the HOLD register for command and data. The
+ * HOLD register should be bypassed in case there is no phase shift
+ * applied on CMD/DATA that is sent to the card.
+ */
+ if (priv-ctrl_type == DW_MCI_TYPE_EXYNOS4412)
+ drv = SDMMC_CLKSEL_GET_DRV_WD2(mci_readl(host, CLKSEL));
As it has been mentioned previously, only exynos4210 uses 2-bit.
So SDMMC_CLKSEL_GET_DRV_WD3 will be right in exynos4412.
In the Exynos4412 user manual that I referred, the SelClk_Drv and
SelClk_Sample bit fields of the CLKSEL register are 2 bits wide. Could
you please confirm that these two bit-fields are in fact 3 bits wide?
I think you are referring old manual. 3-bit is right.
I hope you find this.
Ok. Maybe I have an older manual then. I will change it to 3-bit for 4412.
[...]
+static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios
*ios)
+{
+ struct dw_mci_exynos_priv_data *priv = host-priv;
+
+ if (ios-timing == MMC_TIMING_UHS_DDR50)
+ mci_writel(host, CLKSEL, priv-ddr_timing);
+ else
+ mci_writel(host, CLKSEL, priv-sdr_timing);
+
+ host-bus_hz = clk_get_rate(host-ciu_clk);
+ if (priv-ctrl_type == DW_MCI_TYPE_EXYNOS5250)
+ host-bus_hz /= SDMMC_CLKSEL_GET_DIVRATIO(
+ mci_readl(host, CLKSEL));
bus_hz should be recalculated for exynoxs4 as well.
Could you check the previous mailing?
Exynos4 does not have the additional clock divisor, as in Exynos5250.
Could you please explain why the bus_hz clock should be divided in
Exynos4?
Yes, clock divisor is used in Exynos5250.
In case of Exynos4 SoC's, divider value(DIVRATIO) isn't exposed to register.
But SDCLKIN is divided by fixed divider value internally.
As mentioned previously, divider is used like below.
Exynos4210 : 2
Exynos4X12 : 4
Ok. Thanks for the information. I will add divisor support for Exynos4
as well. These patches have not been tested with Exynos4 since I do
not have a Exynos4 based board that uses dw-mmc controller.
[...]
DW_MCI_DEF_SDR_TIMING and DW_MCI_DEF_DDR_TIMING are board-specific timing
values.
So, these values can't be used commonly. It has been already discussed.
If this property is empty, returning error with message will be fine.
Currently just 0 is always returned.
Yes, you had mentioned this previously. But these are only default
values. In case, a board cannot work with these default values, the
board's dtsi file should provide the correct values by using these
bindings. What is your opinion on this, please let me know.
Is there any basis for these value which you chose?
If these can be acceptable for the most part, we can consider it for default
value.
But it depends on host of SOC and target board.
Ok. I will remove the optional value and make this property mandatory.
Thanks,
Thomas.
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Re: [PATCH 1/3] ARM: EXYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx
On 28 August 2012 15:36, Tomasz Figa t.f...@samsung.com wrote: The GPEx gpios are specific to Exynos4210 and do not exist on Exynos4x12. Redefine them to use the exact SoC name. Based on ARM: EXYYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx by Joonyoung Shim, see: http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/100738.html Signed-off-by: Tomasz Figa t.f...@samsung.com --- arch/arm/mach-exynos/include/mach/gpio.h | 32 +++--- arch/arm/mach-exynos/mach-nuri.c | 16 +++ arch/arm/mach-exynos/mach-origen.c | 6 +++--- arch/arm/mach-exynos/mach-trats.c | 4 ++-- arch/arm/mach-exynos/mach-universal_c210.c | 32 +++--- arch/arm/mach-exynos/setup-fimc.c | 4 ++-- drivers/gpio/gpio-samsung.c| 20 +-- 7 files changed, 57 insertions(+), 57 deletions(-) Reviewed-by: Thomas Abraham thomas.abra...@linaro.org [...] -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/3] gpio: samsung: Add support for Exynos4x12 SoCs
On 28 August 2012 15:36, Tomasz Figa t.f...@samsung.com wrote:
Based on patch gpio/exynos: Add support for Exynos4x12 SoC by Joonyoung
Shim.
See:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/100737.html
Exynos4x12 GPIO part1 and part2 have different layout than Exynos4210,
so the initialization code has to be modified to support Exynos4x12 SoC.
GPVx Exynos4x12 GPIO part4 is not supported yet.
In the Exynos4x12 GPIO part1 and part2, the interval of base register
offset is 0x20 but GPF0, GPJ0, GPK0 and GPM0 have different offsets. Same goes
for the interrupt reg offset of GPF0 and GPK0. Refer to the layout below.
- Exynos4x12 GPIO Part1
GPIOBase offset Interrupt reg offset
GPA00x000 0x00
GPA10x020 0x04
GPB 0x040 0x08
GPC00x060 0x0C
GPC10x080 0x10
GPD00x0A0 0x14
GPD10x0C0 0x18
...
GPF00x180 0x30
GPF10x1A0 0x34
GPF20x1C0 0x38
GPF30x1E0 0x3C
...
GPJ00x240 0x40
GPJ10x260 0x44
- Exynos4x12 GPIO Part2
...
GPK00x040 0x08
GPK10x060 0x0C
GPK20x080 0x10
GPK30x0A0 0x14
GPL00x0C0 0x18
GPL10x0E0 0x1C
GPL20x100 0x20
GPY00x120 x
GPY10x140 x
GPY20x160 x
GPY30x180 x
GPY40x1A0 x
GPY50x1C0 x
GPY60x1E0 x
...
GPM00x260 0x24
GPM10x280 0x28
GPM20x2A0 0x2C
GPM30x2C0 0x30
GPM40x2E0 0x34
GPX00xC00 x
GPX10xC20 x
GPX20xC40 x
GPX30xC60 x
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mach-exynos/include/mach/gpio.h | 28 ++-
arch/arm/mach-exynos/include/mach/irqs.h | 6 -
drivers/gpio/gpio-samsung.c | 330
---
3 files changed, 326 insertions(+), 38 deletions(-)
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h
b/arch/arm/mach-exynos/include/mach/gpio.h
index 21c9bf1..2103d14 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -26,11 +26,13 @@
#define EXYNOS4_GPIO_C1_NR (5)
#define EXYNOS4_GPIO_D0_NR (4)
#define EXYNOS4_GPIO_D1_NR (4)
+
#define EXYNOS4210_GPIO_E0_NR (5)
#define EXYNOS4210_GPIO_E1_NR (8)
#define EXYNOS4210_GPIO_E2_NR (6)
#define EXYNOS4210_GPIO_E3_NR (8)
#define EXYNOS4210_GPIO_E4_NR (8)
+
#define EXYNOS4_GPIO_F0_NR (8)
#define EXYNOS4_GPIO_F1_NR (8)
#define EXYNOS4_GPIO_F2_NR (8)
@@ -44,6 +46,13 @@
#define EXYNOS4_GPIO_L0_NR (8)
#define EXYNOS4_GPIO_L1_NR (3)
#define EXYNOS4_GPIO_L2_NR (8)
+
+#define EXYNOS4X12_GPIO_M0_NR (8)
+#define EXYNOS4X12_GPIO_M1_NR (7)
+#define EXYNOS4X12_GPIO_M2_NR (5)
+#define EXYNOS4X12_GPIO_M3_NR (8)
+#define EXYNOS4X12_GPIO_M4_NR (8)
+
#define EXYNOS4_GPIO_X0_NR (8)
#define EXYNOS4_GPIO_X1_NR (8)
#define EXYNOS4_GPIO_X2_NR (8)
@@ -67,12 +76,20 @@ enum exynos4_gpio_number {
EXYNOS4_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0),
EXYNOS4_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1),
EXYNOS4_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),
+
EXYNOS4210_GPIO_E0_START= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
EXYNOS4210_GPIO_E1_START=
EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E0),
EXYNOS4210_GPIO_E2_START=
EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E1),
EXYNOS4210_GPIO_E3_START=
EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E2),
EXYNOS4210_GPIO_E4_START=
EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E3),
- EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E4),
+
+ EXYNOS4X12_GPIO_M0_START= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
+ EXYNOS4X12_GPIO_M1_START=
EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M0),
+ EXYNOS4X12_GPIO_M2_START=
EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M1),
+ EXYNOS4X12_GPIO_M3_START=
EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M2),
+ EXYNOS4X12_GPIO_M4_START=
EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M3),
+
+ EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M4),
EXYNOS4_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0),
EXYNOS4_GPIO_F2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1),
EXYNOS4_GPIO_F3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
@@ -108,11 +125,13 @@ enum exynos4_gpio_number {
#define EXYNOS4_GPC1(_nr) (EXYNOS4_GPIO_C1_START + (_nr))
#define EXYNOS4_GPD0(_nr) (EXYNOS4_GPIO_D0_START + (_nr))
#define EXYNOS4_GPD1(_nr) (EXYNOS4_GPIO_D1_START + (_nr))
+
#define EXYNOS4210_GPE0(_nr) (EXYNOS4210_GPIO_E0_START + (_nr))
Re: [PATCH 0/3] ARM: EXYNOS: Add support for GPIO on Exynos4x12
On 28 August 2012 15:31, Tomasz Figa t.f...@samsung.com wrote: This patch series makes necessary preparations and adds support for GPIO on Exynos4x12 SoCs. Tomasz Figa (3): ARM: EXYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx gpio: samsung: Add support for Exynos4x12 SoCs ARM: EXYNOS: Add support for FIMC cam port B GPIO setup on Exynos4x12 arch/arm/mach-exynos/include/mach/gpio.h | 58 -- arch/arm/mach-exynos/include/mach/irqs.h |6 - arch/arm/mach-exynos/mach-nuri.c | 16 +- arch/arm/mach-exynos/mach-origen.c |6 +- arch/arm/mach-exynos/mach-trats.c |4 +- arch/arm/mach-exynos/mach-universal_c210.c | 32 ++-- arch/arm/mach-exynos/setup-fimc.c | 21 ++- drivers/gpio/gpio-samsung.c| 351 8 files changed, 399 insertions(+), 95 deletions(-) -- 1.7.8.6 Hopefully, we can get device tree support merged for Exynos4412 soon and then switch over to using pinctrl driver. That can simplfy the gpio/pinmux support for Exynos4 SoC's. Thanks, Thomas. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412
On 8/28/2012 4:13 AM, Tomasz Figa wrote:
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 36c3984..1114ced 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -34,8 +34,19 @@
extern void exynos4_secondary_startup(void);
-#define CPU1_BOOT_REG(samsung_rev() == EXYNOS4210_REV_1_1 ? \
- S5P_INFORM5 : S5P_VA_SYSRAM)
+static inline volatile void *cpu_boot_reg_base(void)
__iomem?
+{
+ if (soc_is_exynos4210() samsung_rev() == EXYNOS4210_REV_1_1)
+ return S5P_INFORM5;
+ return S5P_VA_SYSRAM;
+}
+
+static inline volatile void *cpu_boot_reg(int cpu)
__iomem? And why volatile?
+{
+ if (soc_is_exynos4412())
+ return cpu_boot_reg_base() + 4*cpu;
+ return cpu_boot_reg_base();
+}
/*
* control for which core is the next to come out of the secondary
@@ -195,6 +208,8 @@ void __init platform_smp_prepare_cpus(unsigned int
max_cpus)
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*/
- __raw_writel(virt_to_phys(exynos4_secondary_startup),
- CPU1_BOOT_REG);
+ for (i = 1; i max_cpus; ++i) {
+ __raw_writel(virt_to_phys(exynos4_secondary_startup),
+ cpu_boot_reg(i));
Do you need to use cpu_logical_map()?
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Re: [RESUBMIT PATCH] ASoC: SAMSUNG: Change Kconfig to support all SAMSUNG ASoC
On Tue, Aug 28, 2012 at 05:55:49PM +0900, Sangsu Park wrote: All SAMSUNG ASoC needs SND_SOC_SAMSUNG configuration. This patch change Kconfig to support all SAMSUNG ASoC. Applied, thanks. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412
Hi,
Thanks for reviewing the patch.
On Tuesday 28 of August 2012 09:21:40 Stephen Boyd wrote:
On 8/28/2012 4:13 AM, Tomasz Figa wrote:
diff --git a/arch/arm/mach-exynos/platsmp.c
b/arch/arm/mach-exynos/platsmp.c index 36c3984..1114ced 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -34,8 +34,19 @@
extern void exynos4_secondary_startup(void);
-#define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
- S5P_INFORM5 : S5P_VA_SYSRAM)
+static inline volatile void *cpu_boot_reg_base(void)
__iomem?
Sorry, bad habit. I will fix it.
+{
+ if (soc_is_exynos4210() samsung_rev() == EXYNOS4210_REV_1_1)
+ return S5P_INFORM5;
+ return S5P_VA_SYSRAM;
+}
+
+static inline volatile void *cpu_boot_reg(int cpu)
__iomem? And why volatile?
Ditto.
+{
+ if (soc_is_exynos4412())
+ return cpu_boot_reg_base() + 4*cpu;
+ return cpu_boot_reg_base();
+}
/*
* control for which core is the next to come out of the secondary
@@ -195,6 +208,8 @@ void __init platform_smp_prepare_cpus(unsigned int
max_cpus)
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*/
- __raw_writel(virt_to_phys(exynos4_secondary_startup),
- CPU1_BOOT_REG);
+ for (i = 1; i max_cpus; ++i) {
+ __raw_writel(virt_to_phys(exynos4_secondary_startup),
+ cpu_boot_reg(i));
Do you need to use cpu_logical_map()?
Correct me if I am wrong, but physical to logical CPU mapping will not be
1:1 only if booted on physical CPU other than 0. I have not seen yet an
Exynos-based board which does it.
However it might be wiser to use cpu_logical_map() just to be safe indeed.
I will add it in next version of the patch.
--
Best regards,
Tomasz Figa
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Re: [PATCH 0/3] Removal of obsolete s3c2410_* GPIO API
On 08/28/2012 01:33 AM, Kukjin Kim wrote: On 08/25/12 05:20, Sylwester Nawrocki wrote: This short patch series converts remaining users of the s3c24xx SoC specific gpiolib functions to the gpiolib API and finally removes all s3c2410_* functions from drivers/gpio/gpio-samsung.c. Sylwester Nawrocki (3): ARM: S3C24XX: Convert users of s3c2410_gpio_setpin to gpiolib API ARM: S3C24XX: Remove obsolete GPIO API declarations gpio-samsung: Remove now unused s3c2410_gpio* API arch/arm/mach-s3c24xx/mach-anubis.c | 3 +- arch/arm/mach-s3c24xx/mach-jive.c | 12 ++-- arch/arm/mach-s3c24xx/mach-mini2440.c | 4 +- arch/arm/mach-s3c24xx/mach-nexcoder.c | 22 +++--- arch/arm/mach-s3c24xx/mach-osiris.c | 7 +- arch/arm/plat-samsung/include/plat/gpio-fns.h | 97 - drivers/gpio/gpio-samsung.c | 40 -- 7 files changed, 25 insertions(+), 160 deletions(-) Nice cleanup. Thanks for taking care of this whole series. I thought it needs to be done as we go adding more and more new code.. For time being it is my last GPIO cleanup patch series ;) Accordingly, we need to sort out the 'Documentation/arm/Samsung-S3C24XX/GPIO.txt' later? Indeed, I let this out for a moment. Let me tidy this up as well, when I find some time. Thanks, Sylwester Linus, this series should be sent to upstream via both trees, samsung and gpio to avoid useless merge conflicts. How do you think? Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: S3C24XX: Add .get_rate callback for camif-upll clock
On 08/28/2012 12:58 AM, Kukjin Kim wrote:
On 08/27/12 13:12, Sylwester Nawrocki wrote:
Add missing get_rate callback for the camif-upll clock, so frequency
of this clock is properly reported with clk_get_rate().
Signed-off-by: Sylwester Nawrockisylvester.nawro...@gmail.com
---
arch/arm/mach-s3c24xx/clock-s3c2440.c | 14 ++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c
b/arch/arm/mach-s3c24xx/clock-s3c2440.c
index cb2883d..749220f 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2440.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c
@@ -87,6 +87,19 @@ static int s3c2440_camif_upll_setrate(struct clk
*clk, unsigned long rate)
return 0;
}
+static unsigned long s3c2440_camif_upll_getrate(struct clk *clk)
+{
+ unsigned long parent_rate = clk_get_rate(clk-parent);
+ unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
+
+ if (!(camdivn S3C2440_CAMDIVN_CAMCLK_SEL))
+ return parent_rate;
+
+ camdivn= S3C2440_CAMDIVN_CAMCLK_MASK;
+
+ return parent_rate / (camdivn + 1) / 2;
Well, why do we need '/ 2' here?
I simply followed documentation of the camera clock divider register
(CAMDIVN). This is how CAMCLK_SEL and CAMCLK_DIV bit fields are described
there:
CAMDIVN | Bit | Description
--
CAMCLK_SEL | [4] | 0 : Use CAMCLK with UPLL output(CAMCLK=UPLL output)
| | 1 : CAMCLK is divided by CAMCLK_DIV value
-+---+
CAMCLK_DIV | [3:0] | CAMCLK divide factor setting register(0 – 15).
| | Camera clock = UPLL / [(CAMCLK_DIV +1)x2].
| | This bit is valid when CAMCLK_SEL=1.
So, camera clock frequency = parent_rate / ((camdivn + 1) * 2).
This is exactly same as 'parent_rate / ( camdivn + 1) / 2'.
To be 1000% sure I compared frequency values reported from clk_get_rate()
in the driver with values measured with an oscilloscope at the CAMCLKOUT
pin. Everything was as expected (UPLL - 48 MHz, CAMCLKOUT - 12 MHz).
Also, it's easy to confirm correctness of this code by inversing equations
found in function s3c2440_camif_upll_setrate(), i.e.
camdivn = ~(S3C2440_CAMDIVN_CAMCLK_SEL | S3C2440_CAMDIVN_CAMCLK_MASK);
if (rate != parent_rate) {
camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
camdivn |= (((parent_rate / rate) / 2) - 1);
}
__raw_writel(camdivn, S3C2440_CAMDIVN);
--
Regards,
Sylwester
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[PATCH v2] gpio: samsung: add devicetree init for s3c24xx arches
Until now the Exynos-SoC was the only Samsung-SoC supporting the GPIOs
via the device tree. This patch implements dt-support for the
s3c24xx arches.
The controllers contain only 3 cells, as the underlying gpio controller
does not support controlling the drive strength on a gpio level.
Tested with the gpio-keys driver on a s3c2416 based machine.
Signed-off-by: Heiko Stuebner he...@sntech.de
Reviewed-by: Thomas Abraham thomas.abra...@linaro.org
---
changes since v1:
update bindings documentation to address SoC specific issues
.../devicetree/bindings/gpio/gpio-samsung.txt | 43 +
drivers/gpio/gpio-samsung.c| 63
2 files changed, 106 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
index 5375625..f1e5dfe 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
@@ -39,3 +39,46 @@ Example:
#gpio-cells = 4;
gpio-controller;
};
+
+
+Samsung S3C24XX GPIO Controller
+
+Required properties:
+- compatible: Compatible property value should be samsung,s3c24xx-gpio.
+
+- reg: Physical base address of the controller and length of memory mapped
+ region.
+
+- #gpio-cells: Should be 3. The syntax of the gpio specifier used by client
nodes
+ should be the following with values derived from the SoC user manual.
+ [phandle of the gpio controller node]
+ [pin number within the gpio controller]
+ [mux function]
+ [flags and pull up/down]
+
+ Values for gpio specifier:
+ - Pin number: depending on the controller a number from 0 up to 15.
+ - Mux function: Depending on the SoC and the gpio bank the gpio can be set
+ as input, output or a special function
+ - Flags and Pull Up/Down: the values to use differ for the individual SoCs
+example S3C2416/S3C2450:
+0 - Pull Up/Down Disabled.
+1 - Pull Down Enabled.
+2 - Pull Up Enabled.
+ Bit 16 (0x0001) - Input is active low.
+ Consult the user manual for the correct values of Mux and Pull Up/Down.
+
+- gpio-controller: Specifies that the node is a gpio controller.
+- #address-cells: should be 1.
+- #size-cells: should be 1.
+
+Example:
+
+ gpa: gpio-controller@5600 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = samsung,s3c24xx-gpio;
+ reg = 0x5600 0x10;
+ #gpio-cells = 3;
+ gpio-controller;
+ };
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index ba126cc..54f6663 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -938,6 +938,67 @@ static void __init samsung_gpiolib_add(struct
samsung_gpio_chip *chip)
s3c_gpiolib_track(chip);
}
+#if defined(CONFIG_PLAT_S3C24XX) defined(CONFIG_OF)
+static int s3c24xx_gpio_xlate(struct gpio_chip *gc,
+ const struct of_phandle_args *gpiospec, u32 *flags)
+{
+ unsigned int pin;
+
+ if (WARN_ON(gc-of_gpio_n_cells 3))
+ return -EINVAL;
+
+ if (WARN_ON(gpiospec-args_count gc-of_gpio_n_cells))
+ return -EINVAL;
+
+ if (gpiospec-args[0] gc-ngpio)
+ return -EINVAL;
+
+ pin = gc-base + gpiospec-args[0];
+
+ if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec-args[1])))
+ pr_warn(gpio_xlate: failed to set pin function\n);
+ if (s3c_gpio_setpull(pin, gpiospec-args[2] 0x))
+ pr_warn(gpio_xlate: failed to set pin pull up/down\n);
+
+ if (flags)
+ *flags = gpiospec-args[2] 16;
+
+ return gpiospec-args[0];
+}
+
+static const struct of_device_id s3c24xx_gpio_dt_match[] __initdata = {
+ { .compatible = samsung,s3c24xx-gpio, },
+ {}
+};
+
+static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip
*chip,
+u64 base, u64 offset)
+{
+ struct gpio_chip *gc = chip-chip;
+ u64 address;
+
+ if (!of_have_populated_dt())
+ return;
+
+ address = chip-base ? base + ((u32)chip-base 0xfff) : base + offset;
+ gc-of_node = of_find_matching_node_by_address(NULL,
+ s3c24xx_gpio_dt_match, address);
+ if (!gc-of_node) {
+ pr_info(gpio: device tree node not found for gpio controller
+with base address %08llx\n, address);
+ return;
+ }
+ gc-of_gpio_n_cells = 3;
+ gc-of_xlate = s3c24xx_gpio_xlate;
+}
+#elif defined(CONFIG_PLAT_S3C24XX)
+static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip
*chip,
+u64 base, u64 offset)
Re: [PATCH v2] gpio: samsung: add devicetree init for s3c24xx arches
On 08/28/12 14:55, Heiko Stübner wrote:
Until now the Exynos-SoC was the only Samsung-SoC supporting the GPIOs
via the device tree. This patch implements dt-support for the
s3c24xx arches.
The controllers contain only 3 cells, as the underlying gpio controller
does not support controlling the drive strength on a gpio level.
Tested with the gpio-keys driver on a s3c2416 based machine.
Signed-off-by: Heiko Stuebnerhe...@sntech.de
Reviewed-by: Thomas Abrahamthomas.abra...@linaro.org
Yeah, looks good to me...
Acked-by: Kukjin Kim kgene@samsung.com
BTW, I'm not sure when we can support device tree for S3C24XX :-)
Thanks.
Best regards,
Kgene.
--
Kukjin Kim kgene@samsung.com, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
---
changes since v1:
update bindings documentation to address SoC specific issues
.../devicetree/bindings/gpio/gpio-samsung.txt | 43 +
drivers/gpio/gpio-samsung.c| 63
2 files changed, 106 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
index 5375625..f1e5dfe 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
@@ -39,3 +39,46 @@ Example:
#gpio-cells =4;
gpio-controller;
};
+
+
+Samsung S3C24XX GPIO Controller
+
+Required properties:
+- compatible: Compatible property value should be samsung,s3c24xx-gpio.
+
+- reg: Physical base address of the controller and length of memory mapped
+ region.
+
+- #gpio-cells: Should be 3. The syntax of the gpio specifier used by client
nodes
+ should be the following with values derived from the SoC user manual.
+[phandle of the gpio controller node]
+ [pin number within the gpio controller]
+ [mux function]
+ [flags and pull up/down]
+
+ Values for gpio specifier:
+ - Pin number: depending on the controller a number from 0 up to 15.
+ - Mux function: Depending on the SoC and the gpio bank the gpio can be set
+ as input, output or a special function
+ - Flags and Pull Up/Down: the values to use differ for the individual SoCs
+example S3C2416/S3C2450:
+0 - Pull Up/Down Disabled.
+1 - Pull Down Enabled.
+2 - Pull Up Enabled.
+ Bit 16 (0x0001) - Input is active low.
+ Consult the user manual for the correct values of Mux and Pull Up/Down.
+
+- gpio-controller: Specifies that the node is a gpio controller.
+- #address-cells: should be 1.
+- #size-cells: should be 1.
+
+Example:
+
+ gpa: gpio-controller@5600 {
+ #address-cells =1;
+ #size-cells =1;
+ compatible = samsung,s3c24xx-gpio;
+ reg =0x5600 0x10;
+ #gpio-cells =3;
+ gpio-controller;
+ };
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index ba126cc..54f6663 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -938,6 +938,67 @@ static void __init samsung_gpiolib_add(struct
samsung_gpio_chip *chip)
s3c_gpiolib_track(chip);
}
+#if defined(CONFIG_PLAT_S3C24XX) defined(CONFIG_OF)
+static int s3c24xx_gpio_xlate(struct gpio_chip *gc,
+ const struct of_phandle_args *gpiospec, u32 *flags)
+{
+ unsigned int pin;
+
+ if (WARN_ON(gc-of_gpio_n_cells 3))
+ return -EINVAL;
+
+ if (WARN_ON(gpiospec-args_count gc-of_gpio_n_cells))
+ return -EINVAL;
+
+ if (gpiospec-args[0] gc-ngpio)
+ return -EINVAL;
+
+ pin = gc-base + gpiospec-args[0];
+
+ if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec-args[1])))
+ pr_warn(gpio_xlate: failed to set pin function\n);
+ if (s3c_gpio_setpull(pin, gpiospec-args[2] 0x))
+ pr_warn(gpio_xlate: failed to set pin pull up/down\n);
+
+ if (flags)
+ *flags = gpiospec-args[2] 16;
+
+ return gpiospec-args[0];
+}
+
+static const struct of_device_id s3c24xx_gpio_dt_match[] __initdata = {
+ { .compatible = samsung,s3c24xx-gpio, },
+ {}
+};
+
+static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip
*chip,
+u64 base, u64 offset)
+{
+ struct gpio_chip *gc =chip-chip;
+ u64 address;
+
+ if (!of_have_populated_dt())
+ return;
+
+ address = chip-base ? base + ((u32)chip-base 0xfff) : base + offset;
+ gc-of_node = of_find_matching_node_by_address(NULL,
+ s3c24xx_gpio_dt_match, address);
+ if (!gc-of_node) {
+ pr_info(gpio: device tree node not found for gpio controller
+with base address
Re: [PATCH] ARM: S3C24XX: Add .get_rate callback for camif-upll clock
On 08/28/12 13:58, Sylwester Nawrocki wrote:
On 08/28/2012 12:58 AM, Kukjin Kim wrote:
On 08/27/12 13:12, Sylwester Nawrocki wrote:
Add missing get_rate callback for the camif-upll clock, so frequency
of this clock is properly reported with clk_get_rate().
Signed-off-by: Sylwester Nawrockisylvester.nawro...@gmail.com
---
arch/arm/mach-s3c24xx/clock-s3c2440.c | 14 ++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c
b/arch/arm/mach-s3c24xx/clock-s3c2440.c
index cb2883d..749220f 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2440.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c
@@ -87,6 +87,19 @@ static int s3c2440_camif_upll_setrate(struct clk
*clk, unsigned long rate)
return 0;
}
+static unsigned long s3c2440_camif_upll_getrate(struct clk *clk)
+{
+ unsigned long parent_rate = clk_get_rate(clk-parent);
+ unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
+
+ if (!(camdivn S3C2440_CAMDIVN_CAMCLK_SEL))
+ return parent_rate;
+
+ camdivn= S3C2440_CAMDIVN_CAMCLK_MASK;
+
+ return parent_rate / (camdivn + 1) / 2;
Well, why do we need '/ 2' here?
I simply followed documentation of the camera clock divider register
(CAMDIVN). This is how CAMCLK_SEL and CAMCLK_DIV bit fields are described
there:
CAMDIVN | Bit | Description
--
CAMCLK_SEL | [4] | 0 : Use CAMCLK with UPLL output(CAMCLK=UPLL output)
| | 1 : CAMCLK is divided by CAMCLK_DIV value
-+---+
CAMCLK_DIV | [3:0] | CAMCLK divide factor setting register(0 – 15).
| | Camera clock = UPLL / [(CAMCLK_DIV +1)x2].
| | This bit is valid when CAMCLK_SEL=1.
So, camera clock frequency = parent_rate / ((camdivn + 1) * 2).
This is exactly same as 'parent_rate / ( camdivn + 1) / 2'.
To be 1000% sure I compared frequency values reported from clk_get_rate()
in the driver with values measured with an oscilloscope at the CAMCLKOUT
pin. Everything was as expected (UPLL - 48 MHz, CAMCLKOUT - 12 MHz).
Also, it's easy to confirm correctness of this code by inversing equations
found in function s3c2440_camif_upll_setrate(), i.e.
camdivn= ~(S3C2440_CAMDIVN_CAMCLK_SEL | S3C2440_CAMDIVN_CAMCLK_MASK);
if (rate != parent_rate) {
camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
camdivn |= (((parent_rate / rate) / 2) - 1);
}
__raw_writel(camdivn, S3C2440_CAMDIVN);
--
Looks OK, thanks for your reply :-)
Applied.
Best regards,
Kgene.
--
Kukjin Kim kgene@samsung.com, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
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Re: [PATCH 0/3] Removal of obsolete s3c2410_* GPIO API
On 08/27/12 17:13, Linus Walleij wrote: On Sat, Aug 25, 2012 at 5:20 AM, Sylwester Nawrocki sylvester.nawro...@gmail.com wrote: This short patch series converts remaining users of the s3c24xx SoC specific gpiolib functions to the gpiolib API and finally removes all s3c2410_* functions from drivers/gpio/gpio-samsung.c. I'm fine with this as long as the Samsung maintainer is, so Acked-by: Linus Walleijlinus.wall...@linaro.org Thanks, applied this series with your ack. But I suspect this will be merged through the Samsung SoC tree? Yes, then will be sent to upstream via arm-soc. If any problems, please let me know. Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: Exynos4: Turn off clocks for NAND, OneNAND and TSI controllers
On 08/28/12 01:15, Thomas Abraham wrote:
On 24 August 2012 20:22, Chander Kashyapchander.kash...@linaro.org wrote:
The clocks for NAND, OneNAND and Transport Stream Interface(TSI)
controllers could be either enabled or disabled at boot. To ensure
that these are turned off until used, add them to the list of clocks
to be turned off during boot.
Signed-off-by: Chander Kashyapchander.kash...@linaro.org
---
arch/arm/mach-exynos/clock-exynos4.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mach-exynos/clock-exynos4.c
b/arch/arm/mach-exynos/clock-exynos4.c
index 2f51293..7cc5491 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -501,6 +501,10 @@ static struct clk exynos4_init_clocks_off[] = {
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit= (1 3),
}, {
+ .name = tsi,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit= (1 4),
+ }, {
.name = hsmmc,
.devname= exynos4-sdhci.0,
.parent =exynos4_clk_aclk_133.clk,
@@ -530,6 +534,14 @@ static struct clk exynos4_init_clocks_off[] = {
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit= (1 9),
}, {
+ .name = onenand,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit= (1 15),
+ }, {
+ .name = nfcon,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit= (1 16),
+ }, {
.name = dac,
.devname= s5p-sdo,
.enable = exynos4_clk_ip_tv_ctrl,
--
1.7.9.5
Reviewed-by: Thomas Abrahamthomas.abra...@linaro.org
Applied, thanks.
Best regards,
Kgene.
--
Kukjin Kim kgene@samsung.com, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
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Re: [PATCH] ARM: EXYNOS: Fix incorrect help text
On 08/28/12 01:07, Sachin Kamat wrote: Changed Exynos4 - Exynos5. Signed-off-by: Sachin Kamatsachin.ka...@linaro.org --- arch/arm/mach-exynos/Kconfig |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index b5b4c8c..9369ff7 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -418,8 +418,8 @@ config MACH_EXYNOS5_DT select USE_OF select ARM_AMBA help - Machine support for Samsung Exynos4 machine with device tree enabled. - Select this if a fdt blob is available for the EXYNOS4 SoC based board. + Machine support for Samsung Exynos5 machine with device tree enabled. + Select this if a fdt blob is available for the EXYNOS5 SoC based board. if ARCH_EXYNOS4 Yes, applied. Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] ARM: S3C64XX: Update configuration for WM5102 module on Cragganmore
On 08/23/12 08:20, Mark Brown wrote: On Thu, Aug 23, 2012 at 06:45:19PM +0900, Kukjin Kim wrote: Yeah, actually SoC defconfig in mainline doesn't cover _real_ requirements for (mass) product. But I think, it's time we need to sort out the defconfigs so that we could use them efficiently on product. BTW, if enabling board in defconfig, at least, unexpected build breakages could be detected by testing defconfig before merge for mainline... Right, sure. I guess the main thing I'm saying here is that I don't mind what happens here, it's certainly no problem for me turn them on in the build if that's what people wants. Hmm...I want? :) --- From: Kukjin Kim kgene@samsung.com Subject: [PATCH] ARM: s3c6400_defconfig: enable more boards in defconfig This enables all of s3c64xx boards in the s3c6400_defconfig. In this time, MINI6410, REAL6410, and WLF_CRAGG_6410 are added in the defconfig. Cc: Darius Augulis augulis.dar...@gmail.com Cc: Mark Brown broo...@opensource.wolfsonmicro.com Signed-off-by: Kukjin Kim kgene@samsung.com --- arch/arm/configs/s3c6400_defconfig |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/arm/configs/s3c6400_defconfig b/arch/arm/configs/s3c6400_defconfig index ba6a515..3a186d6 100644 --- a/arch/arm/configs/s3c6400_defconfig +++ b/arch/arm/configs/s3c6400_defconfig @@ -9,11 +9,14 @@ CONFIG_ARCH_S3C64XX=y CONFIG_S3C_BOOT_ERROR_RESET=y CONFIG_MACH_SMDK6400=y CONFIG_MACH_ANW6410=y +CONFIG_MACH_MINI6410=y +CONFIG_MACH_REAL6410=y CONFIG_MACH_SMDK6410=y CONFIG_MACH_NCP=y CONFIG_MACH_HMT=y CONFIG_MACH_SMARTQ5=y CONFIG_MACH_SMARTQ7=y +CONFIG_MACH_WLF_CRAGG_6410=y CONFIG_CPU_32v6K=y CONFIG_AEABI=y CONFIG_CMDLINE=console=ttySAC0,115200 root=/dev/ram init=/linuxrc initrd=0x5100,6M ramdisk_size=6144 -- Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] ARM: EXYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx
On 08/28/12 03:06, Tomasz Figa wrote: The GPEx gpios are specific to Exynos4210 and do not exist on Exynos4x12. Redefine them to use the exact SoC name. Based on ARM: EXYYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx by Joonyoung Shim, see: http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/100738.html Signed-off-by: Tomasz Figat.f...@samsung.com --- arch/arm/mach-exynos/include/mach/gpio.h | 32 +++--- arch/arm/mach-exynos/mach-nuri.c | 16 +++ arch/arm/mach-exynos/mach-origen.c | 6 +++--- arch/arm/mach-exynos/mach-trats.c | 4 ++-- arch/arm/mach-exynos/mach-universal_c210.c | 32 +++--- arch/arm/mach-exynos/setup-fimc.c | 4 ++-- drivers/gpio/gpio-samsung.c| 20 +-- 7 files changed, 57 insertions(+), 57 deletions(-) diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h index eb24f1e..21c9bf1 100644 --- a/arch/arm/mach-exynos/include/mach/gpio.h +++ b/arch/arm/mach-exynos/include/mach/gpio.h @@ -26,11 +26,11 @@ #define EXYNOS4_GPIO_C1_NR(5) #define EXYNOS4_GPIO_D0_NR(4) #define EXYNOS4_GPIO_D1_NR(4) -#define EXYNOS4_GPIO_E0_NR (5) -#define EXYNOS4_GPIO_E1_NR (8) -#define EXYNOS4_GPIO_E2_NR (6) -#define EXYNOS4_GPIO_E3_NR (8) -#define EXYNOS4_GPIO_E4_NR (8) +#define EXYNOS4210_GPIO_E0_NR (5) +#define EXYNOS4210_GPIO_E1_NR (8) +#define EXYNOS4210_GPIO_E2_NR (6) +#define EXYNOS4210_GPIO_E3_NR (8) +#define EXYNOS4210_GPIO_E4_NR (8) Please see my comments on Joonyoung Shim's previous patch... http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/101522.html [...] Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: EXYNOS: Use non-secure MDMA1
On 08/28/12 04:08, Tomasz Figa wrote:
Using secure MDMA1 on TrustZone-enabled boards causes early boot crash,
so use non-secure instead.
Signed-off-by: Tomasz Figat.f...@samsung.com
Signed-off-by: Kyungmin Parkkyungmin.p...@samsung.com
---
arch/arm/mach-exynos/dma.c | 2 +-
arch/arm/mach-exynos/include/mach/map.h | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index f60b66d..8858df5 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -261,7 +261,7 @@ static struct dma_pl330_platdata exynos_mdma1_pdata = {
};
static AMBA_AHB_DEVICE(exynos_mdma1, dma-pl330.2, 0x00041330,
- EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1},exynos_mdma1_pdata);
+ EXYNOS4_PA_NS_MDMA1, {EXYNOS4_IRQ_MDMA1},exynos_mdma1_pdata);
static int __init exynos_dma_init(void)
{
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-
exynos/include/mach/map.h
index 51943f2..5df5910 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -89,7 +89,8 @@
#define EXYNOS4_PA_L2CC 0x10502000
#define EXYNOS4_PA_MDMA0 0x1081
-#define EXYNOS4_PA_MDMA1 0x1284
+#define EXYNOS4_PA_S_MDMA1 0x1284
+#define EXYNOS4_PA_NS_MDMA10x1285
#define EXYNOS4_PA_PDMA0 0x1268
#define EXYNOS4_PA_PDMA1 0x1269
#define EXYNOS5_PA_MDMA0 0x1080
Cc'ed Boojin Kim.
Well, just fix the address is enough like exynos5 stuff? I don't have
any idea why we need secure mdma and non-secure mdma both here...
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index c72b675..c941053 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -89,7 +89,7 @@
#define EXYNOS4_PA_L2CC0x10502000
#define EXYNOS4_PA_MDMA0 0x1081
-#define EXYNOS4_PA_MDMA1 0x1284
+#define EXYNOS4_PA_MDMA1 0x1285
#define EXYNOS4_PA_PDMA0 0x1268
#define EXYNOS4_PA_PDMA1 0x1269
#define EXYNOS5_PA_MDMA0 0x1080
--
Thanks.
Best regards,
Kgene.
--
Kukjin Kim kgene@samsung.com, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
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Re: [PATCH 1/3] ARM: EXYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx
On 8/29/12, Kukjin Kim kgene@samsung.com wrote:
On 08/28/12 03:06, Tomasz Figa wrote:
The GPEx gpios are specific to Exynos4210 and do not exist on Exynos4x12.
Redefine them to use the exact SoC name.
Based on ARM: EXYYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx by
Joonyoung Shim, see:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/100738.html
Signed-off-by: Tomasz Figat.f...@samsung.com
---
arch/arm/mach-exynos/include/mach/gpio.h | 32
+++---
arch/arm/mach-exynos/mach-nuri.c | 16 +++
arch/arm/mach-exynos/mach-origen.c | 6 +++---
arch/arm/mach-exynos/mach-trats.c | 4 ++--
arch/arm/mach-exynos/mach-universal_c210.c | 32
+++---
arch/arm/mach-exynos/setup-fimc.c | 4 ++--
drivers/gpio/gpio-samsung.c| 20 +--
7 files changed, 57 insertions(+), 57 deletions(-)
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h
b/arch/arm/mach-exynos/include/mach/gpio.h
index eb24f1e..21c9bf1 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -26,11 +26,11 @@
#define EXYNOS4_GPIO_C1_NR (5)
#define EXYNOS4_GPIO_D0_NR (4)
#define EXYNOS4_GPIO_D1_NR (4)
-#define EXYNOS4_GPIO_E0_NR (5)
-#define EXYNOS4_GPIO_E1_NR (8)
-#define EXYNOS4_GPIO_E2_NR (6)
-#define EXYNOS4_GPIO_E3_NR (8)
-#define EXYNOS4_GPIO_E4_NR (8)
+#define EXYNOS4210_GPIO_E0_NR (5)
+#define EXYNOS4210_GPIO_E1_NR (8)
+#define EXYNOS4210_GPIO_E2_NR (6)
+#define EXYNOS4210_GPIO_E3_NR (8)
+#define EXYNOS4210_GPIO_E4_NR (8)
Please see my comments on Joonyoung Shim's previous patch...
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/101522.html
It's perference issue. some person like this style. others doesn't.
Moreever vender, System LSI, provided codes have whole different style.
It lists up whole gpios for each SoCs.
EXYNOS4210_{A0, Z}
EXYNOS4412_{A0, V4}
EXYNOS5250_{A0, Z}
anyway, just remain it as broken, and try to use pinctl as Thomas mentioned.
Thank you,
Kyungmin Park
[...]
Thanks.
Best regards,
Kgene.
--
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SW Solution Development Team, Samsung Electronics Co., Ltd.
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Re: [PATCH] ARM: EXYNOS: Use non-secure MDMA1
On 8/29/12, Kukjin Kim kgene@samsung.com wrote:
On 08/28/12 04:08, Tomasz Figa wrote:
Using secure MDMA1 on TrustZone-enabled boards causes early boot crash,
so use non-secure instead.
Signed-off-by: Tomasz Figat.f...@samsung.com
Signed-off-by: Kyungmin Parkkyungmin.p...@samsung.com
---
arch/arm/mach-exynos/dma.c | 2 +-
arch/arm/mach-exynos/include/mach/map.h | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index f60b66d..8858df5 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -261,7 +261,7 @@ static struct dma_pl330_platdata exynos_mdma1_pdata =
{
};
static AMBA_AHB_DEVICE(exynos_mdma1, dma-pl330.2, 0x00041330,
-EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1},exynos_mdma1_pdata);
+EXYNOS4_PA_NS_MDMA1, {EXYNOS4_IRQ_MDMA1},exynos_mdma1_pdata);
static int __init exynos_dma_init(void)
{
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-
exynos/include/mach/map.h
index 51943f2..5df5910 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -89,7 +89,8 @@
#define EXYNOS4_PA_L2CC0x10502000
#define EXYNOS4_PA_MDMA0 0x1081
-#define EXYNOS4_PA_MDMA10x1284
+#define EXYNOS4_PA_S_MDMA1 0x1284
+#define EXYNOS4_PA_NS_MDMA1 0x1285
#define EXYNOS4_PA_PDMA0 0x1268
#define EXYNOS4_PA_PDMA1 0x1269
#define EXYNOS5_PA_MDMA0 0x1080
Cc'ed Boojin Kim.
Well, just fix the address is enough like exynos5 stuff? I don't have
any idea why we need secure mdma and non-secure mdma both here...
Did you see the datasheet and your team codes?
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index c72b675..c941053 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -89,7 +89,7 @@
#define EXYNOS4_PA_L2CC0x10502000
#define EXYNOS4_PA_MDMA00x1081
-#define EXYNOS4_PA_MDMA1 0x1284
+#define EXYNOS4_PA_MDMA1 0x1285
#define EXYNOS4_PA_PDMA00x1268
#define EXYNOS4_PA_PDMA10x1269
#define EXYNOS5_PA_MDMA00x1080
--
Thanks.
Best regards,
Kgene.
--
Kukjin Kim kgene@samsung.com, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
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[PATCH v3 0/4] Add support to enable ARM PMU for EXYNOS
This patchset fixes irq numbers of ARM Performance Monitoring unit and enable it for Perf(Performance Counter) on the exynos 4 and 5. The exynos4 and 5 use 2 more cpu cores which has its own pmu. The exynos uses combiner-irq type for arm-pmu. Especially, the exynos4412 has 4 extra combined irq groups. So, we need to change a max combiner number. To enable perf, we need also to implement a set_irq_affinity function about the combiner-irq. After applying this patch, we can use the perf for the exynos machine. Changes from v2: - Convert to dt binding of exynos5250 Changes from v1: - Split arm-pmu init of exynos from plat-samsung - Correct combined irqs of exynos4412 - Use soc_is_xxx function instead of CONFIG_XXX to identify dynamically Chanho Park (4): ARM: EXYNOS: Add set_irq_affinity function for combiner_irq ARM: EXYNOS: Correct combined IRQs for exynos4412 ARM: EXYNOS: Enable PMUs for exynos4 ARM: EXYNOS: Add arm-pmu DT binding for exynos5250 arch/arm/boot/dts/exynos5250.dtsi|6 ++ arch/arm/mach-exynos/common.c| 106 ++ arch/arm/mach-exynos/include/mach/irqs.h | 10 ++- arch/arm/plat-samsung/devs.c |2 +- 4 files changed, 109 insertions(+), 15 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 1/4] ARM: EXYNOS: Add set_irq_affinity function for combiner_irq
This patch adds set_irq_affinity function for combiner_irq. We need this
function to enable a arm-pmu because the pmu of exynos has combined type irqs.
Signed-off-by: Chanho Park chanho61.p...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/common.c | 30 +-
1 file changed, 25 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 4eb39cd..f194bbc 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -405,6 +405,7 @@ struct combiner_chip_data {
unsigned int irq_offset;
unsigned int irq_mask;
void __iomem *base;
+ unsigned int parent_irq;
};
static struct irq_domain *combiner_irq_domain;
@@ -461,10 +462,28 @@ static void combiner_handle_cascade_irq(unsigned int irq,
struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
+#ifdef CONFIG_SMP
+static int combiner_set_affinity(struct irq_data *d,
+const struct cpumask *mask_val, bool force)
+{
+ struct combiner_chip_data *chip_data = irq_data_get_irq_chip_data(d);
+ struct irq_chip *chip = irq_get_chip(chip_data-parent_irq);
+ struct irq_data *data = irq_get_irq_data(chip_data-parent_irq);
+
+ if (chip chip-irq_set_affinity)
+ return chip-irq_set_affinity(data, mask_val, force);
+ else
+ return -EINVAL;
+}
+#endif
+
static struct irq_chip combiner_chip = {
- .name = COMBINER,
- .irq_mask = combiner_mask_irq,
- .irq_unmask = combiner_unmask_irq,
+ .name = COMBINER,
+ .irq_mask = combiner_mask_irq,
+ .irq_unmask = combiner_unmask_irq,
+#ifdef CONFIG_SMP
+ .irq_set_affinity = combiner_set_affinity,
+#endif
};
static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int
irq)
@@ -484,12 +503,13 @@ static void __init combiner_cascade_irq(unsigned int
combiner_nr, unsigned int i
}
static void __init combiner_init_one(unsigned int combiner_nr,
-void __iomem *base)
+void __iomem *base, unsigned int irq)
{
combiner_data[combiner_nr].base = base;
combiner_data[combiner_nr].irq_offset = irq_find_mapping(
combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
combiner_data[combiner_nr].irq_mask = 0xff ((combiner_nr % 4) 3);
+ combiner_data[combiner_nr].parent_irq = irq;
/* Disable all interrupts */
__raw_writel(combiner_data[combiner_nr].irq_mask,
@@ -573,12 +593,12 @@ static void __init combiner_init(void __iomem
*combiner_base,
}
for (i = 0; i max_nr; i++) {
- combiner_init_one(i, combiner_base + (i 2) * 0x10);
irq = IRQ_SPI(i);
#ifdef CONFIG_OF
if (np)
irq = irq_of_parse_and_map(np, i);
#endif
+ combiner_init_one(i, combiner_base + (i 2) * 0x10, irq);
combiner_cascade_irq(i, irq);
}
}
--
1.7.9.5
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[PATCH v3 2/4] ARM: EXYNOS: Correct combined IRQs for exynos4412
This patch corrects combined IRQs for exynos4412 platform. The exynos4412 has
four extra combined irq group. Each irq is mapped to IRQ_SPI(xx). Unfortunately,
extra combined IRQs isn't sequential. So, we need to map the irq manually.
Signed-off-by: Chanho Park chanho61.p...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/common.c| 31 --
arch/arm/mach-exynos/include/mach/irqs.h |2 +-
2 files changed, 26 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index f194bbc..be61564 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -560,23 +560,39 @@ static struct irq_domain_ops combiner_irq_domain_ops = {
.map= combiner_irq_domain_map,
};
+static unsigned int get_combiner_extra_irq(int group)
+{
+ switch (group) {
+ case 16:
+ return IRQ_SPI(107);
+ case 17:
+ return IRQ_SPI(108);
+ case 18:
+ return IRQ_SPI(48);
+ case 19:
+ return IRQ_SPI(42);
+ default:
+ return 0;
+ }
+}
+
static void __init combiner_init(void __iomem *combiner_base,
struct device_node *np)
{
int i, irq, irq_base;
unsigned int max_nr, nr_irq;
+ max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
+ EXYNOS4_MAX_COMBINER_NR;
+
if (np) {
if (of_property_read_u32(np, samsung,combiner-nr, max_nr)) {
pr_warning(%s: number of combiners not specified,
setting default as %d.\n,
- __func__, EXYNOS4_MAX_COMBINER_NR);
- max_nr = EXYNOS4_MAX_COMBINER_NR;
+ __func__, max_nr);
}
- } else {
- max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
- EXYNOS4_MAX_COMBINER_NR;
}
+
nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
@@ -593,7 +609,10 @@ static void __init combiner_init(void __iomem
*combiner_base,
}
for (i = 0; i max_nr; i++) {
- irq = IRQ_SPI(i);
+ if (i 16 || soc_is_exynos5250())
+ irq = IRQ_SPI(i);
+ else
+ irq = get_combiner_extra_irq(i);
#ifdef CONFIG_OF
if (np)
irq = irq_of_parse_and_map(np, i);
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h
b/arch/arm/mach-exynos/include/mach/irqs.h
index 35bced6..357ed7f 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -165,7 +165,7 @@
#define EXYNOS4_IRQ_FIMD0_VSYNCCOMBINER_IRQ(11, 1)
#define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
-#define EXYNOS4_MAX_COMBINER_NR16
+#define EXYNOS4_MAX_COMBINER_NR20
#define EXYNOS4_IRQ_GPIO1_NR_GROUPS16
#define EXYNOS4_IRQ_GPIO2_NR_GROUPS9
--
1.7.9.5
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[PATCH v3 3/4] ARM: EXYNOS: Enable PMUs for exynos4
This patch define irq numbers of ARM performance monitoring unit for exynos4.
The number of CPU cores and PMU irq numbers are vary according to soc types.
So we need to identify each soc type using soc_is_xxx function and define the
pmu irqs dynamically. In case of exynos4412, there are 4 cpu cores and pmus.
Signed-off-by: Chanho Park chanho61.p...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/common.c| 45 ++
arch/arm/mach-exynos/include/mach/irqs.h |8 --
arch/arm/plat-samsung/devs.c |2 +-
3 files changed, 52 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index be61564..24b78bd 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -30,11 +30,13 @@
#include asm/mach/map.h
#include asm/mach/irq.h
#include asm/cacheflush.h
+#include asm/pmu.h
#include mach/regs-irq.h
#include mach/regs-pmu.h
#include mach/regs-gpio.h
#include mach/pmu.h
+#include mach/irqs.h
#include plat/cpu.h
#include plat/clock.h
@@ -1056,3 +1058,46 @@ static int __init exynos_init_irq_eint(void)
return 0;
}
arch_initcall(exynos_init_irq_eint);
+
+#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
+static struct resource exynos42xx_pmu_resource[] = {
+ DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
+ DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
+};
+
+static struct platform_device exynos42xx_device_pmu = {
+ .name = arm-pmu,
+ .num_resources = ARRAY_SIZE(exynos42xx_pmu_resource),
+ .resource = exynos42xx_pmu_resource,
+};
+#endif
+
+#if defined(CONFIG_SOC_EXYNOS4412)
+static struct resource exynos44xx_pmu_resource[] = {
+ DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
+ DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
+ DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
+ DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
+};
+
+static struct platform_device exynos44xx_device_pmu = {
+ .name = arm-pmu,
+ .num_resources = ARRAY_SIZE(exynos44xx_pmu_resource),
+ .resource = exynos44xx_pmu_resource,
+};
+#endif
+
+static int __init exynos_armpmu_init(void)
+{
+#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
+ if (soc_is_exynos4210() || soc_is_exynos4212())
+ platform_device_register(exynos42xx_device_pmu);
+#endif
+#if defined(CONFIG_SOC_EXYNOS4412)
+ if (soc_is_exynos4412())
+ platform_device_register(exynos44xx_device_pmu);
+#endif
+
+ return 0;
+}
+arch_initcall(exynos_armpmu_init);
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h
b/arch/arm/mach-exynos/include/mach/irqs.h
index 357ed7f..5e75b19 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -128,7 +128,7 @@
#define EXYNOS4_IRQ_ADC1 IRQ_SPI(107)
#define EXYNOS4_IRQ_PEN1 IRQ_SPI(108)
#define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109)
-#define EXYNOS4_IRQ_PMUIRQ_SPI(110)
+#define EXYNOS4_IRQ_POWER_PMU IRQ_SPI(110)
#define EXYNOS4_IRQ_GPSIRQ_SPI(111)
#define EXYNOS4_IRQ_INTFEEDCTRL_SSSIRQ_SPI(112)
#define EXYNOS4_IRQ_SLIMBUSIRQ_SPI(113)
@@ -136,6 +136,11 @@
#define EXYNOS4_IRQ_TSIIRQ_SPI(115)
#define EXYNOS4_IRQ_SATA IRQ_SPI(116)
+#define EXYNOS4_IRQ_PMUCOMBINER_IRQ(2, 2)
+#define EXYNOS4_IRQ_PMU_CPU1 COMBINER_IRQ(3, 2)
+#define EXYNOS4_IRQ_PMU_CPU2 COMBINER_IRQ(18, 2)
+#define EXYNOS4_IRQ_PMU_CPU3 COMBINER_IRQ(19, 2)
+
#define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
#define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
#define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
@@ -230,7 +235,6 @@
#define IRQ_TC EXYNOS4_IRQ_PEN0
#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD
-#define IRQ_PMUEXYNOS4_IRQ_PMU
#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO
#define IRQ_FIMD0_VSYNCEXYNOS4_IRQ_FIMD0_VSYNC
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index fc49f3d..3b44dad 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -1125,7 +1125,7 @@ struct platform_device s5p_device_onenand = {
/* PMU */
-#ifdef CONFIG_PLAT_S5P
+#if defined(CONFIG_PLAT_S5P) !defined(CONFIG_ARCH_EXYNOS)
static struct resource s5p_pmu_resource[] = {
DEFINE_RES_IRQ(IRQ_PMU)
};
--
1.7.9.5
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[PATCH v3 4/4] ARM: EXYNOS: Add arm-pmu DT binding for exynos5250
This patch enables arm-pmu to bind device tree for exynos5250. The exynos5250
has two pmus which have combiner irq type.
Signed-off-by: Chanho Park chanho61.p...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos5250.dtsi |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 004aaa8..45746cbf 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -52,6 +52,12 @@
0 28 0, 0 29 0, 0 30 0, 0 31 0;
};
+ pmu {
+ compatible = arm,cortex-a15-pmu;
+ interrupt-parent = combiner;
+ interrupts = 1 2, 22 4;
+ };
+
watchdog {
compatible = samsung,s3c2410-wdt;
reg = 0x101D 0x100;
--
1.7.9.5
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Re: [PATCH v3 3/4] ARM: EXYNOS: Enable PMUs for exynos4
Hi Chanho,
On 29 August 2012 06:44, Chanho Park chanho61.p...@samsung.com wrote:
This patch define irq numbers of ARM performance monitoring unit for exynos4.
The number of CPU cores and PMU irq numbers are vary according to soc types.
So we need to identify each soc type using soc_is_xxx function and define the
pmu irqs dynamically. In case of exynos4412, there are 4 cpu cores and pmus.
Signed-off-by: Chanho Park chanho61.p...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/common.c| 45
++
arch/arm/mach-exynos/include/mach/irqs.h |8 --
arch/arm/plat-samsung/devs.c |2 +-
3 files changed, 52 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index be61564..24b78bd 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -30,11 +30,13 @@
#include asm/mach/map.h
#include asm/mach/irq.h
#include asm/cacheflush.h
+#include asm/pmu.h
#include mach/regs-irq.h
#include mach/regs-pmu.h
#include mach/regs-gpio.h
#include mach/pmu.h
+#include mach/irqs.h
#include plat/cpu.h
#include plat/clock.h
@@ -1056,3 +1058,46 @@ static int __init exynos_init_irq_eint(void)
return 0;
}
arch_initcall(exynos_init_irq_eint);
+
+#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
+static struct resource exynos42xx_pmu_resource[] = {
+ DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
+ DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
+};
+
+static struct platform_device exynos42xx_device_pmu = {
+ .name = arm-pmu,
+ .num_resources = ARRAY_SIZE(exynos42xx_pmu_resource),
+ .resource = exynos42xx_pmu_resource,
+};
+#endif
+
+#if defined(CONFIG_SOC_EXYNOS4412)
+static struct resource exynos44xx_pmu_resource[] = {
+ DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
+ DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
+ DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
+ DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
+};
+
+static struct platform_device exynos44xx_device_pmu = {
+ .name = arm-pmu,
+ .num_resources = ARRAY_SIZE(exynos44xx_pmu_resource),
+ .resource = exynos44xx_pmu_resource,
+};
+#endif
+
+static int __init exynos_armpmu_init(void)
+{
+#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
+ if (soc_is_exynos4210() || soc_is_exynos4212())
+ platform_device_register(exynos42xx_device_pmu);
+#endif
+#if defined(CONFIG_SOC_EXYNOS4412)
+ if (soc_is_exynos4412())
+ platform_device_register(exynos44xx_device_pmu);
+#endif
Do we need both compile time and run-time checks here?
+
+ return 0;
+}
+arch_initcall(exynos_armpmu_init);
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h
b/arch/arm/mach-exynos/include/mach/irqs.h
index 357ed7f..5e75b19 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -128,7 +128,7 @@
#define EXYNOS4_IRQ_ADC1 IRQ_SPI(107)
#define EXYNOS4_IRQ_PEN1 IRQ_SPI(108)
#define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109)
-#define EXYNOS4_IRQ_PMUIRQ_SPI(110)
+#define EXYNOS4_IRQ_POWER_PMU IRQ_SPI(110)
#define EXYNOS4_IRQ_GPSIRQ_SPI(111)
#define EXYNOS4_IRQ_INTFEEDCTRL_SSSIRQ_SPI(112)
#define EXYNOS4_IRQ_SLIMBUSIRQ_SPI(113)
@@ -136,6 +136,11 @@
#define EXYNOS4_IRQ_TSIIRQ_SPI(115)
#define EXYNOS4_IRQ_SATA IRQ_SPI(116)
+#define EXYNOS4_IRQ_PMUCOMBINER_IRQ(2, 2)
+#define EXYNOS4_IRQ_PMU_CPU1 COMBINER_IRQ(3, 2)
+#define EXYNOS4_IRQ_PMU_CPU2 COMBINER_IRQ(18, 2)
+#define EXYNOS4_IRQ_PMU_CPU3 COMBINER_IRQ(19, 2)
+
#define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
#define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
#define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
@@ -230,7 +235,6 @@
#define IRQ_TC EXYNOS4_IRQ_PEN0
#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD
-#define IRQ_PMUEXYNOS4_IRQ_PMU
#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO
#define IRQ_FIMD0_VSYNCEXYNOS4_IRQ_FIMD0_VSYNC
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index fc49f3d..3b44dad 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -1125,7 +1125,7 @@ struct platform_device s5p_device_onenand = {
/* PMU */
-#ifdef CONFIG_PLAT_S5P
+#if defined(CONFIG_PLAT_S5P) !defined(CONFIG_ARCH_EXYNOS)
static struct resource s5p_pmu_resource[] = {
DEFINE_RES_IRQ(IRQ_PMU)
};
--
1.7.9.5
--
With warm regards,
Sachin
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RE: [PATCH v3 3/4] ARM: EXYNOS: Enable PMUs for exynos4
-Original Message-
From: Sachin Kamat [mailto:sachin.ka...@linaro.org]
Sent: Wednesday, August 29, 2012 12:39 PM
To: Chanho Park
Cc: kgene@samsung.com; linux-arm-ker...@lists.infradead.org; linux-
samsung-...@vger.kernel.org; li...@arm.linux.org.uk;
will.dea...@arm.com; thomas.abra...@linaro.org; Kyungmin Park
Subject: Re: [PATCH v3 3/4] ARM: EXYNOS: Enable PMUs for exynos4
Hi Chanho,
On 29 August 2012 06:44, Chanho Park chanho61.p...@samsung.com
wrote:
This patch define irq numbers of ARM performance monitoring unit for
exynos4.
The number of CPU cores and PMU irq numbers are vary according to soc
types.
So we need to identify each soc type using soc_is_xxx function and
define the pmu irqs dynamically. In case of exynos4412, there are 4 cpu
cores and pmus.
Signed-off-by: Chanho Park chanho61.p...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/common.c| 45
++
arch/arm/mach-exynos/include/mach/irqs.h |8 --
arch/arm/plat-samsung/devs.c |2 +-
3 files changed, 52 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos/common.c
b/arch/arm/mach-exynos/common.c index be61564..24b78bd 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -30,11 +30,13 @@
#include asm/mach/map.h
#include asm/mach/irq.h
#include asm/cacheflush.h
+#include asm/pmu.h
#include mach/regs-irq.h
#include mach/regs-pmu.h
#include mach/regs-gpio.h
#include mach/pmu.h
+#include mach/irqs.h
#include plat/cpu.h
#include plat/clock.h
@@ -1056,3 +1058,46 @@ static int __init exynos_init_irq_eint(void)
return 0;
}
arch_initcall(exynos_init_irq_eint);
+
+#if defined(CONFIG_CPU_EXYNOS4210) ||
defined(CONFIG_SOC_EXYNOS4212)
+static struct resource exynos42xx_pmu_resource[] = {
+ DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
+ DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
+};
+
+static struct platform_device exynos42xx_device_pmu = {
+ .name = arm-pmu,
+ .num_resources = ARRAY_SIZE(exynos42xx_pmu_resource),
+ .resource = exynos42xx_pmu_resource,
+};
+#endif
+
+#if defined(CONFIG_SOC_EXYNOS4412)
+static struct resource exynos44xx_pmu_resource[] = {
+ DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
+ DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
+ DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
+ DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
+};
+
+static struct platform_device exynos44xx_device_pmu = {
+ .name = arm-pmu,
+ .num_resources = ARRAY_SIZE(exynos44xx_pmu_resource),
+ .resource = exynos44xx_pmu_resource,
+};
+#endif
+
+static int __init exynos_armpmu_init(void) { #if
+defined(CONFIG_CPU_EXYNOS4210) ||
defined(CONFIG_SOC_EXYNOS4212)
+ if (soc_is_exynos4210() || soc_is_exynos4212())
+ platform_device_register(exynos42xx_device_pmu);
+#endif
+#if defined(CONFIG_SOC_EXYNOS4412)
+ if (soc_is_exynos4412())
+ platform_device_register(exynos44xx_device_pmu);
+#endif
Do we need both compile time and run-time checks here?
I think we can reduce code size and avoid unnecessary comparison using compile
time check if
turn off these kernel configurations.
And runtime check is helpful when turned on all SoC types in the kernel
configurations.
Best regards,
Chanho Park
+
+ return 0;
+}
+arch_initcall(exynos_armpmu_init);
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h
b/arch/arm/mach-exynos/include/mach/irqs.h
index 357ed7f..5e75b19 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -128,7 +128,7 @@
#define EXYNOS4_IRQ_ADC1 IRQ_SPI(107)
#define EXYNOS4_IRQ_PEN1 IRQ_SPI(108)
#define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109)
-#define EXYNOS4_IRQ_PMUIRQ_SPI(110)
+#define EXYNOS4_IRQ_POWER_PMU IRQ_SPI(110)
#define EXYNOS4_IRQ_GPSIRQ_SPI(111)
#define EXYNOS4_IRQ_INTFEEDCTRL_SSSIRQ_SPI(112)
#define EXYNOS4_IRQ_SLIMBUSIRQ_SPI(113)
@@ -136,6 +136,11 @@
#define EXYNOS4_IRQ_TSIIRQ_SPI(115)
#define EXYNOS4_IRQ_SATA IRQ_SPI(116)
+#define EXYNOS4_IRQ_PMUCOMBINER_IRQ(2, 2)
+#define EXYNOS4_IRQ_PMU_CPU1 COMBINER_IRQ(3, 2)
+#define EXYNOS4_IRQ_PMU_CPU2 COMBINER_IRQ(18, 2)
+#define EXYNOS4_IRQ_PMU_CPU3 COMBINER_IRQ(19, 2)
+
#define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
#define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
#define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
@@ -230,7 +235,6 @@
#define IRQ_TC EXYNOS4_IRQ_PEN0
#define IRQ_KEYPAD
[PATCH 0/2] ARM: EXYNOS: Set the capability of pdm0 and pdm1 as DMA_PRIVATE
DMA clients pdma0 and pdma1 are internal to the SoC and are used only by dedicated peripherals. Since they cannot be used for generic purpose, their capability should be set as DMA_PRIVATE. The patches are rebased on top of v3.6-rc3. Tushar Behera (2): ARM: EXYNOS: Set the capability of pdm0 and pdm1 as DMA_PRIVATE DMA: PL330: Set the capability of pdm0 and pdm1 as DMA_PRIVATE arch/arm/mach-exynos/dma.c |2 ++ drivers/dma/pl330.c|1 + 2 files changed, 3 insertions(+), 0 deletions(-) -- 1.7.4.1 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] ARM: EXYNOS: Set the capability of pdm0 and pdm1 as DMA_PRIVATE
DMA clients pdma0 and pdma1 are internal to the SoC and are used only by dedicated peripherals. Since they cannot be used for generic purpose, their capability should be set as DMA_PRIVATE. CC: Kukjin Kim kgene@samsung.com Signed-off-by: Tushar Behera tushar.beh...@linaro.org --- arch/arm/mach-exynos/dma.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c index f60b66d..21d568b 100644 --- a/arch/arm/mach-exynos/dma.c +++ b/arch/arm/mach-exynos/dma.c @@ -303,10 +303,12 @@ static int __init exynos_dma_init(void) dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask); dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask); + dma_cap_set(DMA_PRIVATE, exynos_pdma0_pdata.cap_mask); amba_device_register(exynos_pdma0_device, iomem_resource); dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask); dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask); + dma_cap_set(DMA_PRIVATE, exynos_pdma1_pdata.cap_mask); amba_device_register(exynos_pdma1_device, iomem_resource); dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask); -- 1.7.4.1 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] DMA: PL330: Set the capability of pdm0 and pdm1 as DMA_PRIVATE
DMA clients pdma0 and pdma1 are internal to the SoC and are used only
by dedicated peripherals. Since they cannot be used for generic
purpose, their capability should be set as DMA_PRIVATE.
CC: Vinod Koul vinod.k...@intel.com
Signed-off-by: Tushar Behera tushar.beh...@linaro.org
---
drivers/dma/pl330.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index e4feba6..600ea5e 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -2954,6 +2954,7 @@ pl330_probe(struct amba_device *adev, const struct
amba_id *id)
if (pi-pcfg.num_peri) {
dma_cap_set(DMA_SLAVE, pd-cap_mask);
dma_cap_set(DMA_CYCLIC, pd-cap_mask);
+ dma_cap_set(DMA_PRIVATE, pd-cap_mask);
}
}
--
1.7.4.1
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