Re: [PATCH V4 2/2] video: drm: exynos: Add device tree support
Hi 2012/9/7 Leela Krishna Amudala l.kris...@samsung.com: Hi, On Thu, Sep 6, 2012 at 4:35 PM, Sylwester Nawrocki s.nawro...@samsung.com wrote: Hi, On 09/06/2012 09:21 AM, InKi Dae wrote: +Required properties: + - compatible: Should be samsung,exynos5-fimd or samsung,exynos4-fb for Doesn't better to use single word? fimd or fb?. I think 'fb' is used for framebuffer historically. but now it's used both fb and drm, so fimd is neutral and architecture specific. To do this, Modify arch-exynos first and update it at each drivers it properly. Thank you, Kyungmin Park I agree with Kyungmin but I'd like to use as is. the reason we used 'exynos4-fb' as device name, is for that it uses fimd driver's platform device commonly and gets fimd clock. so I think that dts file should be defined with hardware specific name but not driver name such as 'exynos4-fb'. but with this, we can't get fimd clock with device's name because 'exynos4-fb' is used as device name of fimd clock. so to use 'exynos4-fimd', we should modify the device name of fimd clock from 'exynos4-fb' to 'exynos4-fimd' and also ids definitions of s3c-fb and drm fimd driver. so my conclusion is that it merges this I think it's good moment to put those things in order, i.e. use uniform 'compatible' names: samsung,exynos4-fimd, samsung,exynos5-fimd. Platform device names are separate issue, but could perhaps be unified at this time as well. Yes, Platform device name is independent of compatible string. Will change the compatible string to samsung,exynos4-fimd and will keep the device name as exynos4-fb for now. Will change the platform device names to exynosX-fimd later. I'm not sure that clk_get is worked well with this change. I think, when driver called clk_get(), first of all, it tries to get a clk from the registered list of clock providers in the dts file and next in legacy way. but now legacy way(needing clock name and device' name) would be failed if the dts file has no the list because platform device's name differs from device name of clock. so I think we should change device name of clock and also ids of related drivers for compatibility with non-dt. for this, we need some patch sets, changing arch/arm/mach-exynos/common.c and changing arch/arm/mach-exynos/clock-exynos4/5.c and changing s3c-fb.c and last this patch. if there are no other opinions, I'd like to merge this patch set(v5) and next we can update others(maybe common.c, clock-exynos4/5.c and s3c-fb.c) later. Thanks. Inki Dae patch set as is and then let's modify related things later. any opinions, welcome~ anytime. Thanks. Inki Dae -- Regards, Sylwester -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html ___ dri-devel mailing list dri-de...@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: SAMSUNG: Use spin_lock_{irqsave,irqrestore} in clk_set_rate
The spinlock clocks_lock can be held during ISR, hence it is not safe to
hold that lock with disabling interrupts.
It fixes following potential deadlock.
=
[ INFO: possible irq lock inversion dependency detected ]
3.6.0-rc4+ #2 Not tainted
-
swapper/0/1 just changed the state of lock:
((host-lock)-rlock){-.}, at: [c027fb0d] sdhci_irq+0x15/0x564
but this lock took another, HARDIRQ-unsafe lock in the past:
(clocks_lock){+.+...}
and interrupts could create inverse lock ordering between them.
other info that might help us debug this:
Possible interrupt unsafe locking scenario:
CPU0CPU1
lock(clocks_lock);
local_irq_disable();
lock((host-lock)-rlock);
lock(clocks_lock);
Interrupt
lock((host-lock)-rlock);
*** DEADLOCK ***
Signed-off-by: Tushar Behera tushar.beh...@linaro.org
---
arch/arm/plat-samsung/clock.c |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 65c5eca..9b71719 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -144,6 +144,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
int clk_set_rate(struct clk *clk, unsigned long rate)
{
+ unsigned long flags;
int ret;
if (IS_ERR(clk))
@@ -159,9 +160,9 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
if (clk-ops == NULL || clk-ops-set_rate == NULL)
return -EINVAL;
- spin_lock(clocks_lock);
+ spin_lock_irqsave(clocks_lock, flags);
ret = (clk-ops-set_rate)(clk, rate);
- spin_unlock(clocks_lock);
+ spin_unlock_irqrestore(clocks_lock, flags);
return ret;
}
--
1.7.4.1
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Re: [PATCH v5 4/9] mmc: dw_mmc: lookup for optional biu and ciu clocks
Hi Jaehoon,
Thanks for reviewing the patch.
On 5 September 2012 14:00, Jaehoon Chung jh80.ch...@samsung.com wrote:
On 09/05/2012 04:46 AM, Thomas Abraham wrote:
Some platforms allow for clock gating and control of bus interface unit clock
and card interface unit clock. Add support for clock lookup of optional biu
and ciu clocks for clock gating and clock speed determination.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
Acked-by: Will Newton will.new...@imgtec.com
---
drivers/mmc/host/dw_mmc.c | 50
+--
include/linux/mmc/dw_mmc.h |4 +++
2 files changed, 51 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 227c42e..e8c8491 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -1960,13 +1960,40 @@ int dw_mci_probe(struct dw_mci *host)
return -ENODEV;
}
- if (!host-pdata-bus_hz) {
+ host-biu_clk = clk_get(host-dev, biu);
+ if (IS_ERR(host-biu_clk)) {
+ dev_dbg(host-dev, biu clock not available\n);
+ } else {
+ ret = clk_prepare_enable(host-biu_clk);
+ if (ret) {
+ dev_err(host-dev, failed to enable biu clock\n);
+ return ret;
didn't clk_put() for biu_clk?
Yes, I missed that. Thanks for pointing this out. I will fix this.
+ }
+ }
+
+ host-ciu_clk = clk_get(host-dev, ciu);
+ if (IS_ERR(host-ciu_clk)) {
+ dev_dbg(host-dev, ciu clock not available\n);
+ } else {
+ ret = clk_prepare_enable(host-ciu_clk);
+ if (ret) {
+ dev_err(host-dev, failed to enable ciu clock\n);
+ goto err_clk_biu;
+ }
+ }
+
+ if (IS_ERR(host-ciu_clk))
+ host-bus_hz = host-pdata-bus_hz;
+ else
+ host-bus_hz = clk_get_rate(host-ciu_clk);
+
+ if (!host-bus_hz) {
dev_err(host-dev,
Platform data must supply bus speed\n);
- return -ENODEV;
+ ret = -ENODEV;
+ goto err_clk_ciu;
}
- host-bus_hz = host-pdata-bus_hz;
host-quirks = host-pdata-quirks;
spin_lock_init(host-lock);
@@ -2116,6 +2143,17 @@ err_dmaunmap:
regulator_disable(host-vmmc);
regulator_put(host-vmmc);
}
+
+err_clk_ciu:
+ if (!IS_ERR(host-ciu_clk)) {
+ clk_disable_unprepare(host-ciu_clk);
+ clk_put(host-ciu_clk);
+ }
+err_clk_biu:
I think right that is located the clk_put(host-ciu_clk) at here
In the next version of this patch, if clk_prepare_enable() fails for
host-ciu_clk, the put(host-ciu_clk) is also done before returning.
Thanks,
Thomas.
+ if (!IS_ERR(host-biu_clk)) {
+ clk_disable_unprepare(host-biu_clk);
+ clk_put(host-biu_clk);
+ }
return ret;
}
EXPORT_SYMBOL(dw_mci_probe);
@@ -2149,6 +2187,12 @@ void dw_mci_remove(struct dw_mci *host)
regulator_put(host-vmmc);
}
+ if (!IS_ERR(host-ciu_clk))
+ clk_disable_unprepare(host-ciu_clk);
+ if (!IS_ERR(host-biu_clk))
+ clk_disable_unprepare(host-biu_clk);
+ clk_put(host-ciu_clk);
+ clk_put(host-biu_clk);
}
EXPORT_SYMBOL(dw_mci_remove);
diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
index a37a573..787ad56 100644
--- a/include/linux/mmc/dw_mmc.h
+++ b/include/linux/mmc/dw_mmc.h
@@ -78,6 +78,8 @@ struct mmc_data;
* @data_offset: Set the offset of DATA register according to VERID.
* @dev: Device associated with the MMC controller.
* @pdata: Platform data associated with the MMC controller.
+ * @biu_clk: Pointer to bus interface unit clock instance.
+ * @ciu_clk: Pointer to card interface unit clock instance.
* @slot: Slots sharing this MMC controller.
* @fifo_depth: depth of FIFO.
* @data_shift: log2 of FIFO item size.
@@ -158,6 +160,8 @@ struct dw_mci {
u16 data_offset;
struct device *dev;
struct dw_mci_board *pdata;
+ struct clk *biu_clk;
+ struct clk *ciu_clk;
struct dw_mci_slot *slot[MAX_MCI_SLOTS];
/* FIFO push and pull */
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[PATCH 0/2] DMA: PL330: Clock and runtime cleanup
The controller clock is being managed at AMBA bus level probe/remove and pm_runtime/suspend functions. The existing driver does the clock enable/disable again in the same code paths, which unneccessarily increments the usage count of the clock for the same device. The following patches remove the redundant clock enable/disable from the driver. Inderpal Singh (2): DMA: PL330: Remove controller clock enable/disable DMA: PL330: Remove redundant runtime_suspend/resume functions drivers/dma/pl330.c | 73 --- 1 file changed, 5 insertions(+), 68 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] DMA: PL330: Remove controller clock enable/disable
The controller clock is being enabled/disabled in AMBA bus infrastructre in probe/remove functions. Hence, its not required at driver level probe/remove. Signed-off-by: Inderpal Singh inderpal.si...@linaro.org --- drivers/dma/pl330.c | 12 1 file changed, 12 deletions(-) diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c index e4feba6..f70e783 100644 --- a/drivers/dma/pl330.c +++ b/drivers/dma/pl330.c @@ -2896,11 +2896,6 @@ pl330_probe(struct amba_device *adev, const struct amba_id *id) amba_set_drvdata(adev, pdmac); -#ifndef CONFIG_PM_RUNTIME - /* enable dma clk */ - clk_enable(pdmac-clk); -#endif - irq = adev-irq[0]; ret = request_irq(irq, pl330_irq_handler, 0, dev_name(adev-dev), pi); @@ -2987,9 +2982,6 @@ probe_err5: probe_err4: free_irq(irq, pi); probe_err3: -#ifndef CONFIG_PM_RUNTIME - clk_disable(pdmac-clk); -#endif clk_put(pdmac-clk); probe_err2: iounmap(pi-base); @@ -3037,10 +3029,6 @@ static int __devexit pl330_remove(struct amba_device *adev) res = adev-res; release_mem_region(res-start, resource_size(res)); -#ifndef CONFIG_PM_RUNTIME - clk_disable(pdmac-clk); -#endif - kfree(pdmac); return 0; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] DMA: PL330: Remove redundant runtime_suspend/resume functions
The driver's runtime_suspend/resume functions just disable/enable
the clock which is already being managed at AMBA bus level
runtime_suspend/resume functions.
Hence, remove the driver's runtime_suspend/resume functions.
Signed-off-by: Inderpal Singh inderpal.si...@linaro.org
---
drivers/dma/pl330.c | 61 +--
1 file changed, 5 insertions(+), 56 deletions(-)
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index f70e783..d9e1433 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -23,7 +23,6 @@
#include linux/dmaengine.h
#include linux/amba/bus.h
#include linux/amba/pl330.h
-#include linux/pm_runtime.h
#include linux/scatterlist.h
#include linux/of.h
@@ -586,8 +585,6 @@ struct dma_pl330_dmac {
/* Peripheral channels connected to this DMAC */
struct dma_pl330_chan *peripherals; /* keep at end */
-
- struct clk *clk;
};
struct dma_pl330_desc {
@@ -2887,24 +2884,17 @@ pl330_probe(struct amba_device *adev, const struct
amba_id *id)
goto probe_err1;
}
- pdmac-clk = clk_get(adev-dev, dma);
- if (IS_ERR(pdmac-clk)) {
- dev_err(adev-dev, Cannot get operation clock.\n);
- ret = -EINVAL;
- goto probe_err2;
- }
-
amba_set_drvdata(adev, pdmac);
irq = adev-irq[0];
ret = request_irq(irq, pl330_irq_handler, 0,
dev_name(adev-dev), pi);
if (ret)
- goto probe_err3;
+ goto probe_err2;
ret = pl330_add(pi);
if (ret)
- goto probe_err4;
+ goto probe_err3;
INIT_LIST_HEAD(pdmac-desc_pool);
spin_lock_init(pdmac-pool_lock);
@@ -2964,7 +2954,7 @@ pl330_probe(struct amba_device *adev, const struct
amba_id *id)
ret = dma_async_device_register(pd);
if (ret) {
dev_err(adev-dev, unable to register DMAC\n);
- goto probe_err5;
+ goto probe_err4;
}
dev_info(adev-dev,
@@ -2977,12 +2967,10 @@ pl330_probe(struct amba_device *adev, const struct
amba_id *id)
return 0;
-probe_err5:
- pl330_del(pi);
probe_err4:
- free_irq(irq, pi);
+ pl330_del(pi);
probe_err3:
- clk_put(pdmac-clk);
+ free_irq(irq, pi);
probe_err2:
iounmap(pi-base);
probe_err1:
@@ -3044,49 +3032,10 @@ static struct amba_id pl330_ids[] = {
MODULE_DEVICE_TABLE(amba, pl330_ids);
-#ifdef CONFIG_PM_RUNTIME
-static int pl330_runtime_suspend(struct device *dev)
-{
- struct dma_pl330_dmac *pdmac = dev_get_drvdata(dev);
-
- if (!pdmac) {
- dev_err(dev, failed to get dmac\n);
- return -ENODEV;
- }
-
- clk_disable(pdmac-clk);
-
- return 0;
-}
-
-static int pl330_runtime_resume(struct device *dev)
-{
- struct dma_pl330_dmac *pdmac = dev_get_drvdata(dev);
-
- if (!pdmac) {
- dev_err(dev, failed to get dmac\n);
- return -ENODEV;
- }
-
- clk_enable(pdmac-clk);
-
- return 0;
-}
-#else
-#define pl330_runtime_suspend NULL
-#define pl330_runtime_resume NULL
-#endif /* CONFIG_PM_RUNTIME */
-
-static const struct dev_pm_ops pl330_pm_ops = {
- .runtime_suspend = pl330_runtime_suspend,
- .runtime_resume = pl330_runtime_resume,
-};
-
static struct amba_driver pl330_driver = {
.drv = {
.owner = THIS_MODULE,
.name = dma-pl330,
- .pm = pl330_pm_ops,
},
.id_table = pl330_ids,
.probe = pl330_probe,
--
1.7.9.5
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Re: [PATCH V4 2/2] video: drm: exynos: Add device tree support
2012/9/7 Inki Dae inki@samsung.com: Hi 2012/9/7 Leela Krishna Amudala l.kris...@samsung.com: Hi, On Thu, Sep 6, 2012 at 4:35 PM, Sylwester Nawrocki s.nawro...@samsung.com wrote: Hi, On 09/06/2012 09:21 AM, InKi Dae wrote: +Required properties: + - compatible: Should be samsung,exynos5-fimd or samsung,exynos4-fb for Doesn't better to use single word? fimd or fb?. I think 'fb' is used for framebuffer historically. but now it's used both fb and drm, so fimd is neutral and architecture specific. To do this, Modify arch-exynos first and update it at each drivers it properly. Thank you, Kyungmin Park I agree with Kyungmin but I'd like to use as is. the reason we used 'exynos4-fb' as device name, is for that it uses fimd driver's platform device commonly and gets fimd clock. so I think that dts file should be defined with hardware specific name but not driver name such as 'exynos4-fb'. but with this, we can't get fimd clock with device's name because 'exynos4-fb' is used as device name of fimd clock. so to use 'exynos4-fimd', we should modify the device name of fimd clock from 'exynos4-fb' to 'exynos4-fimd' and also ids definitions of s3c-fb and drm fimd driver. so my conclusion is that it merges this I think it's good moment to put those things in order, i.e. use uniform 'compatible' names: samsung,exynos4-fimd, samsung,exynos5-fimd. Platform device names are separate issue, but could perhaps be unified at this time as well. Yes, Platform device name is independent of compatible string. Will change the compatible string to samsung,exynos4-fimd and will keep the device name as exynos4-fb for now. Will change the platform device names to exynosX-fimd later. I'm not sure that clk_get is worked well with this change. I think, when driver called clk_get(), first of all, it tries to get a clk from the registered list of clock providers in the dts file and next in legacy way. but now legacy way(needing clock name and device' name) would be failed if the dts file has no the list because platform device's name differs from device name of clock. so I think we should change device name of clock and also ids of related drivers for compatibility with non-dt. for this, we need some patch sets, changing arch/arm/mach-exynos/common.c and changing arch/arm/mach-exynos/clock-exynos4/5.c and changing s3c-fb.c and last this patch. if there are no other opinions, I'd like to merge this patch set(v5) and next we can update others(maybe common.c, clock-exynos4/5.c and s3c-fb.c) later. there is my missing point. with dt, platform device's name is set by OF_DEV_AUXDATA's name so it doesn't need to modify things related to exynos4 anymore. we just need to update things related to exynos5. Thanks. Inki Dae Thanks. Inki Dae patch set as is and then let's modify related things later. any opinions, welcome~ anytime. Thanks. Inki Dae -- Regards, Sylwester -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html ___ dri-devel mailing list dri-de...@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V5 0/2] video: drm: Add Device tree support to DRM-FIMD
Applied. Thanks. Inki Dae 2012/9/7 Leela Krishna Amudala l.kris...@samsung.com: This patch set adds device tree support for DRM-FIMD for Samsung's Exynos5250. It includes parsing platform data from dts file. Also, adds the driver data for exynos4 and exynos5 devices. This patchset is based and tested on top of v3.6-rc4 on smdk5250 board Also depends on below patchset http://lists.freedesktop.org/archives/dri-devel/2012-August/026076.html Changes since V4: - Changed the compatible string from samsung,exynos4-fb to samsung,exynos4-fimd. Changes since V3: - Removed the fimd version from driver data and using timing base address instead - Removed the drm_ prefixes to the structures and fucntions Changes since V2: - Added driver data to exynos5-drm-fimd as per Marek Szyprowski suggestion Changes since V1: - Corrected typo errors and changed compatibility string Leela Krishna Amudala (2): drm/exynos: add platform_device_id table and driver data for drm fimd video: drm: exynos: Add device tree support Documentation/devicetree/bindings/fb/drm-fimd.txt | 80 drivers/gpu/drm/exynos/exynos_drm_fimd.c | 138 - 2 files changed, 212 insertions(+), 6 deletions(-) create mode 100644 Documentation/devicetree/bindings/fb/drm-fimd.txt ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 9/9] mmc: dw_mmc: add support for exynos specific implementation of dw-mshc
Hi Seungwon,
Thanks for reviewing the patch.
On 5 September 2012 16:13, Seungwon Jeon tgih@samsung.com wrote:
On Wednesday, September 05, 2012, Thomas Abraham thomas.abra...@linaro.org
wrote:
Version 6 is right?
Samsung Exynos SoC's extend the dw-mshc controller for additional clock and
bus
control. Add support for these extensions and include provide device tree
based
discovery suppory as well.
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
Acked-by: Will Newton will.new...@imgtec.com
---
.../devicetree/bindings/mmc/exynos-dw-mshc.txt | 86 +++
drivers/mmc/host/Kconfig |9 +
drivers/mmc/host/Makefile |1 +
drivers/mmc/host/dw_mmc-exynos.c | 253
4 files changed, 349 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
create mode 100644 drivers/mmc/host/dw_mmc-exynos.c
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
new file mode 100644
index 000..323a891
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -0,0 +1,86 @@
+* Samsung Exynos specific extensions to the Synopsis Designware Mobile
+ Storage Host Controller
+
+The Synopsis designware mobile storage host controller is used to interface
+a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
+differences between the core Synopsis dw mshc controller properties
described
+by synposis-dw-mshc.txt and the properties used by the Samsung Exynos
specific
+extensions to the Synopsis Designware Mobile Storage Host Controller.
+
+Required Properties:
+
+* compatible: should be
+ - samsung,exynos4210-dw-mshc: for controllers with Samsung Exynos4210
+ specific extentions.
+ - samsung,exynos4412-dw-mshc: for controllers with Samsung Exynos4412
+ specific extentions.
+ - samsung,exynos5250-dw-mshc: for controllers with Samsung Exynos5250
+ specific extentions.
+
+* samsung,dw-mshc-ciu-div: Specifies the divider value for the card
interface
+ unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
+ ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7.
+
+* samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift
value
+ in transmit mode and CIU clock phase shift value in receive mode for
single
+ data rate mode operation. Refer notes below for the order of the cells
and the
+ valid values.
+
+* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift
value
+ in transmit mode and CIU clock phase shift value in receive mode for
double
+ data rate mode operation. Refer notes below for the order of the cells
and the
+ valid values.
+
+ Notes for the sdr-timing and ddr-timing values:
+
+The order of the cells should be
+ - First Cell: CIU clock phase shift value for tx mode.
+ - Second Cell: CIU clock phase shift value for rx mode.
+
+Valid values for SDR and DDR CIU clock timing for Exynos5250:
+ - valid value for tx phase shift and rx phase shift is 0 to 7.
+ - when CIU clock divider value is set to 3, all possible 8 phase shift
+values can be used.
+ - if CIU clock divider value is 0 (that is divide by 1), both tx and
rx
+phase shift clocks should be 0.
+
+Required properties for a slot:
+
+* gpios: specifies a list of gpios used for command, clock and data bus. The
+ first gpio is the command line and the second gpio is the clock line. The
+ rest of the gpios (depending on the bus-width property) are the data
lines in
+ no particular order. The format of the gpio specifier depends on the gpio
+ controller.
+
+Example:
+
+ The MSHC controller node can be split into two portions, SoC specific and
+ board specific portions as listed below.
+
+ dwmmc0@1220 {
+ compatible = samsung,exynos5250-dw-mshc;
+ reg = 0x1220 0x1000;
+ interrupts = 0 75 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
+ dwmmc0@1220 {
+ num-slots = 1;
+ supports-highspeed;
+ broken-cd;
+ fifo-depth = 0x80;
+ card-detect-delay = 200;
+ samsung,dw-mshc-sdr-timing = 2 3 3;
+ samsung,dw-mshc-ddr-timing = 1 2 3;
Third filed is still useful?
No, it is not used anymore. Thanks for pointing this out.
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ gpios = gpc0 0 2 0 3, gpc0 1 2 0 3,
+ gpc1 0 2 3 3, gpc1 1 2 3 3,
+ gpc1 2 2 3 3, gpc1 3 2 3 3,
+ gpc0 3 2 3 3, gpc0 4 2 3 3,
+
[PATCH 1/2] ARM: samsung: clock: add clock_tree debugfs file
From: Colin Cross ccr...@android.com
Add a clock/clock_tree debugfs file that shows the entire clock
hierarchy including usage counts and rates.
Signed-off-by: Colin Cross ccr...@android.com
Signed-off-by: Jonghwan Choi jhbird.c...@samsung.com
---
arch/arm/plat-samsung/clock.c | 65
-
1 files changed, 64 insertions(+), 1 deletions(-)
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index b7338ce..9392959 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -396,6 +396,64 @@ int __init s3c24xx_register_baseclocks(unsigned long
xtal)
static struct dentry *clk_debugfs_root;
+static void clock_tree_show_one(struct seq_file *s, struct clk *c, int
level)
+{
+ struct clk *child;
+ const char *state;
+ char buf[255] = { 0 };
+ int n = 0;
+
+ if (c-name)
+ n = snprintf(buf, sizeof(buf) - 1, %s, c-name);
+
+ if (c-devname)
+ n += snprintf(buf + n, sizeof(buf) - 1 - n, :%s, c-
devname);
+
+ state = (c-usage 0) ? on : off;
+
+ seq_printf(s, %*s%-*s %-6s %-3d %-10lu\n,
+ level * 3 + 1, ,
+ 50 - level * 3, buf,
+ state, c-usage, clk_get_rate(c));
+
+ list_for_each_entry(child, clocks, list) {
+ if (child-parent != c)
+ continue;
+
+ clock_tree_show_one(s, child, level + 1);
+ }
+}
+
+static int clock_tree_show(struct seq_file *s, void *data)
+{
+ struct clk *c;
+ unsigned long flags;
+
+ seq_printf(s, clock
state ref rate\n);
+ seq_printf(s, -
---\n);
+
+ spin_lock_irqsave(clocks_lock, flags);
+
+ list_for_each_entry(c, clocks, list)
+ if (c-parent == NULL)
+ clock_tree_show_one(s, c, 0);
+
+ spin_unlock_irqrestore(clocks_lock, flags);
+ return 0;
+}
+
+static int clock_tree_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, clock_tree_show, inode-i_private);
+}
+
+static const struct file_operations clock_tree_fops = {
+ .open = clock_tree_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
0001-ARM-samsung-clock-add-clock_tree-debugfs-file.patch 106L, 2832C
1,1 Top
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release= single_release,
+};
+
static int clk_debugfs_register_one(struct clk *c)
{
int err;
@@ -457,13 +515,18 @@ static int __init clk_debugfs_init(void)
{
struct clk *c;
struct dentry *d;
- int err;
+ int err = -ENOMEM;
d = debugfs_create_dir(clock, NULL);
if (!d)
return -ENOMEM;
clk_debugfs_root = d;
+ d = debugfs_create_file(clock_tree, S_IRUGO, clk_debugfs_root,
NULL,
+ clock_tree_fops);
+ if (!d)
+ goto err_out;
+
list_for_each_entry(c, clocks, list) {
err = clk_debugfs_register(c);
if (err)
--
1.7.1
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[PATCH 2/2] ARM: samsung: call clk_get_rate for debugfs rate files
From: Colin Cross ccr...@android.com
c-rate is rarely set, call clk_get_rate on the clock to print
the value in /d/clock/.../rate.
Signed-off-by: Colin Cross ccr...@android.com
Signed-off-by: Jonghwan Choi jhbird.c...@samsung.com
---
arch/arm/plat-samsung/clock.c | 10 +-
1 files changed, 9 insertions(+), 1 deletions(-)
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 9392959..b8ec1cf 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -454,6 +454,14 @@ static const struct file_operations clock_tree_fops = {
.release= single_release,
};
+static int clock_rate_show(void *data, u64 *val)
+{
+ struct clk *c = data;
+ *val = clk_get_rate(c);
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_rate_show, NULL, %llu\n);
+
static int clk_debugfs_register_one(struct clk *c)
{
int err;
@@ -480,7 +488,7 @@ static int clk_debugfs_register_one(struct clk *c)
goto err_out;
}
- d = debugfs_create_u32(rate, S_IRUGO, c-dent, (u32 *)c-rate);
+ d = debugfs_create_file(rate, S_IRUGO, c-dent, c,
clock_rate_fops);
if (!d) {
err = -ENOMEM;
goto err_out;
--
1.7.1
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[PATCH Resend 1/2] ARM: dts: Use active low flag for gpio-keys on Origen
Commit: f447ed8b31d (gpio: samsung: add flags specifier to
device-tree binding) adds a flag to represent active low state
for gpio line. Since gpio-keys on Origen board are active low,
using this flag to represent the same.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
Reviewed-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/boot/dts/exynos4210-origen.dts | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index 0c49caa..c37edf0 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -62,31 +62,31 @@
up {
label = Up;
- gpios = gpx2 0 0 0 2;
+ gpios = gpx2 0 0 0x1 2;
linux,code = 103;
};
down {
label = Down;
- gpios = gpx2 1 0 0 2;
+ gpios = gpx2 1 0 0x1 2;
linux,code = 108;
};
back {
label = Back;
- gpios = gpx1 7 0 0 2;
+ gpios = gpx1 7 0 0x1 2;
linux,code = 158;
};
home {
label = Home;
- gpios = gpx1 6 0 0 2;
+ gpios = gpx1 6 0 0x1 2;
linux,code = 102;
};
menu {
label = Menu;
- gpios = gpx1 5 0 0 2;
+ gpios = gpx1 5 0 0x1 2;
linux,code = 139;
};
};
--
1.7.4.1
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[PATCH Resend 2/2] ARM: dts: Add heartbeat gpio-leds support to Origen
Adds heartbeat gpio-leds support to Origen board.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
arch/arm/boot/dts/exynos4210-origen.dts |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index c37edf0..d69a799 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -91,6 +91,14 @@
};
};
+ leds {
+ compatible = gpio-leds;
+ status {
+ gpios = gpx1 3 0 0x1 2;
+ linux,default-trigger = heartbeat;
+ };
+ };
+
keypad@100A {
status = disabled;
};
--
1.7.4.1
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[PATCH v5 4/9] mmc: dw_mmc: lookup for optional biu and ciu clocks
Some platforms allow for clock gating and control of bus interface unit clock
and card interface unit clock. Add support for clock lookup of optional biu
and ciu clocks for clock gating and clock speed determination.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
Acked-by: Will Newton will.new...@imgtec.com
---
drivers/mmc/host/dw_mmc.c | 52 +--
include/linux/mmc/dw_mmc.h |4 +++
2 files changed, 53 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 227c42e..de45ad2 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -1960,13 +1960,42 @@ int dw_mci_probe(struct dw_mci *host)
return -ENODEV;
}
- if (!host-pdata-bus_hz) {
+ host-biu_clk = clk_get(host-dev, biu);
+ if (IS_ERR(host-biu_clk)) {
+ dev_dbg(host-dev, biu clock not available\n);
+ } else {
+ ret = clk_prepare_enable(host-biu_clk);
+ if (ret) {
+ dev_err(host-dev, failed to enable biu clock\n);
+ clk_put(host-biu_clk);
+ return ret;
+ }
+ }
+
+ host-ciu_clk = clk_get(host-dev, ciu);
+ if (IS_ERR(host-ciu_clk)) {
+ dev_dbg(host-dev, ciu clock not available\n);
+ } else {
+ ret = clk_prepare_enable(host-ciu_clk);
+ if (ret) {
+ dev_err(host-dev, failed to enable ciu clock\n);
+ clk_put(host-ciu_clk);
+ goto err_clk_biu;
+ }
+ }
+
+ if (IS_ERR(host-ciu_clk))
+ host-bus_hz = host-pdata-bus_hz;
+ else
+ host-bus_hz = clk_get_rate(host-ciu_clk);
+
+ if (!host-bus_hz) {
dev_err(host-dev,
Platform data must supply bus speed\n);
- return -ENODEV;
+ ret = -ENODEV;
+ goto err_clk_ciu;
}
- host-bus_hz = host-pdata-bus_hz;
host-quirks = host-pdata-quirks;
spin_lock_init(host-lock);
@@ -2116,6 +2145,17 @@ err_dmaunmap:
regulator_disable(host-vmmc);
regulator_put(host-vmmc);
}
+
+err_clk_ciu:
+ if (!IS_ERR(host-ciu_clk)) {
+ clk_disable_unprepare(host-ciu_clk);
+ clk_put(host-ciu_clk);
+ }
+err_clk_biu:
+ if (!IS_ERR(host-biu_clk)) {
+ clk_disable_unprepare(host-biu_clk);
+ clk_put(host-biu_clk);
+ }
return ret;
}
EXPORT_SYMBOL(dw_mci_probe);
@@ -2149,6 +2189,12 @@ void dw_mci_remove(struct dw_mci *host)
regulator_put(host-vmmc);
}
+ if (!IS_ERR(host-ciu_clk))
+ clk_disable_unprepare(host-ciu_clk);
+ if (!IS_ERR(host-biu_clk))
+ clk_disable_unprepare(host-biu_clk);
+ clk_put(host-ciu_clk);
+ clk_put(host-biu_clk);
}
EXPORT_SYMBOL(dw_mci_remove);
diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
index a37a573..787ad56 100644
--- a/include/linux/mmc/dw_mmc.h
+++ b/include/linux/mmc/dw_mmc.h
@@ -78,6 +78,8 @@ struct mmc_data;
* @data_offset: Set the offset of DATA register according to VERID.
* @dev: Device associated with the MMC controller.
* @pdata: Platform data associated with the MMC controller.
+ * @biu_clk: Pointer to bus interface unit clock instance.
+ * @ciu_clk: Pointer to card interface unit clock instance.
* @slot: Slots sharing this MMC controller.
* @fifo_depth: depth of FIFO.
* @data_shift: log2 of FIFO item size.
@@ -158,6 +160,8 @@ struct dw_mci {
u16 data_offset;
struct device *dev;
struct dw_mci_board *pdata;
+ struct clk *biu_clk;
+ struct clk *ciu_clk;
struct dw_mci_slot *slot[MAX_MCI_SLOTS];
/* FIFO push and pull */
--
1.6.6.rc2
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[PATCH v5 8/9] mmc: dw_mmc: add support for implementation specific callbacks
The core dw-mshc controller driver can let platform specific implementations
of the dw-mshc controller to control the hardware as required by such
implementations. This is acheived by invoking implementation specific (optional)
callbacks. Define the list of callbacks supported the add invocation points
for the same.
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
Acked-by: Will Newton will.new...@imgtec.com
---
drivers/mmc/host/dw_mmc-pltfm.c | 12 -
drivers/mmc/host/dw_mmc-pltfm.h |3 +-
drivers/mmc/host/dw_mmc.c | 47 ++-
drivers/mmc/host/dw_mmc.h | 24
include/linux/mmc/dw_mmc.h |4 +++
5 files changed, 86 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
index e17da91..c960ca7 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -23,7 +23,8 @@
#include dw_mmc.h
-int dw_mci_pltfm_register(struct platform_device *pdev)
+int dw_mci_pltfm_register(struct platform_device *pdev,
+ struct dw_mci_drv_data *drv_data)
{
struct dw_mci *host;
struct resource *regs;
@@ -41,6 +42,7 @@ int dw_mci_pltfm_register(struct platform_device *pdev)
if (host-irq 0)
return host-irq;
+ host-drv_data = drv_data;
host-dev = pdev-dev;
host-irq_flags = 0;
host-pdata = pdev-dev.platform_data;
@@ -48,6 +50,12 @@ int dw_mci_pltfm_register(struct platform_device *pdev)
if (!host-regs)
return -ENOMEM;
+ if (host-drv_data-init) {
+ ret = host-drv_data-init(host);
+ if (ret)
+ return ret;
+ }
+
platform_set_drvdata(pdev, host);
ret = dw_mci_probe(host);
return ret;
@@ -56,7 +64,7 @@ EXPORT_SYMBOL_GPL(dw_mci_pltfm_register);
static int __devinit dw_mci_pltfm_probe(struct platform_device *pdev)
{
- return dw_mci_pltfm_register(pdev);
+ return dw_mci_pltfm_register(pdev, NULL);
}
static int __devexit dw_mci_pltfm_remove(struct platform_device *pdev)
diff --git a/drivers/mmc/host/dw_mmc-pltfm.h b/drivers/mmc/host/dw_mmc-pltfm.h
index 6c065d9..301f245 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.h
+++ b/drivers/mmc/host/dw_mmc-pltfm.h
@@ -12,7 +12,8 @@
#ifndef _DW_MMC_PLTFM_H_
#define _DW_MMC_PLTFM_H_
-extern int dw_mci_pltfm_register(struct platform_device *pdev);
+extern int dw_mci_pltfm_register(struct platform_device *pdev,
+ struct dw_mci_drv_data *drv_data);
extern int __devexit dw_mci_pltfm_remove(struct platform_device *pdev);
extern const struct dev_pm_ops dw_mci_pltfm_pmops;
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index c792466..9f8e487 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -231,6 +231,7 @@ static void dw_mci_set_timeout(struct dw_mci *host)
static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command
*cmd)
{
struct mmc_data *data;
+ struct dw_mci_slot *slot = mmc_priv(mmc);
u32 cmdr;
cmd-error = -EINPROGRESS;
@@ -260,6 +261,9 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc,
struct mmc_command *cmd)
cmdr |= SDMMC_CMD_DAT_WR;
}
+ if (slot-host-drv_data-prepare_command)
+ slot-host-drv_data-prepare_command(slot-host, cmdr);
+
return cmdr;
}
@@ -815,6 +819,9 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct
mmc_ios *ios)
slot-clock = ios-clock;
}
+ if (slot-host-drv_data-set_ios)
+ slot-host-drv_data-set_ios(slot-host, ios);
+
switch (ios-power_mode) {
case MMC_POWER_UP:
set_bit(DW_MMC_CARD_NEED_INIT, slot-flags);
@@ -1820,6 +1827,7 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned
int id)
{
struct mmc_host *mmc;
struct dw_mci_slot *slot;
+ int ctrl_id, ret;
u8 bus_width;
mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host-dev);
@@ -1851,6 +1859,16 @@ static int dw_mci_init_slot(struct dw_mci *host,
unsigned int id)
if (host-pdata-caps)
mmc-caps = host-pdata-caps;
+ if (host-dev-of_node) {
+ ctrl_id = of_alias_get_id(host-dev-of_node, mshc);
+ if (ctrl_id 0)
+ ctrl_id = 0;
+ } else {
+ ctrl_id = to_platform_device(host-dev)-id;
+ }
+ if (host-drv_data host-drv_data-caps)
+ mmc-caps |= host-drv_data-caps[ctrl_id];
+
if (host-pdata-caps2)
mmc-caps2 = host-pdata-caps2;
@@ -1861,6 +1879,14 @@ static int dw_mci_init_slot(struct dw_mci *host,
unsigned int id)
else
bus_width = 1;
+ if (host-drv_data-setup_bus) {
+ struct device_node *slot_np;
+
[PATCH v5 9/9] mmc: dw_mmc: add support for exynos specific implementation of dw-mshc
Samsung Exynos SoC's extend the dw-mshc controller for additional clock and bus
control. Add support for these extensions and include provide device tree based
discovery suppory as well.
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
Acked-by: Will Newton will.new...@imgtec.com
---
.../devicetree/bindings/mmc/exynos-dw-mshc.txt | 87 +++
drivers/mmc/host/Kconfig |9 +
drivers/mmc/host/Makefile |1 +
drivers/mmc/host/dw_mmc-exynos.c | 253
4 files changed, 350 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
create mode 100644 drivers/mmc/host/dw_mmc-exynos.c
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
new file mode 100644
index 000..7927689
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -0,0 +1,87 @@
+* Samsung Exynos specific extensions to the Synopsis Designware Mobile
+ Storage Host Controller
+
+The Synopsis designware mobile storage host controller is used to interface
+a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
+differences between the core Synopsis dw mshc controller properties described
+by synposis-dw-mshc.txt and the properties used by the Samsung Exynos specific
+extensions to the Synopsis Designware Mobile Storage Host Controller.
+
+Required Properties:
+
+* compatible: should be
+ - samsung,exynos4210-dw-mshc: for controllers with Samsung Exynos4210
+ specific extentions.
+ - samsung,exynos4412-dw-mshc: for controllers with Samsung Exynos4412
+ specific extentions.
+ - samsung,exynos5250-dw-mshc: for controllers with Samsung Exynos5250
+ specific extentions.
+
+* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
+ unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
+ ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7.
+
+* samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift
value
+ in transmit mode and CIU clock phase shift value in receive mode for single
+ data rate mode operation. Refer notes below for the order of the cells and
the
+ valid values.
+
+* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift
value
+ in transmit mode and CIU clock phase shift value in receive mode for double
+ data rate mode operation. Refer notes below for the order of the cells and
the
+ valid values.
+
+ Notes for the sdr-timing and ddr-timing values:
+
+The order of the cells should be
+ - First Cell: CIU clock phase shift value for tx mode.
+ - Second Cell: CIU clock phase shift value for rx mode.
+
+Valid values for SDR and DDR CIU clock timing for Exynos5250:
+ - valid value for tx phase shift and rx phase shift is 0 to 7.
+ - when CIU clock divider value is set to 3, all possible 8 phase shift
+values can be used.
+ - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
+phase shift clocks should be 0.
+
+Required properties for a slot:
+
+* gpios: specifies a list of gpios used for command, clock and data bus. The
+ first gpio is the command line and the second gpio is the clock line. The
+ rest of the gpios (depending on the bus-width property) are the data lines in
+ no particular order. The format of the gpio specifier depends on the gpio
+ controller.
+
+Example:
+
+ The MSHC controller node can be split into two portions, SoC specific and
+ board specific portions as listed below.
+
+ dwmmc0@1220 {
+ compatible = samsung,exynos5250-dw-mshc;
+ reg = 0x1220 0x1000;
+ interrupts = 0 75 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
+ dwmmc0@1220 {
+ num-slots = 1;
+ supports-highspeed;
+ broken-cd;
+ fifo-depth = 0x80;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ gpios = gpc0 0 2 0 3, gpc0 1 2 0 3,
+ gpc1 0 2 3 3, gpc1 1 2 3 3,
+ gpc1 2 2 3 3, gpc1 3 2 3 3,
+ gpc0 3 2 3 3, gpc0 4 2 3 3,
+ gpc0 5 2 3 3, gpc0 6 2 3 3;
+ };
+ };
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index aa131b3..9bf10e7 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -540,6 +540,15 @@ config MMC_DW_PLTFM
If unsure, say Y.
+config MMC_DW_EXYNOS
+
[PATCH v4 3/3] ARM: dts: Add nodes for dw_mmc controllers for Samsung Exynos5250 platforms
Add device nodes for the four instances of dw_mmc controllers in Exynos5250
and enable instance 0 and 2 for the smdk5250 board.
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 57 +
arch/arm/boot/dts/exynos5250.dtsi | 32
2 files changed, 89 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 8a5e348..aac8abc 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -16,6 +16,13 @@
model = SAMSUNG SMDK5250 board based on EXYNOS5250;
compatible = samsung,smdk5250, samsung,exynos5250;
+ aliases {
+ mshc0 = dwmmc_0;
+ mshc1 = dwmmc_1;
+ mshc2 = dwmmc_2;
+ mshc3 = dwmmc_3;
+ };
+
memory {
reg = 0x4000 0x8000;
};
@@ -72,6 +79,56 @@
status = disabled;
};
+ dwmmc_0: dwmmc0@1220 {
+ num-slots = 1;
+ supports-highspeed;
+ broken-cd;
+ fifo-depth = 0x80;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ gpios = gpc0 0 2 0 3, gpc0 1 2 0 3,
+ gpc1 0 2 3 3, gpc1 1 2 3 3,
+ gpc1 2 2 3 3, gpc1 3 2 3 3,
+ gpc0 3 2 3 3, gpc0 4 2 3 3,
+ gpc0 5 2 3 3, gpc0 6 2 3 3;
+ };
+ };
+
+ dwmmc_1: dwmmc1@1221 {
+ status = disabled;
+ };
+
+ dwmmc_2: dwmmc2@1222 {
+ num-slots = 1;
+ supports-highspeed;
+ fifo-depth = 0x80;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 4;
+ samsung,cd-pinmux-gpio = gpc3 2 2 3 3;
+ gpios = gpc3 0 2 0 3, gpc3 1 2 0 3,
+ gpc3 3 2 3 3, gpc3 4 2 3 3,
+ gpc3 5 2 3 3, gpc3 6 2 3 3,
+ gpc4 3 3 3 3, gpc4 3 3 3 3,
+ gpc4 5 3 3 3, gpc4 6 3 3 3;
+ };
+ };
+
+ dwmmc_3: dwmmc3@1223 {
+ status = disabled;
+ };
+
spi_0: spi@12d2 {
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 004aaa8..f69e389 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -182,6 +182,38 @@
#size-cells = 0;
};
+ dwmmc0@1220 {
+ compatible = samsung,exynos5250-dw-mshc;
+ reg = 0x1220 0x1000;
+ interrupts = 0 75 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
+ dwmmc1@1221 {
+ compatible = samsung,exynos5250-dw-mshc;
+ reg = 0x1221 0x1000;
+ interrupts = 0 76 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
+ dwmmc2@1222 {
+ compatible = samsung,exynos5250-dw-mshc;
+ reg = 0x1222 0x1000;
+ interrupts = 0 77 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
+ dwmmc3@1223 {
+ compatible = samsung,exynos5250-dw-mshc;
+ reg = 0x1223 0x1000;
+ interrupts = 0 78 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
amba {
#address-cells = 1;
#size-cells = 1;
--
1.6.6.rc2
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RE: [PATCH v5 9/9] mmc: dw_mmc: add support for exynos specific implementation of dw-mshc
On Friday, September 07, 2012, Thomas Abraham thomas.abra...@linaro.org wrote:
Hi Seungwon,
Thanks for reviewing the patch.
On 5 September 2012 16:13, Seungwon Jeon tgih@samsung.com wrote:
On Wednesday, September 05, 2012, Thomas Abraham
thomas.abra...@linaro.org wrote:
Version 6 is right?
Samsung Exynos SoC's extend the dw-mshc controller for additional clock
and bus
control. Add support for these extensions and include provide device tree
based
discovery suppory as well.
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
Acked-by: Will Newton will.new...@imgtec.com
---
.../devicetree/bindings/mmc/exynos-dw-mshc.txt | 86 +++
drivers/mmc/host/Kconfig |9 +
drivers/mmc/host/Makefile |1 +
drivers/mmc/host/dw_mmc-exynos.c | 253
4 files changed, 349 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
create mode 100644 drivers/mmc/host/dw_mmc-exynos.c
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
new file mode 100644
index 000..323a891
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -0,0 +1,86 @@
+* Samsung Exynos specific extensions to the Synopsis Designware Mobile
+ Storage Host Controller
+
+The Synopsis designware mobile storage host controller is used to
interface
+a SoC with storage medium such as eMMC or SD/MMC cards. This file
documents
+differences between the core Synopsis dw mshc controller properties
described
+by synposis-dw-mshc.txt and the properties used by the Samsung Exynos
specific
+extensions to the Synopsis Designware Mobile Storage Host Controller.
+
+Required Properties:
+
+* compatible: should be
+ - samsung,exynos4210-dw-mshc: for controllers with Samsung
Exynos4210
+ specific extentions.
+ - samsung,exynos4412-dw-mshc: for controllers with Samsung
Exynos4412
+ specific extentions.
+ - samsung,exynos5250-dw-mshc: for controllers with Samsung
Exynos5250
+ specific extentions.
+
+* samsung,dw-mshc-ciu-div: Specifies the divider value for the card
interface
+ unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
+ ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7.
+
+* samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase
shift value
+ in transmit mode and CIU clock phase shift value in receive mode for
single
+ data rate mode operation. Refer notes below for the order of the cells
and the
+ valid values.
+
+* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase
shift value
+ in transmit mode and CIU clock phase shift value in receive mode for
double
+ data rate mode operation. Refer notes below for the order of the cells
and the
+ valid values.
+
+ Notes for the sdr-timing and ddr-timing values:
+
+The order of the cells should be
+ - First Cell: CIU clock phase shift value for tx mode.
+ - Second Cell: CIU clock phase shift value for rx mode.
+
+Valid values for SDR and DDR CIU clock timing for Exynos5250:
+ - valid value for tx phase shift and rx phase shift is 0 to 7.
+ - when CIU clock divider value is set to 3, all possible 8 phase
shift
+values can be used.
+ - if CIU clock divider value is 0 (that is divide by 1), both tx
and rx
+phase shift clocks should be 0.
+
+Required properties for a slot:
+
+* gpios: specifies a list of gpios used for command, clock and data bus.
The
+ first gpio is the command line and the second gpio is the clock line.
The
+ rest of the gpios (depending on the bus-width property) are the data
lines in
+ no particular order. The format of the gpio specifier depends on the
gpio
+ controller.
+
+Example:
+
+ The MSHC controller node can be split into two portions, SoC specific
and
+ board specific portions as listed below.
+
+ dwmmc0@1220 {
+ compatible = samsung,exynos5250-dw-mshc;
+ reg = 0x1220 0x1000;
+ interrupts = 0 75 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
+ dwmmc0@1220 {
+ num-slots = 1;
+ supports-highspeed;
+ broken-cd;
+ fifo-depth = 0x80;
+ card-detect-delay = 200;
+ samsung,dw-mshc-sdr-timing = 2 3 3;
+ samsung,dw-mshc-ddr-timing = 1 2 3;
Third filed is still useful?
No, it is not used anymore. Thanks for pointing this out.
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+
Re: [PATCH v5 9/9] mmc: dw_mmc: add support for exynos specific implementation of dw-mshc
On 7 September 2012 16:21, Seungwon Jeon tgih@samsung.com wrote:
On Friday, September 07, 2012, Thomas Abraham thomas.abra...@linaro.org
wrote:
Hi Seungwon,
Thanks for reviewing the patch.
On 5 September 2012 16:13, Seungwon Jeon tgih@samsung.com wrote:
On Wednesday, September 05, 2012, Thomas Abraham
thomas.abra...@linaro.org wrote:
Version 6 is right?
Samsung Exynos SoC's extend the dw-mshc controller for additional clock
and bus
control. Add support for these extensions and include provide device tree
based
discovery suppory as well.
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
Acked-by: Will Newton will.new...@imgtec.com
---
.../devicetree/bindings/mmc/exynos-dw-mshc.txt | 86 +++
drivers/mmc/host/Kconfig |9 +
drivers/mmc/host/Makefile |1 +
drivers/mmc/host/dw_mmc-exynos.c | 253
4 files changed, 349 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
create mode 100644 drivers/mmc/host/dw_mmc-exynos.c
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
new file mode 100644
index 000..323a891
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -0,0 +1,86 @@
+* Samsung Exynos specific extensions to the Synopsis Designware Mobile
+ Storage Host Controller
+
+The Synopsis designware mobile storage host controller is used to
interface
+a SoC with storage medium such as eMMC or SD/MMC cards. This file
documents
+differences between the core Synopsis dw mshc controller properties
described
+by synposis-dw-mshc.txt and the properties used by the Samsung Exynos
specific
+extensions to the Synopsis Designware Mobile Storage Host Controller.
+
+Required Properties:
+
+* compatible: should be
+ - samsung,exynos4210-dw-mshc: for controllers with Samsung
Exynos4210
+ specific extentions.
+ - samsung,exynos4412-dw-mshc: for controllers with Samsung
Exynos4412
+ specific extentions.
+ - samsung,exynos5250-dw-mshc: for controllers with Samsung
Exynos5250
+ specific extentions.
+
+* samsung,dw-mshc-ciu-div: Specifies the divider value for the card
interface
+ unit (ciu) clock. This property is applicable only for Exynos5 SoC's
and
+ ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7.
+
+* samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase
shift value
+ in transmit mode and CIU clock phase shift value in receive mode for
single
+ data rate mode operation. Refer notes below for the order of the cells
and the
+ valid values.
+
+* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase
shift value
+ in transmit mode and CIU clock phase shift value in receive mode for
double
+ data rate mode operation. Refer notes below for the order of the cells
and the
+ valid values.
+
+ Notes for the sdr-timing and ddr-timing values:
+
+The order of the cells should be
+ - First Cell: CIU clock phase shift value for tx mode.
+ - Second Cell: CIU clock phase shift value for rx mode.
+
+Valid values for SDR and DDR CIU clock timing for Exynos5250:
+ - valid value for tx phase shift and rx phase shift is 0 to 7.
+ - when CIU clock divider value is set to 3, all possible 8 phase
shift
+values can be used.
+ - if CIU clock divider value is 0 (that is divide by 1), both tx
and rx
+phase shift clocks should be 0.
+
+Required properties for a slot:
+
+* gpios: specifies a list of gpios used for command, clock and data bus.
The
+ first gpio is the command line and the second gpio is the clock line.
The
+ rest of the gpios (depending on the bus-width property) are the data
lines in
+ no particular order. The format of the gpio specifier depends on the
gpio
+ controller.
+
+Example:
+
+ The MSHC controller node can be split into two portions, SoC specific
and
+ board specific portions as listed below.
+
+ dwmmc0@1220 {
+ compatible = samsung,exynos5250-dw-mshc;
+ reg = 0x1220 0x1000;
+ interrupts = 0 75 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
+ dwmmc0@1220 {
+ num-slots = 1;
+ supports-highspeed;
+ broken-cd;
+ fifo-depth = 0x80;
+ card-detect-delay = 200;
+ samsung,dw-mshc-sdr-timing = 2 3 3;
+ samsung,dw-mshc-ddr-timing = 1 2 3;
Third filed is still useful?
No, it is not used anymore. Thanks for pointing this out.
+
+ slot@0 {
+
Re: [PATCH 1/2] ARM: samsung: clock: add clock_tree debugfs file
Hi, On 09/07/2012 09:20 AM, 최종환 wrote: From: Colin Crossccr...@android.com Add a clock/clock_tree debugfs file that shows the entire clock hierarchy including usage counts and rates. Signed-off-by: Colin Crossccr...@android.com Signed-off-by: Jonghwan Choijhbird.c...@samsung.com Due to Korean characters this patch series has improper encoding: $ git am -3 \[PATCH\ 1_2\]\ ARM\:\ samsung\:\ clock\:\ add\ clock_tree\ debugfs\ file.eml fatal: cannot convert from ks_c_5601-1987 to UTF-8 Could you please fix this end resend ? -- Thanks, Sylwester -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH Resend 1/2] ARM: dts: Use active low flag for gpio-keys on Origen
Sachin Kamat wrote:
Commit: f447ed8b31d (gpio: samsung: add flags specifier to
device-tree binding) adds a flag to represent active low state
for gpio line. Since gpio-keys on Origen board are active low,
using this flag to represent the same.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
Reviewed-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/boot/dts/exynos4210-origen.dts | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index 0c49caa..c37edf0 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -62,31 +62,31 @@
up {
label = Up;
- gpios = gpx2 0 0 0 2;
+ gpios = gpx2 0 0 0x1 2;
linux,code = 103;
};
down {
label = Down;
- gpios = gpx2 1 0 0 2;
+ gpios = gpx2 1 0 0x1 2;
linux,code = 108;
};
back {
label = Back;
- gpios = gpx1 7 0 0 2;
+ gpios = gpx1 7 0 0x1 2;
linux,code = 158;
};
home {
label = Home;
- gpios = gpx1 6 0 0 2;
+ gpios = gpx1 6 0 0x1 2;
linux,code = 102;
};
menu {
label = Menu;
- gpios = gpx1 5 0 0 2;
+ gpios = gpx1 5 0 0x1 2;
linux,code = 139;
};
};
--
1.7.4.1
Applied, thanks.
Best regards,
Kgene.
--
Kukjin Kim kgene@samsung.com, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
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RE: [PATCH Resend 2/2] ARM: dts: Add heartbeat gpio-leds support to Origen
Sachin Kamat wrote:
Adds heartbeat gpio-leds support to Origen board.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
arch/arm/boot/dts/exynos4210-origen.dts |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index c37edf0..d69a799 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -91,6 +91,14 @@
};
};
+ leds {
+ compatible = gpio-leds;
+ status {
+ gpios = gpx1 3 0 0x1 2;
+ linux,default-trigger = heartbeat;
+ };
+ };
+
keypad@100A {
status = disabled;
};
--
1.7.4.1
Applied, thanks.
Best regards,
Kgene.
--
Kukjin Kim kgene@samsung.com, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
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RE: [PATCH Resend 1/2] ARM: dts: Use active low flag for gpio-keys on Origen
Kukjin Kim wrote:
Sachin Kamat wrote:
Commit: f447ed8b31d (gpio: samsung: add flags specifier to
device-tree binding) adds a flag to represent active low state
for gpio line. Since gpio-keys on Origen board are active low,
using this flag to represent the same.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
Reviewed-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/boot/dts/exynos4210-origen.dts | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index 0c49caa..c37edf0 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -62,31 +62,31 @@
up {
label = Up;
- gpios = gpx2 0 0 0 2;
+ gpios = gpx2 0 0 0x1 2;
linux,code = 103;
};
down {
label = Down;
- gpios = gpx2 1 0 0 2;
+ gpios = gpx2 1 0 0x1 2;
linux,code = 108;
};
back {
label = Back;
- gpios = gpx1 7 0 0 2;
+ gpios = gpx1 7 0 0x1 2;
linux,code = 158;
};
home {
label = Home;
- gpios = gpx1 6 0 0 2;
+ gpios = gpx1 6 0 0x1 2;
linux,code = 102;
};
menu {
label = Menu;
- gpios = gpx1 5 0 0 2;
+ gpios = gpx1 5 0 0x1 2;
linux,code = 139;
};
};
--
1.7.4.1
Applied, thanks.
Note, since this is not a bug fix, queued this for v3.7.
If any problem, let me know.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim kgene@samsung.com, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
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RE: [PATCH] ARM: dts: exynos4: Enable serial controllers on Origen and SMDKV310
Tomasz Figa wrote: This patch adds status override of serial nodes to enable used serial ports on Origen and SMDKV310 board. Well...I'm not sure about the status of Origen serial, but all of the serials are enabled on SMDKV310, is it right? Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v2 2/5] ARM: Exynos4: dts: Specify address and size cells for i2c controllers
Thomas Abraham wrote: On 4 September 2012 14:20, Tomasz Figa t.f...@samsung.com wrote: Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com --- arch/arm/boot/dts/exynos4.dtsi | 16 1 file changed, 16 insertions(+) Acked-by: Thomas Abraham thomas.abra...@linaro.org Looks OK to me, will apply. Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v2 3/5] ARM: Exynos4: Add OF compatibility lookups for Exynos4 i2c adapters
Thomas Abraham wrote: On 4 September 2012 14:20, Tomasz Figa t.f...@samsung.com wrote: Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com --- arch/arm/mach-exynos/mach-exynos4-dt.c | 14 ++ 1 file changed, 14 insertions(+) Acked-by: Thomas Abraham thomas.abra...@linaro.org OK, will apply. Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v2 4/5] ARM: EXYNOS: Increase maximum possible memory bank size to 512MiB
Tomasz Figa wrote: Some boards have larger memory banks than 256MiB. This patch increses maximum bank size for Exynos-based boards to 512MiB. Well...the meaning of SECTION_SIZE_BITS is a little bit different you know. Please refer to following thread. http://lists.infradead.org/pipermail/linux-arm-kernel/2010-July/020184.html Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com --- arch/arm/mach-exynos/include/mach/memory.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/include/mach/memory.h b/arch/arm/mach- exynos/include/mach/memory.h index 374ef2c..d4db508 100644 --- a/arch/arm/mach-exynos/include/mach/memory.h +++ b/arch/arm/mach-exynos/include/mach/memory.h @@ -15,8 +15,8 @@ #define PLAT_PHYS_OFFSET UL(0x4000) -/* Maximum of 256MiB in one bank */ +/* Maximum of 512MiB in one bank */ #define MAX_PHYSMEM_BITS 32 -#define SECTION_SIZE_BITS28 +#define SECTION_SIZE_BITS29 #endif /* __ASM_ARCH_MEMORY_H */ -- 1.7.12 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v2 5/5] ARM: Exynos: Add basic dts file for Samsung Trats board
Tomasz Figa wrote:
Hi,
Thanks for reviewing the patch.
On Wednesday 05 of September 2012 09:35:49 Thomas Abraham wrote:
+
+ memory {
+ reg = 0x4000 0x2000
+ 0x6000 0x2000;
+ };
Why does this have to be split. Why not have a single entry with the
size as 0x4000?
The memory node corresponds to struct meminfo and each entry (with two
values) makes one struct membank defining a memory bank.
Well...
I've been talking with Kyungmin about this. Originally bootloaders used to
report 4 banks of 256 MiB, but it turned out that real bank configuration
on Trats is 2 banks of 512 MiB.
I think, following should ok here.
memory {
reg = 0x4000 0x4000;
};
I'm not into memory management internals, so I don't know if this has any
significance, but I defined the node to represent the real configuration
(otherwise I would have probably used 4 banks of 256 MiB and drop the 4th
patch).
+ max8997_pmic@66 {
+ compatible = maxim,max8997-pmic;
+
+ reg = 0x66;
Probably, the interrupts can be listed when we have pinctrl driver
merged in Samsung tree.
Right.
Note, you can do it on top of samsung tree :-)
Thanks.
Best regards,
Kgene.
--
Kukjin Kim kgene@samsung.com, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
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RE: [PATCH 0/3] ARM: dts: Exynos4 dts reorganization
Thomas Abraham wrote: On 3 September 2012 18:04, Tomasz Figa t.f...@samsung.com wrote: This patch series prepares existing Exynos4210 DT infrastructure to be further extended for new SoCs from Exynos4 line and new boards. Tomasz Figa (3): ARM: dts: Move parts common to Exynos4 from Exynos4210.dtsi to Exynos4.dtsi ARM: EXYNOS: exynos4-dt: Use exynos4 prefix instead of exynos4210 ARM: dts: exynos4: Assume status of all optional nodes as disabled arch/arm/boot/dts/exynos4.dtsi| 232 ++ arch/arm/boot/dts/exynos4210-origen.dts | 58 +--- arch/arm/boot/dts/exynos4210-smdkv310.dts | 52 +-- arch/arm/boot/dts/exynos4210.dtsi | 181 +-- arch/arm/mach-exynos/mach-exynos4-dt.c| 18 +-- 5 files changed, 248 insertions(+), 293 deletions(-) create mode 100644 arch/arm/boot/dts/exynos4.dtsi Thanks, we can build Exynos4412 device tree support on top of this series. Acked-by: Thomas Abraham thomas.abra...@linaro.org Thomas, thanks for your ack on this series and I'm OK on this series. But you know, Donjin Kim submitted almost same patch except gpio stuff one month before this series but needs to update something though. So would be nice if either Tomasz or Dongjin could ack on the other patch? Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
