Re: [PATCH V3] ARM: EXYNOS5: Add bus clock and set parent clock for FIMD
On Friday, September 14, 2012 8:34 PM Leela Krishna Amudala wrote
>
> This patch adds the bus clock for FIMD and changes the device name for lcd
> clock
> also sets mout_mpll_user as parent clock to fimd
>
> Signed-off-by: Leela Krishna Amudala
> ---
> arch/arm/mach-exynos/clock-exynos5.c | 34 +++
> arch/arm/plat-samsung/include/plat/clock.h |2 +
> 2 files changed, 26 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
> b/arch/arm/mach-exynos/clock-exynos5.c
> index 774533c..7c6b1b4 100644
> --- a/arch/arm/mach-exynos/clock-exynos5.c
> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> @@ -891,6 +891,13 @@ static struct clk exynos5_clk_mdma1 = {
> .ctrlbit= (1 << 4),
> };
>
> +static struct clk exynos5_clk_fimd1 = {
> + .name = "fimd",
> + .devname= "exynos5-fb.1",
> + .enable = exynos5_clk_ip_disp1_ctrl,
> + .ctrlbit= (1 << 0),
> +};
> +
> struct clk *exynos5_clkset_group_list[] = {
> [0] = &clk_ext_xtal_mux,
> [1] = NULL,
> @@ -1120,6 +1127,18 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = {
> .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
> };
>
> +struct clksrc_clk exynos5_clk_sclk_fimd1 = {
> + .clk= {
> + .name = "sclk_fimd",
^^^
Use tabs instead of spaces.
> + .devname= "exynos5-fb.1",
Same as above.
> + .enable = exynos5_clksrc_mask_disp1_0_ctrl,
Same as above.
> + .ctrlbit= (1 << 0),
Same as above.
> + },
> + .sources = &exynos5_clkset_group,
> + .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
> + .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
> +};
> +
> static struct clksrc_clk exynos5_clksrcs[] = {
> {
> .clk= {
> @@ -1131,16 +1150,6 @@ static struct clksrc_clk exynos5_clksrcs[] = {
> .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8
> },
> }, {
> .clk= {
> - .name = "sclk_fimd",
> - .devname= "s3cfb.1",
> - .enable = exynos5_clksrc_mask_disp1_0_ctrl,
> - .ctrlbit= (1 << 0),
> - },
> - .sources = &exynos5_clkset_group,
> - .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size =
> 4 },
> - .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size =
> 4 },
> - }, {
> - .clk= {
> .name = "aclk_266_gscl",
> },
> .sources = &clk_src_gscl_266,
> @@ -1240,12 +1249,14 @@ static struct clksrc_clk *exynos5_sysclks[] = {
> &exynos5_clk_mdout_spi0,
> &exynos5_clk_mdout_spi1,
> &exynos5_clk_mdout_spi2,
> + &exynos5_clk_sclk_fimd1,
> };
>
> static struct clk *exynos5_clk_cdev[] = {
> &exynos5_clk_pdma0,
> &exynos5_clk_pdma1,
> &exynos5_clk_mdma1,
> + &exynos5_clk_fimd1,
> };
>
> static struct clksrc_clk *exynos5_clksrc_cdev[] = {
> @@ -1274,6 +1285,7 @@ static struct clk_lookup exynos5_clk_lookup[] = {
> CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
> CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
> CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
> + CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
> };
>
> static unsigned long exynos5_epll_get_rate(struct clk *clk)
> @@ -1492,6 +1504,8 @@ void __init_or_cpufreq exynos5_setup_clocks(void)
>
> clk_set_rate(&exynos5_clk_aclk_acp.clk, 26700);
> clk_set_rate(&exynos5_clk_pclk_acp.clk, 13400);
> + clk_set_parent(&exynos5_clk_sclk_fimd1.clk,
> + &exynos5_clk_mout_mpll_user.clk);
>
> for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
> s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
> diff --git a/arch/arm/plat-samsung/include/plat/clock.h
> b/arch/arm/plat-samsung/include/plat/clock.h
> index a62753d..d8d9802 100644
> --- a/arch/arm/plat-samsung/include/plat/clock.h
> +++ b/arch/arm/plat-samsung/include/plat/clock.h
> @@ -83,6 +83,8 @@ extern struct clk clk_ext;
> extern struct clksrc_clk clk_epllref;
> extern struct clksrc_clk clk_esysclk;
>
> +extern struct clksrc_clk exynos5_clk_sclk_fimd1;
> +
Also, is it right place for exynos5 specific clocks ???
For example, exynos4 specific clocks are placed in
'arch/arm/mach-exynos/clock-exynos4.h'.
> /* S3C64XX specific clocks */
> extern struct clk clk_h2;
> extern struct clk clk_27m;
> --
> 1.7.0.4
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Re: [PATCH v5 1/5] usb: phy: samsung: Introducing usb phy driver for hsotg
On Wed, Sep 12, 2012 at 4:38 PM, Marc Kleine-Budde wrote: > On 09/12/2012 12:45 PM, Praveen Paneri wrote: >> This driver uses usb_phy interface to interact with s3c-hsotg. Supports >> phy_init and phy_shutdown functions to enable/disable phy. Tested with >> smdk6410 and smdkv310. More SoCs can be brought under later. >> >> Signed-off-by: Praveen Paneri >> Acked-by: Heiko Stuebner >> --- >> .../devicetree/bindings/usb/samsung-usbphy.txt |9 + >> drivers/usb/phy/Kconfig|8 + >> drivers/usb/phy/Makefile |1 + >> drivers/usb/phy/samsung-usbphy.c | 371 >> >> include/linux/platform_data/samsung-usbphy.h | 27 ++ >> 5 files changed, 416 insertions(+), 0 deletions(-) >> create mode 100644 Documentation/devicetree/bindings/usb/samsung-usbphy.txt >> create mode 100644 drivers/usb/phy/samsung-usbphy.c >> create mode 100644 include/linux/platform_data/samsung-usbphy.h >> >> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt >> b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt >> new file mode 100644 >> index 000..fefd9c8 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt >> @@ -0,0 +1,9 @@ >> +* Samsung's usb phy transceiver >> + >> +The Samsung's phy transceiver is used for controlling usb otg phy for >> +s3c-hsotg usb device controller. >> + >> +Required properties: >> +- compatible : should be "samsung,exynos4210-usbphy" >> +- reg : base physical address of the phy registers and length of memory >> mapped >> + region. >> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig >> index 63c339b..313685f 100644 >> --- a/drivers/usb/phy/Kconfig >> +++ b/drivers/usb/phy/Kconfig >> @@ -32,3 +32,11 @@ config MV_U3D_PHY >> help >> Enable this to support Marvell USB 3.0 phy controller for Marvell >> SoC. >> + >> +config SAMSUNG_USBPHY >> + bool "Samsung USB PHY controller Driver" >> + depends on USB_S3C_HSOTG >> + select USB_OTG_UTILS >> + help >> + Enable this to support Samsung USB phy controller for samsung >> + SoCs. >> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile >> index b069f29..55dcfc1 100644 >> --- a/drivers/usb/phy/Makefile >> +++ b/drivers/usb/phy/Makefile >> @@ -8,3 +8,4 @@ obj-$(CONFIG_OMAP_USB2) += omap-usb2.o >> obj-$(CONFIG_USB_ISP1301)+= isp1301.o >> obj-$(CONFIG_MV_U3D_PHY) += mv_u3d_phy.o >> obj-$(CONFIG_USB_EHCI_TEGRA) += tegra_usb_phy.o >> +obj-$(CONFIG_SAMSUNG_USBPHY) += samsung-usbphy.o >> diff --git a/drivers/usb/phy/samsung-usbphy.c >> b/drivers/usb/phy/samsung-usbphy.c >> new file mode 100644 >> index 000..b00d01b >> --- /dev/null >> +++ b/drivers/usb/phy/samsung-usbphy.c >> @@ -0,0 +1,371 @@ >> +/* linux/drivers/usb/phy/samsung-usbphy.c >> + * >> + * Copyright (c) 2012 Samsung Electronics Co., Ltd. >> + * http://www.samsung.com >> + * >> + * Author: Praveen Paneri >> + * >> + * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2 as >> + * published by the Free Software Foundation. >> + * >> + * This program is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +/* Register definitions */ >> + >> +#define S3C_PHYPWR (0x00) >> + >> +#define S3C_PHYPWR_NORMAL_MASK (0x19 << 0) >> +#define S3C_PHYPWR_OTG_DISABLE (1 << 4) >> +#define S3C_PHYPWR_ANALOG_POWERDOWN (1 << 3) >> +#define S3C_PHYPWR_FORCE_SUSPEND (1 << 1) >> +/* For Exynos4 */ >> +#define EXYNOS4_PHYPWR_NORMAL_MASK (0x39 << 0) >> +#define EXYNOS4_PHYPWR_SLEEP (1 << 5) >> + >> +#define S3C_PHYCLK (0x04) >> + >> +#define S3C_PHYCLK_MODE_SERIAL (1 << 6) >> +#define S3C_PHYCLK_EXT_OSC (1 << 5) >> +#define S3C_PHYCLK_COMMON_ON_N (1 << 4) >> +#define S3C_PHYCLK_ID_PULL (1 << 2) >> +#define S3C_PHYCLK_CLKSEL_MASK (0x3 << 0) >> +#define S3C_PHYCLK_CLKSEL_SHIFT (0) >> +#define S3C_PHYCLK_CLKSEL_48M(0x0 << 0) >> +#define S3C_PHYCLK_CLKSEL_12M(0x2 << 0) >> +#define S3C_PHYCLK_CLKSEL_24M(0x3 << 0) >> + >> +#define S3C_RSTCON (0x08) >> + >> +#define S3C_RS
[PATCH V3] ARM: EXYNOS5: Add bus clock and set parent clock for FIMD
This patch adds the bus clock for FIMD and changes the device name for lcd clock
also sets mout_mpll_user as parent clock to fimd
Signed-off-by: Leela Krishna Amudala
---
arch/arm/mach-exynos/clock-exynos5.c | 34 +++
arch/arm/plat-samsung/include/plat/clock.h |2 +
2 files changed, 26 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c
b/arch/arm/mach-exynos/clock-exynos5.c
index 774533c..7c6b1b4 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -891,6 +891,13 @@ static struct clk exynos5_clk_mdma1 = {
.ctrlbit= (1 << 4),
};
+static struct clk exynos5_clk_fimd1 = {
+ .name = "fimd",
+ .devname= "exynos5-fb.1",
+ .enable = exynos5_clk_ip_disp1_ctrl,
+ .ctrlbit= (1 << 0),
+};
+
struct clk *exynos5_clkset_group_list[] = {
[0] = &clk_ext_xtal_mux,
[1] = NULL,
@@ -1120,6 +1127,18 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = {
.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
};
+struct clksrc_clk exynos5_clk_sclk_fimd1 = {
+ .clk= {
+ .name = "sclk_fimd",
+ .devname= "exynos5-fb.1",
+ .enable = exynos5_clksrc_mask_disp1_0_ctrl,
+ .ctrlbit= (1 << 0),
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
+};
+
static struct clksrc_clk exynos5_clksrcs[] = {
{
.clk= {
@@ -1131,16 +1150,6 @@ static struct clksrc_clk exynos5_clksrcs[] = {
.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8
},
}, {
.clk= {
- .name = "sclk_fimd",
- .devname= "s3cfb.1",
- .enable = exynos5_clksrc_mask_disp1_0_ctrl,
- .ctrlbit= (1 << 0),
- },
- .sources = &exynos5_clkset_group,
- .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size =
4 },
- .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size =
4 },
- }, {
- .clk= {
.name = "aclk_266_gscl",
},
.sources = &clk_src_gscl_266,
@@ -1240,12 +1249,14 @@ static struct clksrc_clk *exynos5_sysclks[] = {
&exynos5_clk_mdout_spi0,
&exynos5_clk_mdout_spi1,
&exynos5_clk_mdout_spi2,
+ &exynos5_clk_sclk_fimd1,
};
static struct clk *exynos5_clk_cdev[] = {
&exynos5_clk_pdma0,
&exynos5_clk_pdma1,
&exynos5_clk_mdma1,
+ &exynos5_clk_fimd1,
};
static struct clksrc_clk *exynos5_clksrc_cdev[] = {
@@ -1274,6 +1285,7 @@ static struct clk_lookup exynos5_clk_lookup[] = {
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
+ CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
};
static unsigned long exynos5_epll_get_rate(struct clk *clk)
@@ -1492,6 +1504,8 @@ void __init_or_cpufreq exynos5_setup_clocks(void)
clk_set_rate(&exynos5_clk_aclk_acp.clk, 26700);
clk_set_rate(&exynos5_clk_pclk_acp.clk, 13400);
+ clk_set_parent(&exynos5_clk_sclk_fimd1.clk,
+ &exynos5_clk_mout_mpll_user.clk);
for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
diff --git a/arch/arm/plat-samsung/include/plat/clock.h
b/arch/arm/plat-samsung/include/plat/clock.h
index a62753d..d8d9802 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -83,6 +83,8 @@ extern struct clk clk_ext;
extern struct clksrc_clk clk_epllref;
extern struct clksrc_clk clk_esysclk;
+extern struct clksrc_clk exynos5_clk_sclk_fimd1;
+
/* S3C64XX specific clocks */
extern struct clk clk_h2;
extern struct clk clk_27m;
--
1.7.0.4
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Re: [PATCH V2] ARM: EXYNOS5: Add bus clock and set parent clock for FIMD
On Fri, Sep 14, 2012 at 9:57 AM, Jingoo Han wrote:
>
> On Wednesday, September 12, 2012 8:49 PM Leela Krishna Amudala wrote
> >
> > This patch adds the bus clock for FIMD and changes the device name for
> > lcd clock
> > also sets mout_mpll_user as parent clock to fimd
> >
> > Signed-off-by: Leela Krishna Amudala
> > ---
> > arch/arm/mach-exynos/clock-exynos5.c | 34
> > +++
> > arch/arm/plat-samsung/include/plat/clock.h |2 +
> > 2 files changed, 26 insertions(+), 10 deletions(-)
> >
> > diff --git a/arch/arm/mach-exynos/clock-exynos5.c
> > b/arch/arm/mach-exynos/clock-exynos5.c
> > index 774533c..205d19f 100644
> > --- a/arch/arm/mach-exynos/clock-exynos5.c
> > +++ b/arch/arm/mach-exynos/clock-exynos5.c
> > @@ -891,6 +891,13 @@ static struct clk exynos5_clk_mdma1 = {
>
> [.]
>
> >
> > +struct clksrc_clk exynos5_clk_sclk_fimd = {
>
> Replace 'exynos5_clk_sclk_fimd' with 'exynos5_clk_sclk_fimd1'.
> This is because 'exynos5_clk_sclk_fimd0' can be added for other
> Exynos5 SoCs later.
>
Okay, will change it and post the next version.
> Best regards,
> Jingoo Han
>
> > + .clk= {
> > + .name = "sclk_fimd",
> > + .devname= "exynos5-fb.1",
> > + .enable = exynos5_clksrc_mask_disp1_0_ctrl,
> > + .ctrlbit= (1 << 0),
> > + },
> > + .sources = &exynos5_clkset_group,
> > + .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4
> > },
> > + .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4
> > },
> > +};
> > +
>
>
> --
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> linux-samsung-soc" in
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Re: [PATCH] ARM: EXYNOS4: Fix soft reboot hang after suspend/resume
Hi Kukjin, On 15 May 2012 10:01, Inderpal Singh wrote: > Hi Kukjin, > > On 14 May 2012 19:13, Kukjin Kim wrote: >> On 05/14/12 17:42, Inderpal Singh wrote: >>> >>> Hi Kukjin, >>> >>> On 14 May 2012 13:45, Kukjin Kim wrote: Inderpal Singh wrote: > > > Upon wake-up, clear the sleep mode set in INFORM1 register. > Is this for wake-up or _really_ software reset? And is this available on all of EXYNOS4 SoCs? >>> >>> >>> This is for soft reboot hang after one cycle of suspend/resume is >>> complete. >>> And yes this is applicable for all exynos SOCs. >>> >> Hi, >> >> As I know, we don't need it for all of EXYNOS SoCs but let me check about >> the situation you said with hardware engineer tomorrow. If any updates, let >> you know. >> > Any updates on this ? As i mentioned below, Its applicable for Origen, Pegasus and 5250 as well. > The issue happens because u-boot checks INFROM1 register to know if > its wake-up from sleep. Hence if INFORM1 is not cleared, the soft > reboot after one suspend/resume cycle will be understood by u-boot as > wake-up from sleep, so it will try to resume and will hang up. > > I have faced this issue on Origen, Pegasus SMDK and 5250 SMDK. > > Thanks, > Inder > >> >> Thanks. >> >> Best regards, >> Kgene. >> -- >> Kukjin Kim , Senior Engineer, >> SW Solution Development Team, Samsung Electronics Co., Ltd. With Regards, Inder -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: SAMSUNG: Use spin_lock_{irqsave,irqrestore} in clk_set_rate
Ping !
On 09/07/2012 11:38 AM, Tushar Behera wrote:
> The spinlock clocks_lock can be held during ISR, hence it is not safe to
> hold that lock with disabling interrupts.
>
> It fixes following potential deadlock.
>
> =
> [ INFO: possible irq lock inversion dependency detected ]
> 3.6.0-rc4+ #2 Not tainted
> -
> swapper/0/1 just changed the state of lock:
> (&(&host->lock)->rlock){-.}, at: [] sdhci_irq+0x15/0x564
> but this lock took another, HARDIRQ-unsafe lock in the past:
> (clocks_lock){+.+...}
>
> and interrupts could create inverse lock ordering between them.
>
> other info that might help us debug this:
> Possible interrupt unsafe locking scenario:
>
>CPU0CPU1
>
> lock(clocks_lock);
>local_irq_disable();
>lock(&(&host->lock)->rlock);
>lock(clocks_lock);
>
> lock(&(&host->lock)->rlock);
>
> *** DEADLOCK ***
>
> Signed-off-by: Tushar Behera
> ---
> arch/arm/plat-samsung/clock.c |5 +++--
> 1 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
> index 65c5eca..9b71719 100644
> --- a/arch/arm/plat-samsung/clock.c
> +++ b/arch/arm/plat-samsung/clock.c
> @@ -144,6 +144,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
>
> int clk_set_rate(struct clk *clk, unsigned long rate)
> {
> + unsigned long flags;
> int ret;
>
> if (IS_ERR(clk))
> @@ -159,9 +160,9 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
> if (clk->ops == NULL || clk->ops->set_rate == NULL)
> return -EINVAL;
>
> - spin_lock(&clocks_lock);
> + spin_lock_irqsave(&clocks_lock, flags);
> ret = (clk->ops->set_rate)(clk, rate);
> - spin_unlock(&clocks_lock);
> + spin_unlock_irqrestore(&clocks_lock, flags);
>
> return ret;
> }
>
--
Tushar Behera
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RE: [PATCH] ARM: SAMSUNG: Add missing variable declaration in s3c64xx_spi1_set_platdata()
Sylwester Nawrocki wrote:
>
> Fixes regression introduced in commit 4d0efdd5889b1c81a62aa07a
> "ARM: SAMSUNG: Modify s3c64xx_spi{0|1|2}_set_platdata function"
>
> Signed-off-by: Sylwester Nawrocki
> Signed-off-by: Kyungmin Park
> ---
> arch/arm/plat-samsung/devs.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
> index fc49f3d..2195209 100644
> --- a/arch/arm/plat-samsung/devs.c
> +++ b/arch/arm/plat-samsung/devs.c
> @@ -1591,6 +1591,8 @@ struct platform_device s3c64xx_device_spi1 = {
> void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int
> src_clk_nr,
> int num_cs)
> {
> + struct s3c64xx_spi_info pd;
> +
> /* Reject invalid configuration */
> if (!num_cs || src_clk_nr < 0) {
> pr_err("%s: Invalid SPI configuration\n", __func__);
> --
> 1.7.11.3
Applied, thanks.
Best regards,
Kgene.
--
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SW Solution Development Team, Samsung Electronics Co., Ltd.
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RE: [PATCH] spi: s3c64xx: Don't free controller_data on non-dt platforms
Sylwester Nawrocki wrote: > > When s3c64xx-spi is instantiated from device tree an instance of > struct s3c64xx_spi_csinfo is dynamically allocated in the driver. > For non-dt platform it is passed from board code through > spi_register_board_info(). On error path in s3c64xx_spi_setup() > function there is an attempt to free this data struct > s3c64xx_spi_csinfo object as it would have been allocated in the > driver for both, dt and non-dt based platforms. This leads to > following bug when gpio request fails: > > spi spi1.0: Failed to get /CS gpio [21]: -16 > kernel BUG at mm/slub.c:3478! > Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM > Modules linked in: > CPU: 0Not tainted (3.6.0-rc5-00092-g9b0b493-dirty #6111) > PC is at kfree+0x148/0x158 > LR is at s3c64xx_spi_setup+0xac/0x290 > pc : []lr : []psr: 4013 > sp : ee043e10 ip : c032883c fp : c0481f7c > r10: ee0abd80 r9 : 0063 r8 : > r7 : ee129e78 r6 : ee104a00 r5 : fff0 r4 : c047bc64 > r3 : 4400 r2 : c047bc64 r1 : c04def60 r0 : 0004047b > Flags: nZcv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel > Control: 10c5387d Table: 4000404a DAC: 0015 > Process swapper/0 (pid: 1, stack limit = 0xee0422f0) > Stack: (0xee043e10 to 0xee044000) > ... > [] (kfree+0x148/0x158) from [] > (s3c64xx_spi_setup+0xac/0x290) > [] (s3c64xx_spi_setup+0xac/0x290) from [] > (spi_setup+0x34/0x4c) > [] (spi_setup+0x34/0x4c) from [] > (spi_add_device+0x98/0x128) > [] (spi_add_device+0x98/0x128) from [] > (spi_new_device+0x74/0xa8) > [] (spi_new_device+0x74/0xa8) from [] > (spi_match_master_to_boardinfo+0x24/0x44) > [] (spi_match_master_to_boardinfo+0x24/0x44) from [] > (spi_register_master+0xf4/0x2a8) > [] (spi_register_master+0xf4/0x2a8) from [] > (s3c64xx_spi_probe+0x34c/0x42c) > [] (s3c64xx_spi_probe+0x34c/0x42c) from [] > (platform_drv_probe+0x18/0x1c) > > There should be no attempt to kfree controller_data when it was > externally provided through the board code. Fix this by freeing > controller_data only when dev->of_node is not null. > > Signed-off-by: Sylwester Nawrocki > Signed-off-by: Kyungmin Park Yes, correct. Need to check it. Acked-by: Kukjin Kim Thanks. Best regards, Kgene. -- Kukjin Kim , Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2] ARM: EXYNOS5: Add bus clock and set parent clock for FIMD
On Wednesday, September 12, 2012 8:49 PM Leela Krishna Amudala wrote
>
> This patch adds the bus clock for FIMD and changes the device name for lcd
> clock
> also sets mout_mpll_user as parent clock to fimd
>
> Signed-off-by: Leela Krishna Amudala
> ---
> arch/arm/mach-exynos/clock-exynos5.c | 34 +++
> arch/arm/plat-samsung/include/plat/clock.h |2 +
> 2 files changed, 26 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
> b/arch/arm/mach-exynos/clock-exynos5.c
> index 774533c..205d19f 100644
> --- a/arch/arm/mach-exynos/clock-exynos5.c
> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> @@ -891,6 +891,13 @@ static struct clk exynos5_clk_mdma1 = {
[.]
>
> +struct clksrc_clk exynos5_clk_sclk_fimd = {
Replace 'exynos5_clk_sclk_fimd' with 'exynos5_clk_sclk_fimd1'.
This is because 'exynos5_clk_sclk_fimd0' can be added for other
Exynos5 SoCs later.
Best regards,
Jingoo Han
> + .clk= {
> + .name = "sclk_fimd",
> + .devname= "exynos5-fb.1",
> + .enable = exynos5_clksrc_mask_disp1_0_ctrl,
> + .ctrlbit= (1 << 0),
> + },
> + .sources = &exynos5_clkset_group,
> + .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
> + .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
> +};
> +
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RE: [PATCH 9/15] arch/arm/mach-s3c24xx/mach-h1940.c: removes unnecessary semicolon
Peter Senna Tschudin wrote:
>
> From: Peter Senna Tschudin
>
> removes unnecessary semicolon
>
> Found by Coccinelle: http://coccinelle.lip6.fr/
>
> Signed-off-by: Peter Senna Tschudin
>
> ---
> arch/arm/mach-s3c24xx/mach-h1940.c |2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-
> s3c24xx/mach-h1940.c
> index bb8d008..02ef7d5 100644
> --- a/arch/arm/mach-s3c24xx/mach-h1940.c
> +++ b/arch/arm/mach-s3c24xx/mach-h1940.c
> @@ -460,7 +460,7 @@ static void h1940_set_mmc_power(unsigned char
> power_mode, unsigned short vdd)
> break;
> default:
> break;
> - };
> + }
> }
>
> static struct s3c24xx_mci_pdata h1940_mmc_cfg __initdata = {
Applied, thanks.
K-Gene
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RE: [PATCH] arch/arm/mach-s3c24xx/mach-h1940.c: delete double assignment
Julia Lawall wrote: > > From: Julia Lawall > > Delete successive assignments to the same location. > > A simplified version of the semantic match that finds this problem is as > follows: (http://coccinelle.lip6.fr/) > > // > @@ > expression i; > @@ > > *i = ...; > i = ...; > // > > Signed-off-by: Julia Lawall > > --- > Not compiled, and this may change the behavior of the code. Without this > change, check_gpio2 could possibly be used uninitialized later. > > arch/arm/mach-s3c24xx/mach-h1940.c |2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach- > s3c24xx/mach-h1940.c > index bb8d008..48c 100644 > --- a/arch/arm/mach-s3c24xx/mach-h1940.c > +++ b/arch/arm/mach-s3c24xx/mach-h1940.c > @@ -380,7 +380,7 @@ int h1940_led_blink_set(unsigned gpio, int state, > default: > blink_gpio = S3C2410_GPA(3); > check_gpio1 = S3C2410_GPA(1); > - check_gpio1 = S3C2410_GPA(7); > + check_gpio2 = S3C2410_GPA(7); > break; > } > Applied, thanks. K-Gene -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 0/3] ARM: EXYNOS: Add generic PWM lookup support
> On Wed, Sep 12, 2012 at 05:03:29PM +0530, Sachin Kamat wrote: > > This series adds support for generic PWM framework which requires > > that the board setup code register a static mapping that can be > > used to match PWM consumers to providers. > > > > This series is based on for-next branch of Kukjin's tree. > > > > Sachin Kamat (2): > > ARM: EXYNOS: Add generic PWM lookup support for SMDK4X12 > > ARM: EXYNOS: Add generic PWM lookup support for SMDKV310 > > > > Tushar Behera (1): > > ARM: EXYNOS: Use generic pwm driver in Origen board > > > > arch/arm/mach-exynos/Kconfig |3 +++ > > arch/arm/mach-exynos/mach-origen.c |6 ++ > > arch/arm/mach-exynos/mach-smdk4x12.c |6 ++ > > arch/arm/mach-exynos/mach-smdkv310.c |7 +++ > > 4 files changed, 22 insertions(+), 0 deletions(-) > > These look great. I'm glad somebody's starting to convert boards to use > the lookup tables. Eventually when every board has been converted we can > transition to the new API by getting rid of pwm_request() and pwm_free() > in the user drivers and using only the counterparts from the new API. > Yeah, agree :-) > All three patches: Reviewed-by: Thanks, applied this series. K-Gene -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/2] DMA: PL330: Clock and runtime cleanup
On Fri, 2012-09-07 at 12:14 +0530, Inderpal Singh wrote: > The controller clock is being managed at AMBA bus level probe/remove and > pm_runtime/suspend functions. The existing driver does the clock > enable/disable > again in the same code paths, which unneccessarily increments the usage count > of > the clock for the same device. > > The following patches remove the redundant clock enable/disable from the > driver. Looks good, any tested by before I apply this.. Kukjin? > > Inderpal Singh (2): > DMA: PL330: Remove controller clock enable/disable > DMA: PL330: Remove redundant runtime_suspend/resume functions > > drivers/dma/pl330.c | 73 > --- > 1 file changed, 5 insertions(+), 68 deletions(-) > -- ~Vinod -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 0/2] ARM: EXYNOS: Set the capability of pdm0 and pdm1 as DMA_PRIVATE
On Fri, 2012-09-07 at 14:30 +0900, Kukjin Kim wrote: > Vinod Koul wrote: > > > > On Wed, 2012-08-29 at 10:16 +0530, Tushar Behera wrote: > > > DMA clients pdma0 and pdma1 are internal to the SoC and are used only > > > by dedicated peripherals. Since they cannot be used for generic > > > purpose, their capability should be set as DMA_PRIVATE. > > > > > > The patches are rebased on top of v3.6-rc3. > > Kukjin, if you ack them I can take thru my tree, other way round is fine > > with me too. > > Hi Vinod, > > Looks good to me, please pick them into your tree with my ack. > > Acked-by: Kukjin Kim Okay applied both. -- ~Vinod -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] s5p-csis: Add transmission errors logging
Add hardware event/error counters which can be dumped into the kernel
log through VIDIOC_LOG_STATUS ioctl. The counters are reset in each
s_stream(1) call. Any errors are logged after streaming is turned off.
Signed-off-by: Sylwester Nawrocki
Signed-off-by: Kyungmin Park
---
drivers/media/platform/s5p-fimc/mipi-csis.c | 159
1 file changed, 139 insertions(+), 20 deletions(-)
diff --git a/drivers/media/platform/s5p-fimc/mipi-csis.c
b/drivers/media/platform/s5p-fimc/mipi-csis.c
index 2f73d9e..3bfee3a 100644
--- a/drivers/media/platform/s5p-fimc/mipi-csis.c
+++ b/drivers/media/platform/s5p-fimc/mipi-csis.c
@@ -31,7 +31,7 @@
static int debug;
module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "Debug level (0-1)");
+MODULE_PARM_DESC(debug, "Debug level (0-2)");
/* Register map definition */
@@ -60,10 +60,38 @@ MODULE_PARM_DESC(debug, "Debug level (0-1)");
#define S5PCSIS_CFG_FMT_MASK (0x3f << 2)
#define S5PCSIS_CFG_NR_LANE_MASK 3
-/* Interrupt mask. */
+/* Interrupt mask */
#define S5PCSIS_INTMSK 0x10
-#define S5PCSIS_INTMSK_EN_ALL 0xf03f
+#define S5PCSIS_INTMSK_EN_ALL 0xf000103f
+#define S5PCSIS_INTMSK_EVEN_BEFORE (1 << 31)
+#define S5PCSIS_INTMSK_EVEN_AFTER (1 << 30)
+#define S5PCSIS_INTMSK_ODD_BEFORE (1 << 29)
+#define S5PCSIS_INTMSK_ODD_AFTER (1 << 28)
+#define S5PCSIS_INTMSK_ERR_SOT_HS (1 << 12)
+#define S5PCSIS_INTMSK_ERR_LOST_FS (1 << 5)
+#define S5PCSIS_INTMSK_ERR_LOST_FE (1 << 4)
+#define S5PCSIS_INTMSK_ERR_OVER(1 << 3)
+#define S5PCSIS_INTMSK_ERR_ECC (1 << 2)
+#define S5PCSIS_INTMSK_ERR_CRC (1 << 1)
+#define S5PCSIS_INTMSK_ERR_UNKNOWN (1 << 0)
+
+/* Interrupt source */
#define S5PCSIS_INTSRC 0x14
+#define S5PCSIS_INTSRC_EVEN_BEFORE (1 << 31)
+#define S5PCSIS_INTSRC_EVEN_AFTER (1 << 30)
+#define S5PCSIS_INTSRC_EVEN(0x3 << 30)
+#define S5PCSIS_INTSRC_ODD_BEFORE (1 << 29)
+#define S5PCSIS_INTSRC_ODD_AFTER (1 << 28)
+#define S5PCSIS_INTSRC_ODD (0x3 << 28)
+#define S5PCSIS_INTSRC_NON_IMAGE_DATA (0xff << 28)
+#define S5PCSIS_INTSRC_ERR_SOT_HS (0xf << 12)
+#define S5PCSIS_INTSRC_ERR_LOST_FS (1 << 5)
+#define S5PCSIS_INTSRC_ERR_LOST_FE (1 << 4)
+#define S5PCSIS_INTSRC_ERR_OVER(1 << 3)
+#define S5PCSIS_INTSRC_ERR_ECC (1 << 2)
+#define S5PCSIS_INTSRC_ERR_CRC (1 << 1)
+#define S5PCSIS_INTSRC_ERR_UNKNOWN (1 << 0)
+#define S5PCSIS_INTSRC_ERRORS 0xf03f
/* Pixel resolution */
#define S5PCSIS_RESOL 0x2c
@@ -93,6 +121,29 @@ enum {
ST_SUSPENDED= 4,
};
+struct s5pcsis_event {
+ u32 mask;
+ const char * const name;
+ unsigned int counter;
+};
+
+static const struct s5pcsis_event s5pcsis_events[] = {
+ /* Errors */
+ { S5PCSIS_INTSRC_ERR_SOT_HS,"SOT Error" },
+ { S5PCSIS_INTSRC_ERR_LOST_FS, "Lost Frame Start Error" },
+ { S5PCSIS_INTSRC_ERR_LOST_FE, "Lost Frame End Error" },
+ { S5PCSIS_INTSRC_ERR_OVER, "FIFO Overflow Error" },
+ { S5PCSIS_INTSRC_ERR_ECC, "ECC Error" },
+ { S5PCSIS_INTSRC_ERR_CRC, "CRC Error" },
+ { S5PCSIS_INTSRC_ERR_UNKNOWN, "Unknown Error" },
+ /* Non-image data receive events */
+ { S5PCSIS_INTSRC_EVEN_BEFORE, "Non-image data before even frame" },
+ { S5PCSIS_INTSRC_EVEN_AFTER,"Non-image data after even frame" },
+ { S5PCSIS_INTSRC_ODD_BEFORE,"Non-image data before odd frame" },
+ { S5PCSIS_INTSRC_ODD_AFTER, "Non-image data after odd frame" },
+};
+#define S5PCSIS_NUM_EVENTS ARRAY_SIZE(s5pcsis_events)
+
/**
* struct csis_state - the driver's internal state data structure
* @lock: mutex serializing the subdev and power management operations,
@@ -101,11 +152,14 @@ enum {
* @sd: v4l2_subdev associated with CSIS device instance
* @pdev: CSIS platform device
* @regs: mmaped I/O registers memory
+ * @supplies: CSIS regulator supplies
* @clock: CSIS clocks
* @irq: requested s5p-mipi-csis irq number
* @flags: the state variable for power and streaming control
* @csis_fmt: current CSIS pixel format
* @format: common media bus format for the source and sink pad
+ * @slock: spinlock protecting structure members below
+ * @events: MIPI-CSIS event (error) counters
*/
struct csis_state {
struct mutex lock;
@@ -119,6 +173,9 @@ struct csis_state {
u32 flags;
const struct csis_pix_format *csis_fmt;
struct v4l2_mbus_framefmt format;
+
+ struct spinlock slock;
+ struct s5pcsis_event events[S5PCSIS_NUM_EVENTS];
};
/**
@@ -292,17 +349,6 @@ err:
return -ENXIO;
}
-static int s5pcsis_s_power(struct v4l2_subdev *sd, int on)
-{
- struct csis_state *state = sd_to_csis_state(sd);
- struct device *dev = &state->pdev->dev;
-
- if (on)
- return pm_runtime_
[PATCH] spi: s3c64xx: Don't free controller_data on non-dt platforms
When s3c64xx-spi is instantiated from device tree an instance of struct s3c64xx_spi_csinfo is dynamically allocated in the driver. For non-dt platform it is passed from board code through spi_register_board_info(). On error path in s3c64xx_spi_setup() function there is an attempt to free this data struct s3c64xx_spi_csinfo object as it would have been allocated in the driver for both, dt and non-dt based platforms. This leads to following bug when gpio request fails: spi spi1.0: Failed to get /CS gpio [21]: -16 kernel BUG at mm/slub.c:3478! Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM Modules linked in: CPU: 0Not tainted (3.6.0-rc5-00092-g9b0b493-dirty #6111) PC is at kfree+0x148/0x158 LR is at s3c64xx_spi_setup+0xac/0x290 pc : []lr : []psr: 4013 sp : ee043e10 ip : c032883c fp : c0481f7c r10: ee0abd80 r9 : 0063 r8 : r7 : ee129e78 r6 : ee104a00 r5 : fff0 r4 : c047bc64 r3 : 4400 r2 : c047bc64 r1 : c04def60 r0 : 0004047b Flags: nZcv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel Control: 10c5387d Table: 4000404a DAC: 0015 Process swapper/0 (pid: 1, stack limit = 0xee0422f0) Stack: (0xee043e10 to 0xee044000) ... [] (kfree+0x148/0x158) from [] (s3c64xx_spi_setup+0xac/0x290) [] (s3c64xx_spi_setup+0xac/0x290) from [] (spi_setup+0x34/0x4c) [] (spi_setup+0x34/0x4c) from [] (spi_add_device+0x98/0x128) [] (spi_add_device+0x98/0x128) from [] (spi_new_device+0x74/0xa8) [] (spi_new_device+0x74/0xa8) from [] (spi_match_master_to_boardinfo+0x24/0x44) [] (spi_match_master_to_boardinfo+0x24/0x44) from [] (spi_register_master+0xf4/0x2a8) [] (spi_register_master+0xf4/0x2a8) from [] (s3c64xx_spi_probe+0x34c/0x42c) [] (s3c64xx_spi_probe+0x34c/0x42c) from [] (platform_drv_probe+0x18/0x1c) There should be no attempt to kfree controller_data when it was externally provided through the board code. Fix this by freeing controller_data only when dev->of_node is not null. Signed-off-by: Sylwester Nawrocki Signed-off-by: Kyungmin Park --- drivers/spi/spi-s3c64xx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index d1c8441f..7f75d4e 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -976,7 +976,8 @@ err_msgq: spi_set_ctldata(spi, NULL); err_gpio_req: - kfree(cs); + if (spi->dev.of_node) + kfree(cs); return err; } -- 1.7.11.3 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] video: exynos_dp: Add device tree support to DP driver
This patch enables device tree based discovery support for DP driver.
The driver is modified to handle platform data in both the cases:
with DT and non-DT.
DP-PHY should be regarded as a seperate device node while
being passed from device tree list, and device node for
DP should contain DP-PHY as child node with property name "dp-phy"
associated with it.
Signed-off-by: Ajay Kumar
---
drivers/video/exynos/exynos_dp_core.c | 156 +++--
drivers/video/exynos/exynos_dp_core.h |2 +
2 files changed, 151 insertions(+), 7 deletions(-)
diff --git a/drivers/video/exynos/exynos_dp_core.c
b/drivers/video/exynos/exynos_dp_core.c
index f57c915..15887bd 100644
--- a/drivers/video/exynos/exynos_dp_core.c
+++ b/drivers/video/exynos/exynos_dp_core.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
@@ -856,20 +857,117 @@ static irqreturn_t exynos_dp_irq_handler(int irq, void
*arg)
return IRQ_HANDLED;
}
+#ifdef CONFIG_OF
+struct exynos_dp_platdata *exynos_dp_dt_parse_pdata(struct device *dev)
+{
+ struct device_node *dp_node = dev->of_node;
+ struct exynos_dp_platdata *pd;
+ struct video_info *dp_video_config;
+
+ pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
+ if (!pd) {
+ dev_err(dev, "memory allocation for pdata failed\n");
+ return ERR_PTR(-ENOMEM);
+ }
+ dp_video_config = devm_kzalloc(dev,
+ sizeof(*dp_video_config), GFP_KERNEL);
+
+ if (!dp_video_config) {
+ dev_err(dev, "memory allocation for video config failed\n");
+ return ERR_PTR(-ENOMEM);
+ }
+ pd->video_info = dp_video_config;
+
+ if (of_get_property(dp_node, "samsung,h-sync-polarity", NULL))
+ dp_video_config->h_sync_polarity = 1;
+
+ if (of_get_property(dp_node, "samsung,v-sync-polarity", NULL))
+ dp_video_config->v_sync_polarity = 1;
+
+ if (of_get_property(dp_node, "samsung,interlaced", NULL))
+ dp_video_config->interlaced = 1;
+
+ of_property_read_u32(dp_node, "samsung,color_space",
+ &dp_video_config->color_space);
+
+ of_property_read_u32(dp_node, "samsung,dynamic_range",
+ &dp_video_config->dynamic_range);
+
+ of_property_read_u32(dp_node, "samsung,ycbcr_coeff",
+ &dp_video_config->ycbcr_coeff);
+
+ of_property_read_u32(dp_node, "samsung,color_depth",
+ &dp_video_config->color_depth);
+
+ of_property_read_u32(dp_node, "samsung,link_rate",
+ &dp_video_config->link_rate);
+
+ of_property_read_u32(dp_node, "samsung,lane_count",
+ &dp_video_config->lane_count);
+ return pd;
+}
+
+void exynos_dp_dt_parse_phydata(struct exynos_dp_device *dp)
+{
+ struct device_node *dp_phy_node;
+
+ const __be32 *parp;
+
+ u32 phy_base;
+
+ void *virt_phy_base;
+
+ parp = of_get_property(dp->dev->of_node, "dp_phy", NULL);
+ if (!parp) {
+ dp->dp_phy_addr = NULL;
+ return;
+ }
+
+ dp_phy_node = of_find_node_by_phandle(be32_to_cpup(parp));
+ if (!dp_phy_node) {
+ dp->dp_phy_addr = NULL;
+ return;
+ }
+
+ of_property_read_u32(dp_phy_node, "samsung,dptx_phy_reg", &phy_base);
+ of_property_read_u32(dp_phy_node, "samsung,enable_bit",
+ &dp->enable_bit);
+ virt_phy_base = ioremap(phy_base, SZ_4);
+ if (!virt_phy_base) {
+ dev_err(dp->dev, "failed to ioremap dp-phy\n");
+ dp->dp_phy_addr = NULL;
+ return;
+ }
+ dp->dp_phy_addr = virt_phy_base;
+}
+
+void dp_phy_init(struct exynos_dp_device *dp)
+{
+ u32 reg;
+
+ reg = __raw_readl(dp->dp_phy_addr);
+ reg |= dp->enable_bit;
+ __raw_writel(reg, dp->dp_phy_addr);
+}
+
+void dp_phy_exit(struct exynos_dp_device *dp)
+{
+ u32 reg;
+
+ reg = __raw_readl(dp->dp_phy_addr);
+ reg &= ~(dp->enable_bit);
+ __raw_writel(reg, dp->dp_phy_addr);
+}
+#endif /* CONFIG_OF */
+
static int __devinit exynos_dp_probe(struct platform_device *pdev)
{
struct resource *res;
struct exynos_dp_device *dp;
- struct exynos_dp_platdata *pdata;
+ struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
int ret = 0;
- pdata = pdev->dev.platform_data;
- if (!pdata) {
- dev_err(&pdev->dev, "no platform data\n");
- return -EINVAL;
- }
-
dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
GFP_KERNEL);
if (!dp) {
@@ -879,6 +982,19 @@ static int __devinit exynos_dp_probe(struct
platform_device *pdev)
dp->dev = &pdev->dev;
+
[PATCH] ARM: SAMSUNG: Add missing variable declaration in s3c64xx_spi1_set_platdata()
Fixes regression introduced in commit 4d0efdd5889b1c81a62aa07a
"ARM: SAMSUNG: Modify s3c64xx_spi{0|1|2}_set_platdata function"
Signed-off-by: Sylwester Nawrocki
Signed-off-by: Kyungmin Park
---
arch/arm/plat-samsung/devs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index fc49f3d..2195209 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -1591,6 +1591,8 @@ struct platform_device s3c64xx_device_spi1 = {
void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
int num_cs)
{
+ struct s3c64xx_spi_info pd;
+
/* Reject invalid configuration */
if (!num_cs || src_clk_nr < 0) {
pr_err("%s: Invalid SPI configuration\n", __func__);
--
1.7.11.3
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[RFC] [PATCH 2/2] ARM: EXYNOS4: CPUIDLE: Add C2 state
To enter into c2 state:
1. ARM should be off
2. All local power domains should be off
3. All IPs belonging to TOP domain should not be in use
In this state TOP domain remains in retention state.
Signed-off-by: Inderpal Singh
Signed-off-by: Chander Kashyap
Cc: Kisoo Yu
---
arch/arm/mach-exynos/cpuidle.c | 373 +++-
1 file changed, 364 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 5e489a7..7445088 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -23,8 +23,10 @@
#include
#include
#include
+#include
#include
+#include
#define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
@@ -33,7 +35,130 @@
S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
(S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
-#define S5P_CHECK_AFTR 0xFCBA0D10
+/* IROM/u-boot checks on this for LP mode */
+#define S5P_CHECK_LPM 0xFCBA0D10
+
+/* Pad Retention Bit mask */
+#define WAKEUP_FROM_LOWPOWER (0x1 << 28)
+
+/*
+ * Mask for IPs which needs to be checked before entering C2.
+ * These IPs do not fall under any local power domain.
+ */
+#define CLK_GATE_MDMA (0x1 << 2)
+#define CLK_GATE_SMMUMDMA (0x1 << 5)
+#define CLK_GATE_QEMDMA(0x1 << 8)
+#define LPA_IP_IMAGE_MASK (CLK_GATE_MDMA \
+| CLK_GATE_SMMUMDMA \
+| CLK_GATE_QEMDMA)
+
+#define CLK_GATE_PDMA0 (0x1 << 0)
+#define CLK_GATE_PDMA1 (0x1 << 1)
+#define CLK_GATE_TSI (0x1 << 4)
+#define CLK_GATE_MMC (0x1F << 5)
+#define CLK_GATE_ONENAND (0x1 << 15)
+#define CLK_GATE_NFCON (0x1 << 16)
+#define LPA_IP_FSYS_MASK (CLK_GATE_PDMA0 \
+| CLK_GATE_PDMA1 \
+| CLK_GATE_TSI \
+| CLK_GATE_MMC \
+| CLK_GATE_ONENAND \
+| CLK_GATE_NFCON)
+
+#define CLK_GATE_I2C (0xFF << 6)
+#define CLK_GATE_TSADC (0x1 << 15)
+#define CLK_GATE_SPI (0x7 << 16)
+#define CLK_GATE_I2S (0x3 << 20)
+#define CLK_GATE_PCM (0x3 << 22)
+#define CLK_GATE_SPDIF (0x1 << 26)
+#define CLK_GATE_AC97 (0x1 << 27)
+#define LPA_IP_PERIL_MASK (CLK_GATE_I2C \
+| CLK_GATE_TSADC \
+| CLK_GATE_SPI \
+| CLK_GATE_I2S \
+| CLK_GATE_PCM \
+| CLK_GATE_SPDIF \
+| CLK_GATE_AC97)
+
+#define CLK_GATE_WDT (0x1 << 14)
+#define CLK_GATE_KEYIF (0x1 << 16)
+#define LPA_IP_PERIR (CLK_GATE_WDT | CLK_GATE_KEYIF)
+
+/* GPIO Offsets */
+#define GPIO_BANK_OFFSET 0x20
+#define GPIO_PUD_OFFSET0x08
+#define GPIO_CON_PDN_OFFSET0x10
+#define GPIO_PUD_PDN_OFFSET0x14
+
+#define AFTR_MODE_INDEX1
+#define LPA_MODE_INDEX 2
+
+/* Host Controller reg offsets */
+#define HCCONTROL_OFFSET 0x4
+#define USBSTS_OFFSET 0x14
+#define DSTS_OFFSET0x808
+#define GOTGCTL_OFFSET 0
+
+static void __iomem *gpio_base1, *gpio_base2, *gpio_base3,
+ *ehci_usbsts, *ohci_hccontrol, *usbd_dsts, *usbd_gotgctl;
+
+/* Save the current register values */
+static struct sleep_save exynos4_lpa_save[] = {
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
+};
+
+static struct sleep_save exynos4210_lpa_save[] = {
+ SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
+};
+
+/* Default register values, need to be initialized before entering C2 */
+static struct sleep_save exynos4_set_clksrc[] = {
+ { .reg = EXYNOS4_CLKSRC_MASK_TOP, .val = 0x0001, },
+ { .reg = EXYNOS4_CLKSRC_MASK_CAM, .val = 0x, },
+ { .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x0111, },
+ { .reg = EXYNOS4_CLKSRC_MASK_LCD0 , .val = 0x, },
+ { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO , .val = 0x0001, },
+ { .reg = EXYNOS4_CLKSRC_MASK_FSYS , .val = 0x0101, },
+ { .reg = EXYNOS4_CLKSRC_MASK_PERIL0 , .val = 0x0111, },
+ { .reg = EXYNOS4_CLKSRC_MASK_PERIL1 , .val = 0x01110111, },
+ { .reg = EXYNOS4_CLKSRC_MASK_DMC, .val = 0x0001, },
+};
+
+static struct sleep_sav
[RFC] [PATCH 1/2] ARM: Exynos4: CPUIDLE: Add generic function for exynos4 cpuidle
Moved out the code from exynos4_enter_core0_aftr to a separate
function "exynos4_do_idle" in order to make it usable for other
idle states.
Also update the wakeup mask without touching reserved bits.
Signed-off-by: Inderpal Singh
Signed-off-by: Chander Kashyap
---
arch/arm/mach-exynos/cpuidle.c | 24 +++-
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index cff0595..5e489a7 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -60,9 +60,11 @@ static struct cpuidle_driver exynos4_idle_driver = {
};
/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
-static void exynos4_set_wakeupmask(void)
+static void exynos4_set_wakeupmask(int index)
{
- __raw_writel(0xff3e, S5P_WAKEUP_MASK);
+ unsigned long mask = __raw_readl(S5P_WAKEUP_MASK) & 0xFFF0;
+ if (index == 1)
+ __raw_writel(mask | 0xff3e, S5P_WAKEUP_MASK);
}
static unsigned int g_pwr_ctrl, g_diag_reg;
@@ -91,19 +93,17 @@ static int idle_finisher(unsigned long flags)
return 1;
}
-static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
+static void exynos4_do_idle(int index, int pd_conf, int lp_mode_magic)
{
unsigned long tmp;
- exynos4_set_wakeupmask();
+ exynos4_set_wakeupmask(index);
- /* Set value of power down register for aftr mode */
- exynos_sys_powerdown_conf(SYS_AFTR);
+ /* Set value of power down register for requested LP mode */
+ exynos_sys_powerdown_conf(pd_conf);
__raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
- __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
+ __raw_writel(lp_mode_magic, REG_DIRECTGO_FLAG);
save_cpu_arch_register();
@@ -136,7 +136,13 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device
*dev,
/* Clear wakeup state register */
__raw_writel(0x0, S5P_WAKEUP_STAT);
+}
+static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index)
+{
+ exynos4_do_idle(index, SYS_AFTR, S5P_CHECK_AFTR);
return index;
}
--
1.7.9.5
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[RFC] [PATCH 0/2] ARM: EXYNOS4: Add new cpuidle state
This patchset does following: Patch 1: Segregate and move common code to new function Patch 2: Adds C2 idle state It has been tested on Kukjin's for-next branch on Origen board. Chander Kashyap (2): ARM: Exynos4: CPUIDLE: Add generic function for exynos4 cpuidle ARM: EXYNOS4: CPUIDLE: Add C2 state arch/arm/mach-exynos/cpuidle.c | 385 ++-- 1 file changed, 373 insertions(+), 12 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/5] ARM: Add interface for registering and calling firmware-specific operations
On Thursday 13 of September 2012 10:13:35 Tomasz Figa wrote: > In code using firmware ops: > > __raw_writel(virt_to_phys(exynos4_secondary_startup), > CPU1_BOOT_REG); > > /* Call Exynos specific smc call */ > do_firmware_op(cpu_boot, cpu); Typo, s/do_/call_/ . Best regards, -- Tomasz Figa Samsung Poland R&D Center -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 5/5] ARM: EXYNOS: Add secure firmware support to secondary CPU bring-up
Boards using secure firmware must use different CPU boot registers and
call secure firmware to boot the CPU.
This is a follow-up on the patch by Kyungmin Park:
[PATCH v5 2/2] ARM: EXYNOS: SMC instruction (aka firmware) support
http://thread.gmane.org/gmane.linux.ports.arm.kernel/183608/focus=184109
Signed-off-by: Kyungmin Park
Signed-off-by: Tomasz Figa
---
arch/arm/mach-exynos/platsmp.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 816a27d..9d65b1b 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include
#include
@@ -43,6 +44,9 @@ static inline void __iomem *cpu_boot_reg_base(void)
static inline void __iomem *cpu_boot_reg(int cpu)
{
+ void __iomem *fw_boot_reg = call_firmware_op(cpu_boot_reg, cpu);
+ if (fw_boot_reg)
+ return fw_boot_reg;
if (soc_is_exynos4412())
return cpu_boot_reg_base() + 4*cpu;
return cpu_boot_reg_base();
@@ -151,6 +155,10 @@ int __cpuinit boot_secondary(unsigned int cpu, struct
task_struct *idle)
__raw_writel(virt_to_phys(exynos4_secondary_startup),
cpu_boot_reg(phys_cpu));
+
+ /* Call Exynos specific smc call */
+ call_firmware_op(cpu_boot, phys_cpu);
+
gic_raise_softirq(cpumask_of(cpu), 1);
if (pen_release == -1)
--
1.7.12
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[PATCH 4/5] ARM: EXYNOS: Add support for Exynos secure firmware
Some Exynos-based boards contain secure firmware and must use firmware
operations to set up some hardware.
This patch adds firmware operations for Exynos secure firmware and a way
for board code and device tree to specify that they must be used.
Example of use:
In board code:
...MACHINE_START(...)
/* ... */
.init_early = exynos_firmware_init,
/* ... */
MACHINE_END
In device tree:
/ {
/* ... */
firmware {
compatible = "samsung,secure-firmware";
};
/* ... */
};
This is a follow-up on the patch by Kyungmin Park:
[PATCH v5 2/2] ARM: EXYNOS: SMC instruction (aka firmware) support
http://thread.gmane.org/gmane.linux.ports.arm.kernel/183608/focus=184109
Signed-off-by: Kyungmin Park
Signed-off-by: Tomasz Figa
---
.../devicetree/bindings/arm/samsung-boards.txt | 8
arch/arm/mach-exynos/Makefile | 1 +
arch/arm/mach-exynos/common.h | 2 +
arch/arm/mach-exynos/firmware.c| 52 ++
arch/arm/mach-exynos/mach-exynos4-dt.c | 1 +
5 files changed, 64 insertions(+)
create mode 100644 arch/arm/mach-exynos/firmware.c
diff --git a/Documentation/devicetree/bindings/arm/samsung-boards.txt
b/Documentation/devicetree/bindings/arm/samsung-boards.txt
index 0bf68be..f447059 100644
--- a/Documentation/devicetree/bindings/arm/samsung-boards.txt
+++ b/Documentation/devicetree/bindings/arm/samsung-boards.txt
@@ -6,3 +6,11 @@ Required root node properties:
- compatible = should be one or more of the following.
(a) "samsung,smdkv310" - for Samsung's SMDKV310 eval board.
(b) "samsung,exynos4210" - for boards based on Exynos4210 SoC.
+
+Optional:
+- firmware node, specifying presence and type of secure firmware, currently
+supported value of compatible property is "samsung,secure-firmware":
+
+ firmware {
+ compatible = "samsung,secure-firmware";
+ };
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 997864b..9451637 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_EXYNOS4_MCT) += mct.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_ARCH_EXYNOS) += exynos-smc.o
+obj-$(CONFIG_ARCH_EXYNOS) += firmware.o
plus_sec := $(call as-instr,.arch_extension sec,+sec)
AFLAGS_exynos-smc.o:=-Wa,-march=armv7-a$(plus_sec)
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index d7f28ca..358f6a5 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -21,6 +21,8 @@ void exynos4_restart(char mode, const char *cmd);
void exynos5_restart(char mode, const char *cmd);
void exynos_init_late(void);
+void exynos_firmware_init(void);
+
#ifdef CONFIG_PM_GENERIC_DOMAINS
int exynos_pm_late_initcall(void);
#else
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
new file mode 100644
index 000..3f3641d
--- /dev/null
+++ b/arch/arm/mach-exynos/firmware.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics.
+ * Kyungmin Park
+ * Tomasz Figa
+ *
+ * This program is free software,you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+
+#include
+
+#include
+
+#include "smc.h"
+
+static int exynos_do_idle(void)
+{
+exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
+return 0;
+}
+
+static void exynos_cpu_boot(int cpu)
+{
+ exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
+}
+
+static void __iomem *exynos_cpu_boot_reg(int cpu)
+{
+ return S5P_VA_SYSRAM_NS + 0x1c + 4*cpu;
+}
+
+static const struct firmware_ops exynos_firmware_ops __initdata = {
+ .do_idle= exynos_do_idle,
+ .cpu_boot = exynos_cpu_boot,
+ .cpu_boot_reg = exynos_cpu_boot_reg,
+};
+
+void __init exynos_firmware_init(void)
+{
+ if (of_have_populated_dt() &&
+ !of_find_compatible_node(NULL, NULL, "samsung,secure-firmware"))
+ return;
+
+ pr_info("Running under secure firmware.\n");
+
+ register_firmware_ops(&exynos_firmware_ops);
+}
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c
b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 5c48c82..e0827b3 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -116,6 +116,7 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened
Device Tree)")
.init_irq = exynos4_init_irq,
.map_io = exynos4_dt_map_io,
.handle_irq = gic_handle_irq,
+ .init_early = exynos_firmware_init,
.init_machine = exynos4_dt_machine_init,
.init_late = exynos_init_late,
.t
[PATCH 3/5] ARM: EXYNOS: Add support for secure monitor calls
Some boards use secure monitor calls to communicate with secure
firmware.
This patch adds exynos_smc function which uses smc assembly instruction
to do secure monitor calls.
This is a follow-up on the patch by Kyungmin Park:
[PATCH v5 2/2] ARM: EXYNOS: SMC instruction (aka firmware) support
http://thread.gmane.org/gmane.linux.ports.arm.kernel/183608/focus=184109
Signed-off-by: Kyungmin Park
Signed-off-by: Tomasz Figa
---
arch/arm/mach-exynos/Makefile | 5 +
arch/arm/mach-exynos/exynos-smc.S | 22 ++
arch/arm/mach-exynos/smc.h| 31 +++
3 files changed, 58 insertions(+)
create mode 100644 arch/arm/mach-exynos/exynos-smc.S
create mode 100644 arch/arm/mach-exynos/smc.h
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index ee7fde9..997864b 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -30,6 +30,11 @@ obj-$(CONFIG_EXYNOS4_MCT)+= mct.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
+obj-$(CONFIG_ARCH_EXYNOS) += exynos-smc.o
+
+plus_sec := $(call as-instr,.arch_extension sec,+sec)
+AFLAGS_exynos-smc.o:=-Wa,-march=armv7-a$(plus_sec)
+
# machine support
obj-$(CONFIG_MACH_SMDKC210)+= mach-smdkv310.o
diff --git a/arch/arm/mach-exynos/exynos-smc.S
b/arch/arm/mach-exynos/exynos-smc.S
new file mode 100644
index 000..2e27aa3
--- /dev/null
+++ b/arch/arm/mach-exynos/exynos-smc.S
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics.
+ *
+ * Copied from omap-smc.S Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * This program is free software,you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+
+/*
+ * Function signature: void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3)
+ */
+
+ENTRY(exynos_smc)
+ stmfd sp!, {r4-r11, lr}
+ dsb
+ smc #0
+ ldmfd sp!, {r4-r11, pc}
+ENDPROC(exynos_smc)
diff --git a/arch/arm/mach-exynos/smc.h b/arch/arm/mach-exynos/smc.h
new file mode 100644
index 000..e972390
--- /dev/null
+++ b/arch/arm/mach-exynos/smc.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics.
+ *
+ * EXYNOS - SMC Call
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_EXYNOS_SMC_H
+#define __ASM_ARCH_EXYNOS_SMC_H
+
+#define SMC_CMD_INIT(-1)
+#define SMC_CMD_INFO(-2)
+/* For Power Management */
+#define SMC_CMD_SLEEP (-3)
+#define SMC_CMD_CPU1BOOT(-4)
+#define SMC_CMD_CPU0AFTR(-5)
+/* For CP15 Access */
+#define SMC_CMD_C15RESUME (-11)
+/* For L2 Cache Access */
+#define SMC_CMD_L2X0CTRL(-21)
+#define SMC_CMD_L2X0SETUP1 (-22)
+#define SMC_CMD_L2X0SETUP2 (-23)
+#define SMC_CMD_L2X0INVALL (-24)
+#define SMC_CMD_L2X0DEBUG (-25)
+
+extern void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3);
+
+#endif
--
1.7.12
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[PATCH 2/5] ARM: Add interface for registering and calling firmware-specific operations
Some boards are running with secure firmware running in TrustZone secure
world, which changes the way some things have to be initialized.
This patch adds an interface for platforms to specify available firmware
operations and call them.
A wrapper macro, call_firmware_op(), checks if the operation is provided
and calls it if so, otherwise returns 0.
By default no operations are provided.
This is a follow-up on the patch by Kyungmin Park:
[PATCH v5 1/2] ARM: Make a compile firmware conditionally
http://thread.gmane.org/gmane.linux.ports.arm.kernel/183607/focus=183988
Example of use:
In code using firmware ops:
__raw_writel(virt_to_phys(exynos4_secondary_startup),
CPU1_BOOT_REG);
/* Call Exynos specific smc call */
do_firmware_op(cpu_boot, cpu);
gic_raise_softirq(cpumask_of(cpu), 1);
In board-/platform-specific code:
static int platformX_do_idle(void)
{
/* tell platformX firmware to enter idle */
return 0;
}
static void platformX_cpu_boot(int i)
{
/* tell platformX firmware to boot CPU i */
}
static const struct firmware_ops platformX_firmware_ops __initdata = {
.do_idle= exynos_do_idle,
.cpu_boot = exynos_cpu_boot,
/* cpu_boot_reg not available on platformX */
};
static void __init board_init_early(void)
{
register_firmware_ops(&platformX_firmware_ops);
}
Signed-off-by: Kyungmin Park
Signed-off-by: Tomasz Figa
---
arch/arm/common/Makefile| 2 ++
arch/arm/common/firmware.c | 18 ++
arch/arm/include/asm/firmware.h | 30 ++
3 files changed, 50 insertions(+)
create mode 100644 arch/arm/common/firmware.c
create mode 100644 arch/arm/include/asm/firmware.h
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index e8a4e58..55d4182 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -2,6 +2,8 @@
# Makefile for the linux kernel.
#
+obj-y += firmware.o
+
obj-$(CONFIG_ARM_GIC) += gic.o
obj-$(CONFIG_ARM_VIC) += vic.o
obj-$(CONFIG_ICST) += icst.o
diff --git a/arch/arm/common/firmware.c b/arch/arm/common/firmware.c
new file mode 100644
index 000..27ddccb
--- /dev/null
+++ b/arch/arm/common/firmware.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics.
+ * Kyungmin Park
+ * Tomasz Figa
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+
+#include
+
+static const struct firmware_ops default_firmware_ops;
+
+const struct firmware_ops *firmware_ops = &default_firmware_ops;
diff --git a/arch/arm/include/asm/firmware.h b/arch/arm/include/asm/firmware.h
new file mode 100644
index 000..ed51b02
--- /dev/null
+++ b/arch/arm/include/asm/firmware.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics.
+ * Kyungmin Park
+ * Tomasz Figa
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_FIRMWARE_H
+#define __ASM_ARM_FIRMWARE_H
+
+struct firmware_ops {
+ int (*do_idle)(void);
+ void (*cpu_boot)(int cpu);
+ void __iomem *(*cpu_boot_reg)(int cpu);
+};
+
+extern const struct firmware_ops *firmware_ops;
+
+#define call_firmware_op(op, ...) \
+ ((firmware_ops->op) ? firmware_ops->op(__VA_ARGS__) : 0)
+
+static inline void register_firmware_ops(const struct firmware_ops *ops)
+{
+ firmware_ops = ops;
+}
+
+#endif
--
1.7.12
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[PATCH 1/5] ARM: EXYNOS: Add IO mapping for non-secure SYSRAM.
On TrustZone-enabled boards the non-secure SYSRAM is used for secondary
CPU bring-up, so add a mapping for it.
Signed-off-by: Tomasz Figa
---
arch/arm/mach-exynos/common.c| 34
arch/arm/mach-exynos/include/mach/map.h | 3 +++
arch/arm/plat-samsung/include/plat/map-s5p.h | 1 +
3 files changed, 38 insertions(+)
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 715b690..b87feac 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -214,6 +214,33 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
},
};
+static struct map_desc exynos4210_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
+static struct map_desc exynos4x12_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
+static struct map_desc exynos5250_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5_iodesc[] __initdata = {
{
.virtual= (unsigned long)S3C_VA_SYS,
@@ -321,6 +348,13 @@ static void __init exynos4_map_io(void)
else
iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
+ if (soc_is_exynos4210())
+ iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
+ if (soc_is_exynos4212() || soc_is_exynos4412())
+ iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
+ if (soc_is_exynos5250())
+ iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+
/* initialize device information early */
exynos4_default_sdhci0();
exynos4_default_sdhci1();
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index 51943f2..869d8a0 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -26,6 +26,9 @@
#define EXYNOS4_PA_SYSRAM0 0x02025000
#define EXYNOS4_PA_SYSRAM1 0x0202
#define EXYNOS5_PA_SYSRAM 0x0202
+#define EXYNOS4210_PA_SYSRAM_NS0x0203F000
+#define EXYNOS4x12_PA_SYSRAM_NS0x0204F000
+#define EXYNOS5250_PA_SYSRAM_NS0x0204F000
#define EXYNOS4_PA_FIMC0 0x1180
#define EXYNOS4_PA_FIMC1 0x1181
diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h
b/arch/arm/plat-samsung/include/plat/map-s5p.h
index c2d7bda..c186786 100644
--- a/arch/arm/plat-samsung/include/plat/map-s5p.h
+++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
@@ -22,6 +22,7 @@
#define S5P_VA_GPIO3 S3C_ADDR(0x0228)
#define S5P_VA_SYSRAM S3C_ADDR(0x0240)
+#define S5P_VA_SYSRAM_NS S3C_ADDR(0x0241)
#define S5P_VA_DMC0S3C_ADDR(0x0244)
#define S5P_VA_DMC1S3C_ADDR(0x0248)
#define S5P_VA_SROMC S3C_ADDR(0x024C)
--
1.7.12
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[PATCH 0/5] ARM: EXYNOS: Add secure firmware support
Some Exynos-based boards are running with secure firmware running in TrustZone secure world, which changes the way some things have to be initialized. This series adds support for specifying firmware operations, implements some firmware operations for Exynos secure firmware and adds a method of enabling secure firmware operations on Exynos-based boards through board file and device tree. This is a continuation of the patch series by Kyungmin Park: [PATCH v5 1/2] ARM: Make a compile firmware conditionally http://thread.gmane.org/gmane.linux.ports.arm.kernel/183607 [PATCH v5 2/2] ARM: EXYNOS: SMC instruction (aka firmware) support http://thread.gmane.org/gmane.linux.ports.arm.kernel/183608/focus=184109 Tomasz Figa (5): ARM: EXYNOS: Add IO mapping for non-secure SYSRAM. ARM: Add interface for registering and calling firmware-specific operations ARM: EXYNOS: Add support for secure monitor calls ARM: EXYNOS: Add support for Exynos secure firmware ARM: EXYNOS: Add secure firmware support to secondary CPU bring-up .../devicetree/bindings/arm/samsung-boards.txt | 8 arch/arm/common/Makefile | 2 + arch/arm/common/firmware.c | 18 arch/arm/include/asm/firmware.h| 30 + arch/arm/mach-exynos/Makefile | 6 +++ arch/arm/mach-exynos/common.c | 34 ++ arch/arm/mach-exynos/common.h | 2 + arch/arm/mach-exynos/exynos-smc.S | 22 + arch/arm/mach-exynos/firmware.c| 52 ++ arch/arm/mach-exynos/include/mach/map.h| 3 ++ arch/arm/mach-exynos/mach-exynos4-dt.c | 1 + arch/arm/mach-exynos/platsmp.c | 8 arch/arm/mach-exynos/smc.h | 31 + arch/arm/plat-samsung/include/plat/map-s5p.h | 1 + 14 files changed, 218 insertions(+) create mode 100644 arch/arm/common/firmware.c create mode 100644 arch/arm/include/asm/firmware.h create mode 100644 arch/arm/mach-exynos/exynos-smc.S create mode 100644 arch/arm/mach-exynos/firmware.c create mode 100644 arch/arm/mach-exynos/smc.h -- 1.7.12 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
