On 10 July 2013 04:27, Heiko Stübner he...@sntech.de wrote:
This series provides a clock driver for s3c2416, s3c2443 and s3c2450, which
share a common clock tree, but differ fundamentally from earlier s3c24xx
SoCs, and converts the mentioned SoCs to use it.
The clock driver itself follows the
This patch corrects the /include to #include on exynos5420
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
From: Andrew Bresticker abres...@chromium.org
This allows the input clocks to the Exynos AudioSS block to be specified
via device-tree bindings. Default names will be used when an input clock
is not given. This will be useful when adding support for the Exynos5420
where the audio bus clock is
From: Andrew Bresticker abres...@chromium.org
This adds device-tree bindings for the audio subsystem clock controller
on Exynos 5420.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Reviewed-on: https://gerrit.chromium.org/gerrit/57712
Reviewed-by: Simon Glass s...@chromium.org
From: Andrew Bresticker abres...@chromium.org
The AudioSS block on Exynos 5420 has an additional clock gate for the
ADMA bus clock.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Reviewed-on: https://gerrit.chromium.org/gerrit/57711
Reviewed-by: Simon Glass s...@chromium.org
---
Exynos5250 and Exynos5420 has 4 DMA controllers in common. So this patch
set moved the common nodes to exynos.dtsi keeping the clk info seperate
for both the platforms. Exynos5420 has a separate DMA controller for audio
IPs. So this patch set also adds the ADMA node on Exynos5420.
Padmavathi
exynos5250 and exynos5420 has 4 DMA controllers in common. So this patch
moves these nodes to common file keeping the dma controllers clk info in
the exynos5250 dtsi file.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5.dtsi| 44
Exynos5420 has one separate DMA controller for I2S0 and PCM0. This patch
adds the same node on exynos5420 dtsi and adds the DMA clk info for the
remaining DMA controllers.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 33
Hi,
On Friday 05 July 2013 01:59 PM, Jingoo Han wrote:
Exynos PCIe IP consists of Synopsys specific part and Exynos
specific part. Only core block is a Synopsys designware part;
other parts are Exynos specific.
Also, the Synopsys designware part can be shared with other
platforms; thus, it
On Wed, July 10, 2013, Doug Anderson wrote:
If the WAKEUP_INT is asserted at wakeup and not cleared, we'll end up
looping around forever. This has been seen to happen on exynos5420
silicon despite the fact that we haven't enabled any wakeup events.
Signed-off-by: Doug Anderson
Seungwon,
On Wed, Jul 10, 2013 at 7:54 AM, Seungwon Jeon tgih@samsung.com wrote:
On Wed, July 10, 2013, Doug Anderson wrote:
If the WAKEUP_INT is asserted at wakeup and not cleared, we'll end up
looping around forever. This has been seen to happen on exynos5420
silicon despite the fact
This series of patches addresses some suspend/resume problems with
dw_mmc on exynos platforms. Since suspend/resume is not fully working
on ToT Linux (3.10) on exynos5250-snow, this series was tested against
the current ToT ChromeOS 3.8 tree. I have confirmed basic booting
and eMMC / SD card
If the WAKEUP_INT is asserted at wakeup and not cleared, we'll end up
looping around forever. This has been seen to happen on exynos5420
silicon despite the fact that we haven't enabled any wakeup events.
Signed-off-by: Doug Anderson diand...@chromium.org
---
Changes in v3: None
Changes in v2:
-
Hi Heiko,
On Wed, Jul 10, 2013 at 4:27 AM, Heiko Stübner he...@sntech.de wrote:
All Samsung PLLs use similar code to register the clocks and clkdev lookups.
Therefore move these into a separate function to reduce code duplication.
Suggested-by: Russell King li...@arm.linux.org.uk
Hi Felipe,
This is intended to pull down a reset signal line, not to switch power
to the device. I could implement that with the regulator framework
too, but I think that would just be confusing and harder to understand
without providing any benefit. It's really just a plain old GPIO.
--
To
On Wednesday, July 10, 2013 9:34 AM, Julius Werner wrote:
This patch adds support for a new 'samsung,hsic-reset-gpio' in the
device tree, which will be interpreted as an active-low reset pin during
PHY initialization when it exists. Useful for intergrated HSIC devices
like an SMSC 3503 hub.
Hi Julius,
On Wed, Jul 10, 2013 at 2:42 PM, Julius Werner jwer...@chromium.org wrote:
Hi Felipe,
This is intended to pull down a reset signal line, not to switch power
to the device. I could implement that with the regulator framework
too, but I think that would just be confusing and harder
On Tue, Jul 9, 2013 at 12:09 PM, Doug Anderson diand...@chromium.org wrote:
Hi,
On Tue, Jul 9, 2013 at 10:31 AM, Doug Anderson diand...@chromium.org wrote:
If the WAKEUP_INT is asserted at wakeup and not cleared, we'll end up
looping around forever.
Signed-off-by: Doug Anderson
On Wednesday, July 10, 2013 11:02 PM, Kishon Vijay Abraham I:
On Friday 05 July 2013 01:59 PM, Jingoo Han wrote:
Exynos PCIe IP consists of Synopsys specific part and Exynos
specific part. Only core block is a Synopsys designware part;
other parts are Exynos specific.
Also, the Synopsys
Exynos PCIe IP consists of Synopsys specific part and Exynos
specific part. Only core block is a Synopsys designware part;
other parts are Exynos specific.
Also, the Synopsys designware part can be shared with other
platforms; thus, it can be split two parts such as Synopsys
designware part and
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