On Friday 15 November 2013 11:17 AM, Yuvaraj Kumar wrote:
On Thu, Nov 14, 2013 at 11:18 AM, Kishon Vijay Abraham I kis...@ti.com
wrote:
Hi,
On Monday 07 October 2013 07:35 PM, Yuvaraj Cd wrote:
On Tue, Oct 1, 2013 at 6:21 PM, Kishon Vijay Abraham I kis...@ti.com
wrote:
On Tuesday 01
On Tue, Nov 19, 2013 at 3:22 PM, Kishon Vijay Abraham I kis...@ti.com wrote:
On Friday 15 November 2013 11:17 AM, Yuvaraj Kumar wrote:
On Thu, Nov 14, 2013 at 11:18 AM, Kishon Vijay Abraham I kis...@ti.com
wrote:
Hi,
On Monday 07 October 2013 07:35 PM, Yuvaraj Cd wrote:
On Tue, Oct 1, 2013
On Tuesday 19 November 2013 03:42 PM, Yuvaraj Kumar wrote:
On Tue, Nov 19, 2013 at 3:22 PM, Kishon Vijay Abraham I kis...@ti.com wrote:
On Friday 15 November 2013 11:17 AM, Yuvaraj Kumar wrote:
On Thu, Nov 14, 2013 at 11:18 AM, Kishon Vijay Abraham I kis...@ti.com
wrote:
Hi,
On Monday 07
On Mon, Nov 18, 2013 at 07:04:50PM +, Christopher Covington wrote:
On 11/18/2013 12:30 PM, Catalin Marinas wrote:
[...]
You can't run legacy AArch32 code at EL3 and have lower levels in AArch64
mode (architectural constraint).
What prevents AArch32 code from running at EL3 and then
On Mon, Nov 18, 2013 at 05:52:36PM +, Stephen Warren wrote:
On 11/18/2013 10:30 AM, Catalin Marinas wrote:
On Mon, Nov 18, 2013 at 05:03:37PM +, Stephen Warren wrote:
On 11/18/2013 04:58 AM, Catalin Marinas wrote:
...
Of course, trusted foundations interface could be plugged into
On Tue, Nov 19, 2013 at 02:46:55AM +, Alex Courbot wrote:
On 11/18/2013 08:58 PM, Catalin Marinas wrote:
On Mon, Nov 18, 2013 at 03:05:59AM +, Alex Courbot wrote:
On 11/18/2013 12:59 AM, Catalin Marinas wrote:
On 17 November 2013 08:49, Alexandre Courbot acour...@nvidia.com wrote:
On Exynos5440 and Exynos5420 there are registers common
across the TMU channels.
To support that, we introduced a ADDRESS_MULTIPLE flag in the
driver and the 2nd set of register base and size are provided
in the reg property of the node.
As per Amit's suggestion, this patch changes the
Exynos5420 has 5 TMU channels, the TRIMINFO register is
misplaced for TMU channels 2, 3 and 4
TRIMINFO at 0x1006c000 contains data for TMU channel 3
TRIMINFO at 0x100a contains data for TMU channel 4
TRIMINFO at 0x10068000 contains data for TMU channel 2
This patch
1 Adds the neccessary
Exynos5420 SoC has per core thermal management unit.
5 TMU channels 4 for CPUs and 5th for GPU.
This patch adds the device tree nodes to the DT device list.
Nodes carry the misplaced second base address and the second
clock to access the misplaced base address.
Signed-off-by: Leela Krishna
Frequency lock should be considered in suspend/hibernation.
Signed-off-by: Jonghwan Choi jhbird.c...@samsung.com
---
drivers/cpufreq/exynos-cpufreq.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c
index f3c2287..cd05b0a
Frequency lock should be considered in suspend/hibernation.
Signed-off-by: Jonghwan Choi jhbird.c...@samsung.com
---
drivers/devfreq/exynos/exynos5_bus.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/devfreq/exynos/exynos5_bus.c
b/drivers/devfreq/exynos/exynos5_bus.c
index
On Tue, Nov 19, 2013 at 9:26 PM, Catalin Marinas
catalin.mari...@arm.com wrote:
On Tue, Nov 19, 2013 at 02:46:55AM +, Alex Courbot wrote:
On 11/18/2013 08:58 PM, Catalin Marinas wrote:
On Mon, Nov 18, 2013 at 03:05:59AM +, Alex Courbot wrote:
On 11/18/2013 12:59 AM, Catalin Marinas
On 19 November 2013 18:59, Jonghwan Choi jhbird.c...@gmail.com wrote:
Frequency lock should be considered in suspend/hibernation.
These could turn out to be important logs for future. Please write
with more effort..
Signed-off-by: Jonghwan Choi jhbird.c...@samsung.com
---
Hi,
Are you planning to add hibernation support to ARM?
If so then this should be stated somewhere in the patch description.
OTOH if you are not going to add hibernation support to ARM I see
a little sense in adding hibernation support to ARM-only drivers..
Best regards,
--
Bartlomiej
On Tue, Nov 19, 2013 at 02:29:39PM +, Alexandre Courbot wrote:
On Tue, Nov 19, 2013 at 9:26 PM, Catalin Marinas
catalin.mari...@arm.com wrote:
On Tue, Nov 19, 2013 at 02:46:55AM +, Alex Courbot wrote:
2) devices have already shipped with this firmware. Are we going to just
renounce
On Wed, Nov 20, 2013 at 12:07 AM, Catalin Marinas
catalin.mari...@arm.com wrote:
On Tue, Nov 19, 2013 at 02:29:39PM +, Alexandre Courbot wrote:
On Tue, Nov 19, 2013 at 9:26 PM, Catalin Marinas
catalin.mari...@arm.com wrote:
On Tue, Nov 19, 2013 at 02:46:55AM +, Alex Courbot wrote:
One of remaining limitations of current pinctrl-samsung driver was
the inability to parse multiple pinmux/pinconf group nodes grouped
inside a single device tree node. It made defining groups of pins for
single purpose, but with different parameters very inconvenient.
This patch implements
This patch extends the range of settings configurable via pinfunc API
to cover pin value as well. This allows configuration of default values
of pins.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
On 11/19/2013 10:15 AM, Tomasz Figa wrote:
This patch extends the range of settings configurable via pinfunc API
to cover pin value as well. This allows configuration of default values
of pins.
Shouldn't there be a driver that acquires the GPIO that's output to the
pin, and configures the
On Tue, Nov 19, 2013 at 10:46 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 11/19/2013 10:15 AM, Tomasz Figa wrote:
This patch extends the range of settings configurable via pinfunc API
to cover pin value as well. This allows configuration of default values
of pins.
Shouldn't there be a
On 11/19/2013 10:10 AM, Tomasz Figa wrote:
One of remaining limitations of current pinctrl-samsung driver was
the inability to parse multiple pinmux/pinconf group nodes grouped
inside a single device tree node. It made defining groups of pins for
single purpose, but with different parameters
On 11/19/2013 11:59 AM, Doug Anderson wrote:
On Tue, Nov 19, 2013 at 10:46 AM, Stephen Warren swar...@wwwdotorg.org
wrote:
On 11/19/2013 10:15 AM, Tomasz Figa wrote:
This patch extends the range of settings configurable via pinfunc API
to cover pin value as well. This allows configuration of
Quoting Bartlomiej Zolnierkiewicz (2013-11-19 06:50:05)
Hi,
Are you planning to add hibernation support to ARM?
If so then this should be stated somewhere in the patch description.
OTOH if you are not going to add hibernation support to ARM I see
a little sense in adding hibernation
.
[0.00] Booting Linux on physical CPU 0x0
[0.00] Initializing cgroup subsys cpuset
[0.00] Initializing cgroup subsys cpu
[0.00] Initializing cgroup subsys cpuacct
[0.00] Linux version 3.12.0-next-20131119-4-g27f3f5f-dirty
(tom3q@flatron) (gcc version 4.7.2
On Wed, Nov 20, 2013 at 4:16 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 11/19/2013 11:59 AM, Doug Anderson wrote:
On Tue, Nov 19, 2013 at 10:46 AM, Stephen Warren swar...@wwwdotorg.org
wrote:
On 11/19/2013 10:15 AM, Tomasz Figa wrote:
This patch extends the range of settings
On 11/19/2013 05:02 PM, Kyungmin Park wrote:
On Wed, Nov 20, 2013 at 4:16 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 11/19/2013 11:59 AM, Doug Anderson wrote:
On Tue, Nov 19, 2013 at 10:46 AM, Stephen Warren swar...@wwwdotorg.org
wrote:
On 11/19/2013 10:15 AM, Tomasz Figa wrote:
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