On 13 November 2013 17:51, Tomasz Figa tomasz.f...@gmail.com wrote:
On Wednesday 13 of November 2013 12:52:05 Bartlomiej Zolnierkiewicz wrote:
[+ DT maintainers]
Hi,
On Wednesday, November 13, 2013 11:27:03 AM Sylwester Nawrocki wrote:
On 13/11/13 09:08, Tomasz Figa wrote:
As was
On 12/10/2013 12:37 AM, Kukjin Kim wrote:
On 12/10/13 01:34, Tomasz Figa wrote:
Hi Vyacheslav, Tarek,
On Tuesday 26 of November 2013 12:58:06 Vyacheslav Tyrtov wrote:
From: Tarek Dakhrant.dakh...@samsung.com
The EXYNOS5410 clocks are statically listed and registered
using the Samsung
The DWC3-exynos eXtensible host controller on Exynos5420 SoC
is quirky in a way that the PHY needs to be tuned to get it
working at SuperSpeed.
Add relevant calls for tuning the PHY for DWC3-Exynos's
host controller, for that matter passing just USB3 PHY
from DWC3 core, which is saved in secondary
Adding phy tune callback, which facilitates tuning USB 3.0 PHY
present on Exynos5420.
Basically, Exynos5420 has 28nm PHY for which Loss-of-Signal (LOS)
Detector Threshold Level should be controlled for Super-Speed
operations. We are using CR_port for this purpose to send
required data to override
Hi Tomasz,
Am Montag, 9. Dezember 2013, 18:19:16 schrieb Tomasz Figa:
diff --git a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c index f50454a..0a86953 100644
--- a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
+++ b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
Some PHY controllers may need to tune PHY post-initialization,
so that the PHY consumers can call phy-tuning at appropriate
point of time.
Signed-off-by: vivek Gautam gautam.vi...@samsung.com
---
drivers/phy/phy-core.c | 20
include/linux/phy/phy.h |7 +++
2 files
The DWC3-exynos eXtensible host controller on Exynos5420 SoC
is quirky in a way that the PHY needs to be tuned to get it
working at SuperSpeed.
By default this PHY works as High-speed phy and therefore
detects even Super-speed devices as high-speed ones.
So, the PHY needs to be tuned after
The DWC3-exynos eXtensible host controller present on Exynos5420
SoC is quirky. The PHY serving this controller operates at High-Speed
by default, so it detects even Super-speed devices as high-speed ones.
This PHY needs to be tuned for its Tx LOS levels and Boost levels.
In this patch-set, we
From: Mark Brown broo...@linaro.org
Ensure that unused I2C controllers are not activated, causing problems due
to inappropriate pinmuxing or similar, by marking the controllers as
disabled by default and requiring boards to explicitly enable those that
are in use.
Signed-off-by: Mark Brown
From: Mark Brown broo...@linaro.org
Rather than requiring each board to explicitly disable the SPI controllers
it is not using instead require boards to enable those that they are using.
This is less work overall since normally at most one of the controllers is
in use and avoids issues caused by
From: Mark Brown broo...@linaro.org
These symbols are only referenced in this source file so can be made
static, and the efficiency table is constant data so can be declared as
such. This avoids polluting the global namespace and fixes warnings
from sparse.
The function arch_scale_freq_power()
From: Mark Brown broo...@linaro.org
Make it easier to notice the common file for ChromeOS devices based on
the Exynos5250 by giving it the exynos5250 prefix that the boards have.
Signed-off-by: Mark Brown broo...@linaro.org
Acked-by: Tomasz Figa t.f...@samsung.com
Reviewed-by: Doug Anderson
On Mon, Dec 09, 2013 at 04:57:01PM -0800, Doug Anderson wrote:
I'm a little surprised that I don't see removal of spi_0 on SMDK5250.
When I apply your patch to ToT Linux I still see this in
exynos5250-smdk5250.dts:
spi_0: spi@12d2 {
status = disabled;
};
Hi Heiko,
On Thursday 05 of December 2013 00:54:38 Heiko Stübner wrote:
Commit 60e93575476f (serial: samsung: enable clock before clearing pending
interrupts during init) added handling of the controller clock during init.
On most systems this clock is also one of the baud_clock sources and
Hi,
On Tue, Dec 10, 2013 at 04:25:25PM +0530, Vivek Gautam wrote:
@@ -170,6 +189,15 @@ static int xhci_plat_probe(struct platform_device *pdev)
}
/*
+ * The parent of the xhci-plat device may pass in a PHY via
+ * platform data. If it exists, store it in our struct
Hi,
On Tue, Dec 10, 2013 at 04:25:23PM +0530, Vivek Gautam wrote:
Some PHY controllers may need to tune PHY post-initialization,
so that the PHY consumers can call phy-tuning at appropriate
point of time.
Signed-off-by: vivek Gautam gautam.vi...@samsung.com
---
drivers/phy/phy-core.c |
From: Tarek Dakhran t.dakh...@samsung.com
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
From: Tarek Dakhran t.dakh...@samsung.com
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
arch/arm/boot/dts/Makefile
The series of patches represent support of Exynos 5410 SoC
The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture
Patches add new platform description, support of clock controller and device
tree for Exynos 5410.
Dual cluster support for Exynos 5410 (EDCS) has been removed
From: Tarek Dakhran t.dakh...@samsung.com
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Acked-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Vyacheslav Tyrtov
Next try, this time with less time between submissions.
Tested on both non-dt and dt s3c2416.
Changes since v3:
- address comments from Tomasz Figa (binding documentation, etc)
- prevent conflicts with unconverted s3c24xx socs
Changes since v2
- address comments from Tomasz Figa
- use new pll
The s3c2443 uses different plls that are not present yet. Therefore
add the two needed types.
Signed-off-by: Heiko Stuebner he...@sntech.de
Acked-by: Tomasz Figa t.f...@samsung.com
---
drivers/clk/samsung/clk-pll.c | 72 +
drivers/clk/samsung/clk-pll.h |
According to the manual s3c2416 and s3c2450 use a pll 6552 and 6553
and while the pll_6553 matches exactly the one already implemented
the pll_6552 differs to the one from the s3c64xx series.
The change is solely in the bit locations of the mdiv and pdiv values.
All calculations are the same for
The three SoCs share a common clock tree which only differs in the
existence of some special clocks.
As with all parts common to these three SoCs the driver is named
after the s3c2443, as it was the first SoC introducing this structure
and there exists no other label to describe this s3c24xx
Starting with the s3c2443 the s3c24xx series got a new clock tree
compared to the previous s3c24xx socs. This binding describes the
clock controller found in the s3c2443, s3c2416 and s3c2450 socs.
Signed-off-by: Heiko Stuebner he...@sntech.de
Acked-by: Tomasz Figa t.f...@samsung.com
---
As the conversion to the common-clock-framework is done in multiple
steps, it is necessary to prevent conflicts between the different
struct clk implementations.
For this include the s3c24xx_setup_clocks function only when
SAMSUNG_CLOCK is selected and make the socs we don't convert this
time
This adds the clock controller itself, the xti clock on the smdk2416
as well as the clock references in the individual device nodes.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
arch/arm/boot/dts/s3c2416-smdk2416.dts | 13 ++
arch/arm/boot/dts/s3c2416.dtsi | 42
This converts the mentioned platforms to use the newly introduced driver
for the common clock framework for them.
With this the whole legacy clock structure can go away too.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
arch/arm/mach-s3c24xx/Kconfig | 14 +-
Hi Heiko,
On Tuesday 10 of December 2013 16:14:29 Heiko Stübner wrote:
Next try, this time with less time between submissions.
Tested on both non-dt and dt s3c2416.
Changes since v3:
- address comments from Tomasz Figa (binding documentation, etc)
- prevent conflicts with unconverted
Hi Pankaj, Rahul, Arun,
In addition to issues already pointed by Sachin, please also see my
comments inline.
On Friday 06 of December 2013 21:26:25 Rahul Sharma wrote:
From: Pankaj Dubey pankaj.du...@samsung.com
This patch add basic arch side support for exynos5260 SoC.
Signed-off-by:
Hi Young-Gun, Pankaj, Rahul, Arun,
Please see my comments inline.
On Friday 06 of December 2013 21:26:26 Rahul Sharma wrote:
From: Young-Gun Jang yg1004.j...@samsung.com
Add Samsung Exynos5260 SoC specific data to enable pinctrl
support for all platforms based on EXYNOS5260.
[snip]
diff
Hi Arun,
Hi Lukasz,
Thank you for the review.
No problem.
On Mon, Dec 9, 2013 at 1:53 PM, Lukasz Majewski
l.majew...@samsung.com wrote:
Hi Arun,
From: Arjun.K.V arjun...@samsung.com
The patch adds cpufreq driver for exynos5420.
Signed-off-by: Arjun.K.V
Hi Mark,
On Mon, Dec 9, 2013 at 11:00 PM, Mark Brown broo...@kernel.org wrote:
On Fri, Dec 06, 2013 at 10:44:19AM +0530, Padma Venkat wrote:
I couldn't test this patch set due to some crash in recent kernel in
dmaengine_unmap_put. I think this unmap support is not yet implemented
for pl330
Vyacheslav Tyrtov v.tyr...@samsung.com writes:
The series of patches represent support of Exynos 5410 SoC
The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture
Patches add new platform description, support of clock controller and device
tree for Exynos 5410.
Dual
On Tue, Dec 10, 2013 at 10:09:05PM +0530, Padma Venkat wrote:
On Mon, Dec 9, 2013 at 11:00 PM, Mark Brown broo...@kernel.org wrote:
This is unfortunate... I'd suggest trying mainline but I see it's
broken in Linus' tree too and no fixes in -next. :(
I'm tempted to push up with your
Hi Pankaj, Rahul, Arun,
Please split generic SoC dtsi files and board dts files into separate
patches. Also please see my comments inline.
On Friday 06 of December 2013 21:26:27 Rahul Sharma wrote:
From: Arun Kumar K arun...@samsung.com
The patch adds the dts files for exynos5260 and for
On Tue, Dec 10, 2013 at 2:55 AM, Vivek Gautam gautam.vi...@samsung.com wrote:
The DWC3-exynos eXtensible host controller on Exynos5420 SoC
is quirky in a way that the PHY needs to be tuned to get it
working at SuperSpeed.
By default this PHY works as High-speed phy and therefore
detects even
On Tue, Dec 10, 2013 at 11:59:18AM +0530, Sachin Kamat wrote:
Added PMIC node to Arndale-Octa board.
Is there a bootloader posted for this anywhere yet?
+ regulators {
+ ldo1_reg: LDO1 {
+ regulator-name =
On Tuesday, December 10, 2013 8:07 PM, Mark Brown wrote:
From: Mark Brown broo...@linaro.org
These symbols are only referenced in this source file so can be made
static, and the efficiency table is constant data so can be declared as
such. This avoids polluting the global namespace and
Hi,
On Tue, Dec 10, 2013 at 7:31 PM, Heikki Krogerus
heikki.kroge...@linux.intel.com wrote:
Hi,
Thanks for reviewing this.
On Tue, Dec 10, 2013 at 04:25:23PM +0530, Vivek Gautam wrote:
Some PHY controllers may need to tune PHY post-initialization,
so that the PHY consumers can call
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