On 25.06.2014 15:50, Russell King - ARM Linux wrote:
On Wed, Jun 25, 2014 at 03:37:25PM +0200, Tomasz Figa wrote:
This series intends to add support for L2 cache on Exynos4 SoCs on boards
running under secure firmware, which requires certain initialization steps
to be done with help of
On 06/25/2014 03:57 AM, Kukjin Kim wrote:
Naveen Krishna Chatradhi wrote:
+ Jean Delvare, Guenter Roeck
I'm adding maintainers for drivers/hwmon/ntc* but I'm not sure.
Hi,
This series looks good to me. I will take 3/4 and 4/4 for exynos DT changes once
hwmon/ntc maintainer pick the others.
This patch moves PMU specific definitions into a new file
as exynos-pmu.h.
This will help in reducing dependency of common.h in pmu.c.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
---
arch/arm/mach-exynos/common.h | 17 -
arch/arm/mach-exynos/exynos-pmu.h | 31
This series is based on exynos-drm-next branch of Inki Dae's tree at:
git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git
Exynos SOC have a DISP1BLK register where we can select
the path for FIMD output. We can redirect the video data
directly to DP/MIPI interface, or we can pass
Add sysreg phandle to FIMD node so that we are able
to control DISP1BLK configuration in FIMD driver.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
On czw, 2014-06-19 at 20:20 +0200, Javier Martinez Canillas wrote:
Maxim Integrated Power Management ICs are very similar with
regard to their clock outputs. Most of the clock drivers for
these chips are duplicating code and are simpler enough that
can be converted to use a generic driver to
Exynos SOC have a DISP1BLK register where we can select
the path for FIMD output. We can redirect the video data
directly to DP/MIPI interface, or we can pass it via
image enhancement chips.
Since we don't use any image enhancement chips in exynos-drm,
we need to set FIMD BYPASS in DISP1BLK.
Add sysreg phandle to FIMD node so that we are able
to control DISP1BLK configuration in FIMD driver.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
arch/arm/boot/dts/exynos5250.dtsi |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
On czw, 2014-06-19 at 20:20 +0200, Javier Martinez Canillas wrote:
Clocks drivers for Maxim PMIC are very similar so they can
be converted to use the generic Maxim clock driver.
Also, while being there use module_platform_driver() helper
macro to eliminate more boilerplate code.
Hello Krzysztof,
On 06/25/2014 04:19 PM, Krzysztof Kozlowski wrote:
On czw, 2014-06-19 at 20:20 +0200, Javier Martinez Canillas wrote:
Maxim Integrated Power Management ICs are very similar with
regard to their clock outputs. Most of the clock drivers for
these chips are duplicating code and
On Wed, Jun 25, 2014 at 04:13:16PM +0200, Tomasz Figa wrote:
On 25.06.2014 15:50, Russell King - ARM Linux wrote:
On Wed, Jun 25, 2014 at 03:37:25PM +0200, Tomasz Figa wrote:
This series intends to add support for L2 cache on Exynos4 SoCs on boards
running under secure firmware, which
On 25.06.2014 16:37, Russell King - ARM Linux wrote:
On Wed, Jun 25, 2014 at 04:13:16PM +0200, Tomasz Figa wrote:
On 25.06.2014 15:50, Russell King - ARM Linux wrote:
On Wed, Jun 25, 2014 at 03:37:25PM +0200, Tomasz Figa wrote:
This series intends to add support for L2 cache on Exynos4 SoCs on
This patch extends the firmware_ops structure with two new callbacks:
.suspend() and .resume(). The former is intended to ask the firmware to
save all its volatile state and suspend the system, without returning
back to the kernel in between. The latter is to be called early by
very low level
On a numer of Exynos-based boards Linux kernel is running in non-secure
mode under a secure firmware. This means that certain operations need to
be handled in special way, with firmware assistance. System-wide
suspend/resume is an example of such operations.
This patch adds support for
On Exynos-based boards running secure firmware the sequence of low level
operations to enter and leave system-wide sleep mode is different than
on those without the firmware. Namely:
- CP15 power control and diagnostic registers cannot be written directly,
- the way of setting boot address and
Kukjin,
On Wed, Jun 25, 2014 at 4:13 AM, Kukjin Kim kgene@samsung.com wrote:
Doug Anderson wrote:
The original code for the exynos i2c controller registered for the
noirq variants. However during review feedback it was moved to
SIMPLE_DEV_PM_OPS without anyone noticing that it meant we
The original code for the exynos i2c controller registered for the
noirq variants. However during review feedback it was moved to
SIMPLE_DEV_PM_OPS without anyone noticing that it meant we were no
longer actually noirq (despite functions named
exynos5_i2c_suspend_noirq and
Naveen,
On Tue, Jun 24, 2014 at 10:04 PM, Naveen Krishna Ch
naveenkrishna...@gmail.com wrote:
Also, we have few similar nodes on Peach PI and Peach PIT.
Any plans or discussion on merging the common nodes ?
There was some discussion about this in another thread with Javier.
We were thinking
Hi,
On Wed, Jun 25, 2014 at 3:29 AM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Yes, the original Chrome OS 3.8 max77xxx also called the irq worker thread to
ack the interrupt.
So the real problem is that an interrupt occurs before the I2C bus controller
is
resumed and
Seungwon,
On Wed, Jun 25, 2014 at 4:18 AM, Seungwon Jeon tgih@samsung.com wrote:
+ case MMC_POWER_ON:
+ if (!IS_ERR(mmc-supply.vqmmc)
+ !test_bit(DW_MMC_IO_POWERED,
slot-flags)) {
You can use regulator_is_enabled() instead of flag
Seungwon,
On Wed, Jun 25, 2014 at 6:08 AM, Seungwon Jeon tgih@samsung.com wrote:
On Mon, June 23, 2014, Yuvaraj Kumar C D wrote:
Subject: [PATCH 3/3] mmc: dw_mmc: Support voltage changes
From: Doug Anderson diand...@chromium.org
For UHS cards we need the ability to switch voltages from
Sachin,
On Wed, Jun 25, 2014 at 3:02 AM, Sachin Kamat sachin.ka...@samsung.com wrote:
All Exynos5 platforms have HSI2C controllers and are needed by
various IPs connected to the boards based on these SoCs. Thus
select this by default for Exynos5 platforms.
Signed-off-by: Sachin Kamat
Javier,
On Thu, Jun 19, 2014 at 11:20 AM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
@@ -33,6 +38,6 @@ Example: Clock consumer node
foo@0 {
compatible = bar,foo;
/* ... */
- clock-names = my-clock;
-
Hello Doug,
On 06/25/2014 01:56 AM, Doug Anderson wrote:
From: Vincent Palatin vpala...@chromium.org
When the wake-up is triggered by the PMIC RTC, the RTC driver is trying
to read the PMIC interrupt status over I2C and fails because the I2C
controller is not resumed yet.
Let's resume the
On 06/25/2014 07:24 PM, Doug Anderson wrote:
Hi,
On Wed, Jun 25, 2014 at 3:29 AM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Yes, the original Chrome OS 3.8 max77xxx also called the irq worker thread to
ack the interrupt.
So the real problem is that an interrupt
Hello Doug,
Thanks a lot for your feedback.
On 06/25/2014 08:06 PM, Doug Anderson wrote:
Javier,
On Thu, Jun 19, 2014 at 11:20 AM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
@@ -33,6 +38,6 @@ Example: Clock consumer node
foo@0 {
compatible =
The MAX7802 PMIC has a Real-Time-Clock (RTC) with two alarms.
This patch adds support for the RTC and is based on a driver
added by Simon Glass to the Chrome OS kernel 3.8 tree.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v3: None
Clocks drivers for Maxim PMIC are very similar so they can
be converted to use the generic Maxim clock driver.
Also, while being there use module_platform_driver() helper
macro to eliminate more boilerplate code.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Some device drivers using the register map API need to copy the
value from one register to another. Even though it can be done
with a combination of regmap_read() and regmap_write(), it is
better to have a function to avoid code duplication and also it
sanity check and do it atomically by holding
Add Device Tree binding documentation for Maxim 77802 PMIC.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v3: None
Changes since v2:
- Explain better the Dynamic Voltage Scaling (DVS) support in some Buck
regulators and the
By using the generic IRQ support in the Register map API, it
is possible to get rid max77686-irq.c and simplify the code.
Suggested-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Acked-by: Lee Jones lee.jo...@linaro.org
This patch adds a dt-binding include for Maxim 77686
PMIC clock IDs that can be to be shared between the
clk-max77686 clock driver and DeviceTree source files.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
Like most clock drivers, the Maxim 77686 PMIC clock binding
follows the convention that the #clock-cells property is
used to specify the number of cells in a clock provider.
But the binding document is not clear enough that it shall
be set to 1 since the PMIC support multiple clocks outputs.
From: Doug Anderson diand...@chromium.org
The max77686 includes an RTC that keeps power during suspend. It's
convenient to be able to use it as a wakeup source.
NOTE: due to wakeup ordering problems this patch alone doesn't work so
well on exynos5250-snow. You also need something that brings
The MAX77802 PMIC has 10 high-efficiency Buck and 32 Low-dropout
(LDO) regulators. This patch adds support for all these regulators
found on the MAX77802 PMIC and is based on a driver added by Simon
Glass to the Chrome OS kernel 3.8 tree.
Signed-off-by: Javier Martinez Canillas
Javier,
On Wed, Jun 25, 2014 at 12:03 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Like most clock drivers, the Maxim 77686 PMIC clock binding
follows the convention that the #clock-cells property is
used to specify the number of cells in a clock provider.
But the
Naveen,
On Tue, Jun 24, 2014 at 11:29 PM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
Exynos5420 based Peach PIT board has 4 NTC thermistors to measure
temperatures at various points on the board.
IIO based ADC becomes the parent and NTC thermistors are the childs,
via the HWMON
On 6/25/2014 5:13 AM, Tushar Behera wrote:
On 06/25/2014 03:59 AM, Laura Abbott wrote:
On 6/24/2014 10:47 AM, Laura Abbott wrote:
On 6/23/2014 11:32 AM, Kevin Hilman wrote:
On Sun, Jun 22, 2014 at 8:56 PM, Tushar Behera trbli...@gmail.com wrote:
Adding linux-samsung-soc and linux-arm-kernel
Hi Marek, Daniel,
On 24.06.2014 13:47, Marek Szyprowski wrote:
Hello,
On 2014-06-19 14:43, Daniel Drake wrote:
On Tue, Jun 17, 2014 at 10:25 AM, Marek Szyprowski
m.szyprow...@samsung.com wrote:
This patch moves some parts of exynos4412-odroidx.dts to common
exynos4412-odroid-common.dtsi
On Wed, Jun 25, 2014 at 06:18:34PM +0200, Tomasz Figa wrote:
+static int exynos_suspend(void)
+{
+ /* Save Power control and Diagnostic registers */
+ asm (mrc p15, 0, %0, c15, c0, 0\n
+ mrc p15, 0, %1, c15, c0, 1\n
+ : =r (cp15_power), =r (cp15_diag) : : cc);
Specification and existing device trees use vsys-l{1,2}-supply,
not vsys_l{1,2}-supply. Fix the example to match the specification.
Reviewed-by: Doug Anderson diand...@chromium.org
Acked-by: Mark Rutland mark.rutl...@arm.com
Signed-off-by: Andreas Färber afaer...@suse.de
---
v1 - v2:
* More
Doug Anderson diand...@google.com writes:
Tushar,
On Tue, Jun 10, 2014 at 10:32 PM, Tushar Behera tusha...@samsung.com wrote:
Currently CLK_FOUT_EPLL was set as one of the parents of AUDSS mux.
As per the user manual, it should be CLK_MAU_EPLL.
The problem surfaced when the bootloader in
On 06/26/2014 01:18 AM, Tomasz Figa wrote:
This patch extends the firmware_ops structure with two new callbacks:
.suspend() and .resume(). The former is intended to ask the firmware to
save all its volatile state and suspend the system, without returning
back to the kernel in between. The latter
On Tue, Jun 24, 2014 at 3:57 PM, Doug Anderson diand...@google.com wrote:
Kevin,
On Tue, Jun 24, 2014 at 8:35 AM, Kevin Hilman khil...@linaro.org wrote:
- Leave mau_epll enabled
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/262259.html
Can you drop your mau_epll one and
On Thu, Jun 26, 2014 at 4:51 AM, Kevin Hilman khil...@linaro.org wrote:
Doug Anderson diand...@google.com writes:
Tushar,
On Tue, Jun 10, 2014 at 10:32 PM, Tushar Behera tusha...@samsung.com wrote:
Currently CLK_FOUT_EPLL was set as one of the parents of AUDSS mux.
As per the user manual,
Hello Sachin,
On 25 June 2014 16:19, Sachin Kamat spk.li...@gmail.com wrote:
Hi Naveen,
On Wed, Jun 25, 2014 at 4:08 PM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
This patch removes an extra line and fixes a styling nit
in exynos5_i2c_message_start()
Signed-off-by: Naveen
This patch removes an extra read of FIFO_STATUS register in the interrrupt
service routine. Which is read again before the actual use.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
Changes since v1:
None
drivers/i2c/busses/i2c-exynos5.c |1 -
1 file changed, 1
This patch does the following in exynos5_i2c_message_start() function
1. Fixes an assignment
As, i2c_auto_conf is initialized to '0' at the beginning of the
function and HSI2C_READ_WRITE is defined as (1u 16)
Using |= for the first assignment is more readable.
2. Removes an extra line
Adding regulators for HDMI for exynos5800 based Peach-pi board.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
Based on Kukjin's for-next branch.
Depends on:
1) PMIC addition to Peach-pi:
http://www.spinics.net/lists/linux-samsung-soc/msg33166.html
2) tps65090 addition to Peach-pi:
USB DWC3 driver on Exynos platforms does not work without its
corresponding phy driver. Hence it makes no sense to keep the
phy driver as user selectable. Instead select it from USB config
to make things easier for the end user.
While at it make the config depend on ARCH_EXYNOS5 instead of
EHCI and OHCI drivers on Exynos platforms do not work without their
corresponding SoC specific phy drivers. Hence it makes no sense to
keep these phy drivers as user selectable. Instead select them from
the respective USB configs to make things easier for the end user.
While at it enable 5250 phy
On Thu, Jun 26, 2014 at 5:24 AM, YoungJun Cho yj44@gmail.com wrote:
Hi Ajay,
I'm sorry for say that the patchset for exynos drm supporting I80 i/f
includes yours.
The patchset is still in reviewing and I'm preparing v5.
Please check this:
On 06/26/2014 11:09 AM, Sachin Kamat wrote:
EHCI and OHCI drivers on Exynos platforms do not work without their
corresponding SoC specific phy drivers. Hence it makes no sense to
keep these phy drivers as user selectable. Instead select them from
the respective USB configs to make things
On 06/26/2014 11:09 AM, Sachin Kamat wrote:
USB DWC3 driver on Exynos platforms does not work without its
corresponding phy driver. Hence it makes no sense to keep the
phy driver as user selectable. Instead select it from USB config
to make things easier for the end user.
While at it make the
Hi YoungJun,
On Thu, Jun 26, 2014 at 11:23 AM, Ajay kumar ajayn...@gmail.com wrote:
On Thu, Jun 26, 2014 at 5:24 AM, YoungJun Cho yj44@gmail.com wrote:
Hi Ajay,
I'm sorry for say that the patchset for exynos drm supporting I80 i/f
includes yours.
The patchset is still in reviewing and
101 - 155 of 155 matches
Mail list logo
