This patch adds the support for Exynos 64bit SoC. The delay_timer is only used
for Exynos 32bit SoC.
Cc: Daniel Lezcano daniel.lezc...@linaro.org
Cc: Thomas Gleixner t...@linutronix.de
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Signed-off-by: Chanwoo Choi
On 13/01/15 06:09, Linus Walleij wrote:
Hi Linus,
On Mon, Jan 12, 2015 at 7:26 PM, Marc Zyngier marc.zyng...@arm.com wrote:
IMX6 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This
On 12/01/15 19:00, Stefan Agner wrote:
Hi Marc,
On 2015-01-12 19:26, Marc Zyngier wrote:
IMX6 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT
On 01/14/2015 01:19 AM, Javier Martinez Canillas wrote:
I dug further on this issue and found that the cause is that the exynos_mixer
driver needs some clocks (CLK_HDMI and CLK_SCLK_HDMI) grabbed by exynos_hdmi
to be kept enabled after hdmi_poweroff (drivers/gpu/drm/exynos/exynos_hdmi.c).
On wto, 2015-01-13 at 00:20 +0530, Anand Moon wrote:
On enabling CONFIG_LOCKUP_DETECTOR the kernel to act as a watchdog
to detect hard and soft lockups. Enabling CONFIG_LOCKUP_DETECTOR
don't introduce much overhead on exyons SOC.
CONFIG_LOCKUP_DETECTOR is enabled on multi_v7_defconfig.
Dear Myungjoo,
On 01/13/2015 05:42 PM, MyungJoo Ham wrote:
This patch adds the generic exynos bus frequency driver for memory bus
with DEVFREQ framework. The Samsung Exynos SoCs have the common architecture
for memory bus between DRAM memory and MMC/sub IP in SoC. This driver can
support
On 01/13/2015 02:24 PM, Joonyoung Shim wrote:
Hi,
On 01/13/2015 01:09 AM, Javier Martinez Canillas wrote:
Hello Joonyoung,
On 01/12/2015 07:40 AM, Joonyoung Shim wrote:
And also making changes to the clocks in the clk-exynos5420 driver. Can
you please explain the rationale for those
Hi Eduardo,
On Mon, Jan 12, 2015 at 03:09:16PM +0100, Lukasz Majewski wrote:
Hi Eduardo,
Presented patch aims to move data necessary for correct CPU
cooling device configuration from exynos_tmu_data.c to device
tree.
I believe the patch title is misleading. Looks like
Acked-by: MyungJoo Ham myungjoo@samsung.com
Adding to Chanwoo's reply:
If I understand Chanwoo's intention correctly,
this patchset is to provide a common bus memory-interface DVFS driver
for several Exynos SoCs, which allows DT to express per-SoC hardware
details so that we do not need
Dear Myungjoo,
On 01/13/2015 05:42 PM, MyungJoo Ham wrote:
This patch adds the generic exynos bus frequency driver for memory bus
with DEVFREQ framework. The Samsung Exynos SoCs have the common architecture
for memory bus between DRAM memory and MMC/sub IP in SoC. This driver can
This patch adds the memory bus node for Exynos3250 SoC. Exynos3250 has
following memory buses to translate data between DRAM and eMMC/sub-IPs.
Following list specifies the detailed relation between memory bus clock and
DMC
IP in MIF (Memory Interface) block:
- DMC clock : DMC
This patch adds the generic exynos bus frequency driver for memory bus
with DEVFREQ framework. The Samsung Exynos SoCs have the common architecture
for memory bus between DRAM memory and MMC/sub IP in SoC. This driver can
support the memory bus frequency driver for Exynos SoCs.
Each
On 13 January 2015 at 11:53, Marek Szyprowski m.szyprow...@samsung.com wrote:
Hello,
On 2015-01-13 11:44, Ulf Hansson wrote:
On 13 January 2015 at 10:39, Marek Szyprowski m.szyprow...@samsung.com
wrote:
This patch adds support for making one power domain a sub-domain of
other domain.
From: Tomasz Stanislawski t.stanisl...@samsung.com
This patch adds configuration of hw modules required to enable HDMI
support on Universal C210 board.
Signed-off-by: Tomasz Stanislawski t.stanisl...@samsung.com
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
From: Andrzej Hajda a.ha...@samsung.com
The patch adds domain definition and references to it in appropriate devices.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
[mszyprow: rebased onto generic power domains dt bindings]
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
On 13 January 2015 at 10:39, Marek Szyprowski m.szyprow...@samsung.com wrote:
This patch adds support for making one power domain a sub-domain of
other domain. This is useful for modeling power dependences for devices
like TV Mixer or Camera ISP, which needs to have more than one power
domain
Hello,
On 2015-01-13 11:44, Ulf Hansson wrote:
On 13 January 2015 at 10:39, Marek Szyprowski m.szyprow...@samsung.com wrote:
This patch adds support for making one power domain a sub-domain of
other domain. This is useful for modeling power dependences for devices
like TV Mixer or Camera ISP,
Add required clk support for I2S,PCM amd SPDIF
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
.../devicetree/bindings/clock/exynos7-clock.txt|9 ++
drivers/clk/samsung/clk-exynos7.c | 143 +++-
include/dt-bindings/clock/exynos7-clk.h
Add clock support for 5 SPI channels.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
.../devicetree/bindings/clock/exynos7-clock.txt|5 ++
drivers/clk/samsung/clk-exynos7.c | 73
Add PDMA0,PDMA1 gate clock, required clks for 5 SPI channels and
for clks in audio block.
This patchset is dependent on usb clk support from Vivek in below link.
http://www.spinics.net/lists/linux-samsung-soc/msg39342.html
Changes since V1:
- Added documentation for source clks of
Add support for PDMA0 and PDMA1 gate clks.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
drivers/clk/samsung/clk-exynos7.c |4
include/dt-bindings/clock/exynos7-clk.h |4 +++-
2 files changed, 7 insertions(+),
Hello Joonyoung,
On 01/13/2015 09:40 AM, Joonyoung Shim wrote:
These are the changes I have now [0]. Please let me know what you think.
Good, it's working with your patch without u-boot changes and reverting
of commit 2ed127697eb.
But i also get stripe hdmi output if hdmi/mixer
Hi Padma,
On Fri, Dec 19, 2014 at 6:53 PM, Padmavathi Venna padm...@samsung.com wrote:
Add required clk support for I2S,PCM amd SPDIF
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
verified from Exynos7 datasheet. The patch looks good.
Reviewed-by: Vivek Gautam
On 01/13/2015 06:07 PM, MyungJoo Ham wrote:
Dear Myungjoo,
On 01/13/2015 05:42 PM, MyungJoo Ham wrote:
This patch adds the generic exynos bus frequency driver for memory bus
with DEVFREQ framework. The Samsung Exynos SoCs have the common
architecture
for memory bus between DRAM
This patch adds nodes specific to Exynos4412 based Odroid X/X2/U2/U3
boards required for enabling HDMI display.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 44 +
1 file changed, 44 insertions(+)
diff
This patch adds entries for HDMI, Mixer and i2c with hdmi-phy modules
found in Exynos 4210 and 4x12 SoCs.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
arch/arm/boot/dts/exynos4.dtsi| 40 +++
arch/arm/boot/dts/exynos4210.dtsi | 8
This patch adds support for making one power domain a sub-domain of
other domain. This is useful for modeling power dependences for devices
like TV Mixer or Camera ISP, which needs to have more than one power
domain enabled to be operational.
Based on previous work by Amit Daniel Kachhap
Hi all,
This is yet another approach to submit patches, which enables HDMI
support for two Exynos based platforms: UniversalC210 and Odroid X2/U3.
Beside DTS changes, this patchset adds parent domain support for Exynos
PM domains. This was the most controversial patch in the previous
attempts,
This patch adds the memory bus node for Exynos4x12 SoC. Exynos4x12 SoC has
two memory bus to translate data between DRAM and eMMC/sub-IPs.
Following list specifies the detailed relation between memory bus clock and
DMC
IP in MIF (Memory Interface) block:
- DMC/ACP clock : DMC
Hello Joonyoung,
On 01/13/2015 06:24 AM, Joonyoung Shim wrote:
Also, the SW_ACLK_300_DISP1 and USER_ACLK_300_DISP1 are needed for the FIMD
parent and input clock respectively. Adding those to the clocks list of the
DISP1 power domain gives me working display + HDMI on my Exynos5800 Peach Pi.
TV Mixer needs both TV and LCD0 domains enabled to be fully operational.
This dependency is modelled by making TV power domains a sub-domain of
LCD0 power domain.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
arch/arm/boot/dts/exynos4.dtsi | 1 +
1 file changed, 1 insertion(+)
On 12/01/15 10:43, Joonyoung Shim wrote:
+Cc Tomi Valkeinen,
Hi Uwe,
On 01/12/2015 04:50 PM, Uwe Kleine-König wrote:
Hello,
On Mon, Jan 12, 2015 at 11:53:02AM +0900, Joonyoung Shim wrote:
This is required in order to ensure that core system devices such as
voltage regulators attached
On Tue, Dec 3, 2013 at 10:00 PM, Sachin Kamat sachin.ka...@linaro.org wrote:
Hi Abhilash,
On 3 December 2013 20:16, Abhilash Kesavan kesavan.abhil...@gmail.com wrote:
Hi Yadwinder and Sachin,
CC'ing Doug and Andrew who have also worked on ASV.
I tested these patches on a 5250 Chromebook
On Fri, Jan 2, 2015 at 5:32 AM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
From: Bill Richardson wfric...@chromium.org
This patch adds a device interface to access the
Chrome OS Embedded Controller from user-space.
Signed-off-by: Bill Richardson wfric...@chromium.org
From: Kevin Hilman khil...@linaro.org
The odroid-xu3 has 4 INA231 current sensors on board which can be
accessed from the Linux via the hwmon interface.
There is one sensor for each of these power rails:
- A15 cluster: VDD_ARM
- A7 cluster: VDD_KFC
- GPU: VDD_G3D
- memory: VDD_MEM
In addition
Hello Joonyoung,
On 01/13/2015 06:24 AM, Joonyoung Shim wrote:
Yes, I was not able to trigger that by running modetest but by turning off
my HDMI monitor and then turning it on again. When the monitor is turned
on then I see a Power domain power-domain disable failed and the imprecise
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