Re: [PATCH 09/16] iommu/tegra-smmu: Make use of domain_alloc and domain_free
On Thu, Mar 26, 2015 at 01:43:12PM +0100, Joerg Roedel wrote: From: Joerg Roedel jroe...@suse.de Implement domain_alloc and domain_free iommu-ops as a replacement for domain_init/domain_destroy. Signed-off-by: Joerg Roedel jroe...@suse.de --- drivers/iommu/tegra-smmu.c | 41 +++-- 1 file changed, 23 insertions(+), 18 deletions(-) Acked-by: Thierry Reding tred...@nvidia.com pgpIvQf6VeP3T.pgp Description: PGP signature
Re: [PATCH 00/16 v2] iommu: Move domain allocation into drivers
On Thu, Mar 26, 2015 at 01:43:03PM +0100, Joerg Roedel wrote: Changes v1-v2: * Rebased to v4.0-rc5 * Converted domain-types to a bit-field Hi, here is patch-set to replace the existing domain_init and domain_destroy iommu-ops with the new domain_alloc and domain_free callbacks The new callbacks move the allocation of iommu domains into the iommu driver, allowing them to put a generic iommu_domain struct into their own domain struct. This makes domain handling in the drivers more cache efficient and prepares the introduction of default domains in another patch-set. While at it, this patch-set also introduces domain types. These are internal to the iommu core code for now, there are three of them: * DMA-API domains * Identity mapped domains * Domains unmanaged by the iommu-core, used for iommu-api so that the users can create their own mappings The patches have been compile tested for x86, ARM and PPC and runtime tested on x86 (Intel VT-d and AMD IOMMU). Please review. Thanks, Joerg Joerg Roedel (15): iommu: Introduce domain_alloc and domain_free iommu_ops iommu: Introduce iommu domain types iommu/amd: Make use of domain_alloc and domain_free iommu/vt-d: Make use of domain_alloc and domain_free iommu/omap: Make use of domain_alloc and domain_free iommu/arm-smmu: Make use of domain_alloc and domain_free iommu/exynos: Make use of domain_alloc and domain_free iommu/tegra-smmu: Make use of domain_alloc and domain_free iommu/tegra-gart: Make use of domain_alloc and domain_free iommu/msm: Make use of domain_alloc and domain_free iommu/shmobile: Make use of domain_alloc and domain_free iommu/ipmmu-vmsa: Make use of domain_alloc and domain_free iommu/rockchip: Make use of domain_alloc and domain_free iommu/fsl: Make use of domain_alloc and domain_free iommu: Remove domain_init and domain_free iommu_ops drivers/iommu/amd_iommu.c | 84 +-- drivers/iommu/amd_iommu_types.h | 7 ++-- drivers/iommu/arm-smmu.c| 46 +- drivers/iommu/exynos-iommu.c| 87 ++--- drivers/iommu/fsl_pamu_domain.c | 60 +++- drivers/iommu/fsl_pamu_domain.h | 2 +- drivers/iommu/intel-iommu.c | 48 +-- drivers/iommu/iommu.c | 20 ++ drivers/iommu/ipmmu-vmsa.c | 43 +++- drivers/iommu/msm_iommu.c | 73 +- drivers/iommu/omap-iommu.c | 49 +-- drivers/iommu/rockchip-iommu.c | 40 +++ drivers/iommu/shmobile-iommu.c | 40 +++ drivers/iommu/tegra-gart.c | 67 +-- drivers/iommu/tegra-smmu.c | 41 ++- include/linux/iommu.h | 17 ++-- 16 files changed, 407 insertions(+), 317 deletions(-) The core and Tegra bits: Tested-by: Thierry Reding tred...@nvidia.com pgpld3hZekpiI.pgp Description: PGP signature
Re: [PATCH] drm: Exynos: Respect framebuffer pitch for FIMD/Mixer
Hello Inki, On Fri, Mar 27, 2015 at 2:47 AM, Inki Dae inki@samsung.com wrote: Right, this is not documented but if you have ever checked exynos drm driver tree, then I think you could know how we use the prefix. Of course, I don't like to force the use of this prefix but if you and other people use prefix in the manner of them, exynos drm tree would be a little bit messy. i.e., DRM: EXYNOS, drm: exynos, drm: Exynos, drm/exynos, drm/exynos: fimd, drm: exynos: fimd, DRM: EXYNOS: FIMD, ... so many cases Do you really want this? So I will always say please, use right prefix Otherwise, I will change it while merging as is. And I see that other drm drivers have their own way which is not documented but just implicitly. I agree with you that people should follow the convention for subject lines used in a subsystem and that it is tedious to tell them to fix the subject and resend but I do agree with Tobias that you should rethink your mail filters. For example I've a filter for all the emails that are directly addressed to me or that I'm cc'ed to. It's true that you may get some emails that are not interesting to you just because people cc'ed you in random patches but I think is better to have false positives than to have false negatives. Specially since you are a kernel maintainer and people expect your feedback / ack for patches to get merged. Thanks, Inki Dae Best regards, Javier -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] ARM: EXYNOS: Fix failed second suspend on Exynos4
Dear Kukjin, How would you like to proceed? You did not respond to my email nor to Bartlomiej's questions. You questioned the soc_is_exynos(). I replied but there was no answer from you. My last reply: 2015-03-18 9:57 GMT+01:00 Krzysztof Kozlowski k.kozlow...@samsung.com: Probably of_machine_is_compatible() could be used here but such change should be done in separate patch. This is fix for wrong usage of use_delayed_assertion so it should not mix with other changes in the code. This fixes one thing at a time. Fixing many things in one patch often leads to new errors or difficulties in debugging. Bartlomiej's justification for it: 2015-03-18 11:29 GMT+01:00 Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com: Please use another way something like check ARM core rather than use 'soc_is_xxx()', as you know it is not acceptable now even it is just moving/modifying exist function though. Kukjin, could you please explain why 'soc_is_xxx()' usage inside arch/arm/mach-exynos/ code is not acceptable? I know that it should not be used outisde of this directory because of multiplatform support but what is wrong with using it for arch/arm/mach-exynos/ code? I'm also not sure if -rc4 is a desirable time to be doing such changes (especially given that the patch in question is moving an existing code, not adding new 'soc_is_xxx()' users). [ Moreover of_machine_is_compatible() can be sometimes harmful as could have been seen in commit ca489c58ef0b81 (ARM: EXYNOS: Don't use LDREX and STREX after disabling cache coherency fix. ] ... and more. As for the checking in LSI, I did not receive any answer. To summarize: Fixing this with this patch is an optimal way in my humble opinion because: 1. Fixes the problem. 2. Does not introduce regression. 3. Does not remove other features (reverting commits would do). 4. It was tested. 5. We are in late RC and second suspend-to-RAM still does not work. Reverting commits or developing some kind of new patch (which details you did not propose) is asking for some other troubles. Best regards, Krzysztof -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RESEND PATCH 2/2] ARM: EXYNOS: Handle of_find_device_by_node and kstrdup failures
Prevent possible NULL pointer dereference of pointer returned by
of_find_device_by_node(). Handle this by skipping such power domain.
Additionally fail the init on kstrdup() failure. Such case is actually
not fatal because the name for power domain allocated by kstrdup() is
used only in printk. Still as a precaution handle this as an error
condition.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
arch/arm/mach-exynos/pm_domains.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mach-exynos/pm_domains.c
b/arch/arm/mach-exynos/pm_domains.c
index 2c5c206f3ea9..b20d228566b9 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -126,6 +126,12 @@ static __init int exynos4_pm_init_power_domain(void)
struct device *dev;
pdev = of_find_device_by_node(np);
+ if (!pdev) {
+ pr_err(%s: failed to find device for node %s\n,
+ __func__, np-name);
+ of_node_put(np);
+ continue;
+ }
dev = pdev-dev;
pd = kzalloc(sizeof(*pd), GFP_KERNEL);
@@ -136,6 +142,12 @@ static __init int exynos4_pm_init_power_domain(void)
}
pd-pd.name = kstrdup(dev_name(dev), GFP_KERNEL);
+ if (!pd-pd.name) {
+ kfree(pd);
+ of_node_put(np);
+ return -ENOMEM;
+ }
+
pd-name = pd-pd.name;
pd-base = of_iomap(np, 0);
if (!pd-base) {
--
1.9.1
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[RESEND PATCH 1/2] ARM: EXYNOS: Handle of of_iomap() failure
Prevent possible NULL pointer dereference if of_iomap() fails. Handle
the error by skipping such power domain.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
arch/arm/mach-exynos/pm_domains.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-exynos/pm_domains.c
b/arch/arm/mach-exynos/pm_domains.c
index cbe56b35aea0..2c5c206f3ea9 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -138,6 +138,13 @@ static __init int exynos4_pm_init_power_domain(void)
pd-pd.name = kstrdup(dev_name(dev), GFP_KERNEL);
pd-name = pd-pd.name;
pd-base = of_iomap(np, 0);
+ if (!pd-base) {
+ dev_warn(pdev-dev, Failed to map memory\n);
+ kfree(pd);
+ of_node_put(np);
+ continue;
+ }
+
pd-pd.power_off = exynos_pd_power_off;
pd-pd.power_on = exynos_pd_power_on;
--
1.9.1
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Re: [PATCH 10/16] iommu/tegra-gart: Make use of domain_alloc and domain_free
On Thu, Mar 26, 2015 at 01:43:13PM +0100, Joerg Roedel wrote: From: Joerg Roedel jroe...@suse.de Implement domain_alloc and domain_free iommu-ops as a replacement for domain_init/domain_destroy. Signed-off-by: Joerg Roedel jroe...@suse.de --- drivers/iommu/tegra-gart.c | 67 +++--- 1 file changed, 46 insertions(+), 21 deletions(-) Acked-by: Thierry Reding tred...@nvidia.com pgpqhT7suGaYx.pgp Description: PGP signature
Re: [PATCH v2 Resend] pwm: samsung: Fix output race on disabling
Hi Sjoerd,
When disabling the samsung PWM the output state remains at the level
it was in the end of a pwm cycle. In other words, calling pwm_disable
when at 100% duty will keep the output active, while at all other
setting the output will go/stay inactive. On top of that the samsung
PWM settings are double-buffered, which means the new settings only
get applied at the start of a new PWM cycle.
This results in a race if the PWM is at 100% duty and a driver calls:
pwm_config (pwm, 0, period);
pwm_disable (pwm);
In this case the PWMs output will unexpectedly stay active, unless a
new PWM cycle happened to start between the register writes in
_config and _disable. As far as i can tell this is a regression
introduced by 3bdf878, before that a call to pwm_config would call
pwm_samsung_enable which, while heavy-handed, made sure the expected
settings were live.
To resolve this, while not re-introducing the issues 3bdf878
(flickering as the PWM got reset while in a PWM cycle). Only force an
update of the settings when at 100% duty, which shouldn't have a
noticeable effect on the output but is enough to ensure the behaviour
is as expected on disable.
Signed-off-by: Sjoerd Simons sjoerd.sim...@collabora.co.uk
---
Changes since v1:
Fix small issues pointed out by Tomasz Figa
- Correct various coding style issues
- Read the current value of the tcmp register for comparison rather
then using a non-trivial comparison to decide whether the current
state was 100% duty
- Move the code to force manual update out into its own function
- Clarify the comment indicating why a manual update is sometimes
required
drivers/pwm/pwm-samsung.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/pwm/pwm-samsung.c b/drivers/pwm/pwm-samsung.c
index 3e9b583..649f6c4 100644
--- a/drivers/pwm/pwm-samsung.c
+++ b/drivers/pwm/pwm-samsung.c
@@ -269,12 +269,31 @@ static void pwm_samsung_disable(struct pwm_chip
*chip, struct pwm_device *pwm)
spin_unlock_irqrestore(samsung_pwm_lock, flags); }
+static void pwm_samsung_manual_update(struct samsung_pwm_chip *chip,
+ struct pwm_device *pwm)
+{
+ unsigned int tcon_chan = to_tcon_channel(pwm-hwpwm);
+ u32 tcon;
+ unsigned long flags;
+
+ spin_lock_irqsave(samsung_pwm_lock, flags);
+
+ tcon = readl(chip-base + REG_TCON);
+ tcon |= TCON_MANUALUPDATE(tcon_chan);
+ writel(tcon, chip-base + REG_TCON);
+
+ tcon = ~TCON_MANUALUPDATE(tcon_chan);
+ writel(tcon, chip-base + REG_TCON);
+
+ spin_unlock_irqrestore(samsung_pwm_lock, flags);
+}
+
static int pwm_samsung_config(struct pwm_chip *chip, struct
pwm_device *pwm, int duty_ns, int period_ns)
{
struct samsung_pwm_chip *our_chip =
to_samsung_pwm_chip(chip); struct samsung_pwm_channel *chan =
pwm_get_chip_data(pwm);
- u32 tin_ns = chan-tin_ns, tcnt, tcmp;
+ u32 tin_ns = chan-tin_ns, tcnt, tcmp, oldtcmp;
/*
* We currently avoid using 64bit arithmetic by using the
@@ -288,6 +307,7 @@ static int pwm_samsung_config(struct pwm_chip
*chip, struct pwm_device *pwm, return 0;
tcnt = readl(our_chip-base + REG_TCNTB(pwm-hwpwm));
+ oldtcmp = readl(our_chip-base + REG_TCMPB(pwm-hwpwm));
/* We need tick count for calculation, not last tick. */
++tcnt;
@@ -335,6 +355,15 @@ static int pwm_samsung_config(struct pwm_chip
*chip, struct pwm_device *pwm, writel(tcnt, our_chip-base +
REG_TCNTB(pwm-hwpwm)); writel(tcmp, our_chip-base +
REG_TCMPB(pwm-hwpwm));
+ /* In case the PWM is currently at 100% duty, force a manual
update
+ * to prevent the signal staying high in the pwm is disabled
shortly
+ * afer this update (before it autoreloaded the new values) .
+ */
+ if (oldtcmp == (u32) -1) {
+ dev_dbg(our_chip-chip.dev, Forcing manual update);
+ pwm_samsung_manual_update(our_chip, pwm);
+ }
+
chan-period_ns = period_ns;
chan-tin_ns = tin_ns;
chan-duty_ns = duty_ns;
Acked-by: Lukasz Majewski l.majew...@samsung.com
--
Best regards,
Lukasz Majewski
Samsung RD Institute Poland (SRPOL) | Linux Platform Group
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[PATCH v2 1/3] ARM: EXYNOS: Handle of of_iomap() failure
Prevent possible NULL pointer dereference if of_iomap() fails. Handle
the error by skipping such power domain.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
Changes since v1:
1. Add missing kfree() of domain name (allocated with kstrdup()).
---
arch/arm/mach-exynos/pm_domains.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-exynos/pm_domains.c
b/arch/arm/mach-exynos/pm_domains.c
index cbe56b35aea0..14622b5f4481 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -138,6 +138,14 @@ static __init int exynos4_pm_init_power_domain(void)
pd-pd.name = kstrdup(dev_name(dev), GFP_KERNEL);
pd-name = pd-pd.name;
pd-base = of_iomap(np, 0);
+ if (!pd-base) {
+ dev_warn(pdev-dev, Failed to map memory\n);
+ kfree(pd-pd.name);
+ kfree(pd);
+ of_node_put(np);
+ continue;
+ }
+
pd-pd.power_off = exynos_pd_power_off;
pd-pd.power_on = exynos_pd_power_on;
--
1.9.1
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[PATCH v2 2/3] ARM: EXYNOS: Handle of_find_device_by_node and kstrdup failures
Prevent possible NULL pointer dereference of pointer returned by
of_find_device_by_node(). Handle this by skipping such power domain.
Additionally fail the init on kstrdup() failure. Such case is actually
not fatal because the name for power domain allocated by kstrdup() is
used only in printk. Still as a precaution handle this as an error
condition.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
Changes since v1:
None.
---
arch/arm/mach-exynos/pm_domains.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mach-exynos/pm_domains.c
b/arch/arm/mach-exynos/pm_domains.c
index 14622b5f4481..61c32ccc9f7a 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -126,6 +126,12 @@ static __init int exynos4_pm_init_power_domain(void)
struct device *dev;
pdev = of_find_device_by_node(np);
+ if (!pdev) {
+ pr_err(%s: failed to find device for node %s\n,
+ __func__, np-name);
+ of_node_put(np);
+ continue;
+ }
dev = pdev-dev;
pd = kzalloc(sizeof(*pd), GFP_KERNEL);
@@ -136,6 +142,12 @@ static __init int exynos4_pm_init_power_domain(void)
}
pd-pd.name = kstrdup(dev_name(dev), GFP_KERNEL);
+ if (!pd-pd.name) {
+ kfree(pd);
+ of_node_put(np);
+ return -ENOMEM;
+ }
+
pd-name = pd-pd.name;
pd-base = of_iomap(np, 0);
if (!pd-base) {
--
1.9.1
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[PATCH v2 3/3] ARM: EXYNOS: Add missing of_node_put() when parsing power domains
Add missing of_node_put() to:
1. Error return path if allocating memory for exynos_pm_domain failed.
2. Second iteration over power domains if a child domain was not present
or was incomplete.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Reported-by: Karol Wrona k.wr...@samsung.com
---
Changes since v1:
1. New patch.
---
arch/arm/mach-exynos/pm_domains.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos/pm_domains.c
b/arch/arm/mach-exynos/pm_domains.c
index 61c32ccc9f7a..1a90c5da2fd7 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -138,6 +138,7 @@ static __init int exynos4_pm_init_power_domain(void)
if (!pd) {
pr_err(%s: failed to allocate memory for domain\n,
__func__);
+ of_node_put(np);
return -ENOMEM;
}
@@ -209,15 +210,15 @@ no_clk:
args.args_count = 0;
child_domain = of_genpd_get_from_provider(args);
if (!child_domain)
- continue;
+ goto next_pd;
if (of_parse_phandle_with_args(np, power-domains,
#power-domain-cells, 0, args) != 0)
- continue;
+ goto next_pd;
parent_domain = of_genpd_get_from_provider(args);
if (!parent_domain)
- continue;
+ goto next_pd;
if (pm_genpd_add_subdomain(parent_domain, child_domain))
pr_warn(%s failed to add subdomain: %s\n,
@@ -225,6 +226,7 @@ no_clk:
else
pr_info(%s has as child subdomain: %s.\n,
parent_domain-name, child_domain-name);
+next_pd:
of_node_put(np);
}
--
1.9.1
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Re: [PATCH 1/3] drm/exynos: mixer: add 2x scaling to mixer_graph_buffer
Hi Tobias, 2015-03-27 Tobias Jakobi tjak...@math.uni-bielefeld.de: Hello! Gustavo Padovan wrote: I would keep calling these two vars x_ratio and y_ratio. I don't see a reason to change the name here. Right, I'm going to change this. Also I was thinking of basing the patch on your latest cleanup series (the 'drm/exynos: remove struct *_win_data abstraction on planes' one). If you can rebase this in on top of my series this would be really good. Then it would just be: static int mixer_setup_scale(const struct exynos_drm_plane *plane, unsigned int *x_ratio, unsigned int *y_ratio) Also that would automatically fix your other comment below [*]. Use EPERM or ENOTSUPP. Or even true/false. Will do! You need to fix style here if (mixer_setup_scale(win_data-src_width, win_data-src_height, win_data-crtc_width, win_data-crtc_height, x_ratio, y_ratio)) return; With [*] this would just be: if (mixer_setup_scale(plane, x_ratio, y_ratio)) return; What do you think? Changes sounds good to me. Please go ahead and send a new patch. :) Gustavo -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: exynos5800-peach-pi: suspend/resume (still) broken
Hello Abhilash,
On 03/20/2015 06:40 PM, Abhilash Kesavan wrote:
Regarding the mdma0 disablement, it looks like for the system to
suspend properly the mdma0 pclk needs to stay on.
I had time today again to work on this issue and the best
place I found to enable and disable the mdma0 clock is in
exynos5420_pm_{prepare,resume}. Please let me know if you
have a better idea of where the clock should be managed.
I'll send a RFC patch-set soon.
Regards,
Abhilash
Best regards,
Javier
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[RFC PATCH 2/2] ARM: EXYNOS: Make sure that the Exynos5420 MDMA0 clock is enabled during suspend
Commit ae43b3289186 (ARM: 8202/1: dmaengine: pl330: Add runtime Power
Management support v12) added pm support for the pl330 dma driver but
it makes the clock for the Exynos5420 MDMA0 DMA controller to be gated
during suspend and this clock needs to remain enabled in order to make
the system resume from a system suspend state.
To make sure that the clock is enabled during suspend, enable it prior
to entering a suspend state and disable it once the system has resumed.
Thanks to Abhilash Kesavan for figuring out that this was the issue.
Fixes: ae43b32 (ARM: 8202/1: dmaengine: pl330: Add runtime Power Management
support v12)
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
arch/arm/mach-exynos/suspend.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 1521eaf99265..6dbc0a6d1bb5 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -16,6 +16,7 @@
#include linux/init.h
#include linux/suspend.h
#include linux/syscore_ops.h
+#include linux/clk.h
#include linux/cpu_pm.h
#include linux/io.h
#include linux/irq.h
@@ -79,6 +80,7 @@ static const struct exynos_pm_data *pm_data;
static int exynos5420_cpu_state;
static unsigned int exynos_pmu_spare3;
+static struct clk *clk;
/*
* GIC wake-up support
@@ -374,6 +376,16 @@ static void exynos5420_pm_prepare(void)
{
unsigned int tmp;
+ /*
+* Exynos5420 requires the MDMA0 controller clock to be
+* ungated on suspend in order to be resumed correctly.
+*/
+ clk = clk_get(NULL, mdma0);
+ if (IS_ERR(clk))
+ pr_warn(Failed to get mdma0 clk (%ld)\n, PTR_ERR(clk));
+ else
+ clk_prepare_enable(clk);
+
/* Set wake-up mask registers */
exynos_pm_set_wakeup_mask();
@@ -516,6 +528,9 @@ static void exynos5420_pm_resume(void)
{
unsigned long tmp;
+ if (!IS_ERR_OR_NULL(clk))
+ clk_disable_unprepare(clk);
+
/* Restore the CPU0 low power state register */
tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
--
2.1.4
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[RFC PATCH 0/2] ARM: EXYNOS: Fix Suspend-to-RAM on Exynos5420
Hello, Suspend-to-RAM is currently not working. Abhilash Kesavan traced down to the MDMA0 DMA controller clock to be disabled during suspend and that it must stay enaled during suspend or the system is not able to resume. This series is an attempt to fix the issue and is composed of patches: Javier Martinez Canillas (2): clk: exynos5420: Add alias for MDMA0 controller clock ARM: EXYNOS: Make sure that the Exynos5420 MDMA0 clock is enabled during suspend arch/arm/mach-exynos/suspend.c | 15 +++ drivers/clk/samsung/clk-exynos5420.c | 2 +- 2 files changed, 16 insertions(+), 1 deletion(-) Patch #1 just adds an alias fo the MDMA0 clock so a lookup is registered. Patch #2 enables the MDMA0 clock before entering into a suspend state and disables it again once the system has been resumed. The patches are a RFC because I'm not sure if this is the best approach to solve the issue. So feedback will be highly appreciated. Best regards, Javier -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: exynos5800-peach-pi: suspend/resume (still) broken
Hello Abhilash,
On 03/27/2015 03:06 PM, Abhilash Kesavan wrote:
Hello Javier,
On Fri, Mar 27, 2015 at 6:59 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Hello Abhilash,
On 03/20/2015 06:40 PM, Abhilash Kesavan wrote:
Regarding the mdma0 disablement, it looks like for the system to
suspend properly the mdma0 pclk needs to stay on.
I had time today again to work on this issue and the best
place I found to enable and disable the mdma0 clock is in
exynos5420_pm_{prepare,resume}. Please let me know if you
have a better idea of where the clock should be managed.
Modifying exynos5420_clk_suspend in
drivers/clk/samsung/clk-exynos5420.c would be another way to go,
however I have not tested if this actually works.
Sorry, I just posted the series: [RFC PATCH 0/2] ARM: EXYNOS: Fix
Suspend-to-RAM on Exynos5420 before reading your email...
Please let me know if you think that is not the best appraoch and
I can come up with another one to modify the clk-exynos5420 suspend
and resume callbacks.
Another option is to use Lee Jone's clocks always on support [0]
that has been posted.
I'll send a RFC patch-set soon.
Thanks for the effort.
Thanks to you for all the help.
Regards,
Abhilash
Best regards,
Javier
[0]:
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-February/326616.html
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Re: [RFC PATCH 2/2] ARM: EXYNOS: Make sure that the Exynos5420 MDMA0 clock is enabled during suspend
2015-03-27 15:21 GMT+01:00 Javier Martinez Canillas
javier.marti...@collabora.co.uk:
Commit ae43b3289186 (ARM: 8202/1: dmaengine: pl330: Add runtime Power
Management support v12) added pm support for the pl330 dma driver but
it makes the clock for the Exynos5420 MDMA0 DMA controller to be gated
during suspend and this clock needs to remain enabled in order to make
the system resume from a system suspend state.
To make sure that the clock is enabled during suspend, enable it prior
to entering a suspend state and disable it once the system has resumed.
Thanks to Abhilash Kesavan for figuring out that this was the issue.
Fixes: ae43b32 (ARM: 8202/1: dmaengine: pl330: Add runtime Power Management
support v12)
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Hmmm... isn't a real problem elsewhere - like some clock hierarchy is
wrong or incomplete? This rather looks like workaround for the
problem.
---
arch/arm/mach-exynos/suspend.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 1521eaf99265..6dbc0a6d1bb5 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -16,6 +16,7 @@
#include linux/init.h
#include linux/suspend.h
#include linux/syscore_ops.h
+#include linux/clk.h
#include linux/cpu_pm.h
#include linux/io.h
#include linux/irq.h
@@ -79,6 +80,7 @@ static const struct exynos_pm_data *pm_data;
static int exynos5420_cpu_state;
static unsigned int exynos_pmu_spare3;
+static struct clk *clk;
/*
* GIC wake-up support
@@ -374,6 +376,16 @@ static void exynos5420_pm_prepare(void)
{
unsigned int tmp;
+ /*
+* Exynos5420 requires the MDMA0 controller clock to be
+* ungated on suspend in order to be resumed correctly.
+*/
+ clk = clk_get(NULL, mdma0);
+ if (IS_ERR(clk))
+ pr_warn(Failed to get mdma0 clk (%ld)\n, PTR_ERR(clk));
+ else
+ clk_prepare_enable(clk);
+
/* Set wake-up mask registers */
exynos_pm_set_wakeup_mask();
@@ -516,6 +528,9 @@ static void exynos5420_pm_resume(void)
{
unsigned long tmp;
+ if (!IS_ERR_OR_NULL(clk))
+ clk_disable_unprepare(clk);
+
Missing clk_put()
Best regards,
Krzysztof
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Re: exynos5800-peach-pi: suspend/resume (still) broken
Hello Javier,
On Fri, Mar 27, 2015 at 6:59 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Hello Abhilash,
On 03/20/2015 06:40 PM, Abhilash Kesavan wrote:
Regarding the mdma0 disablement, it looks like for the system to
suspend properly the mdma0 pclk needs to stay on.
I had time today again to work on this issue and the best
place I found to enable and disable the mdma0 clock is in
exynos5420_pm_{prepare,resume}. Please let me know if you
have a better idea of where the clock should be managed.
Modifying exynos5420_clk_suspend in
drivers/clk/samsung/clk-exynos5420.c would be another way to go,
however I have not tested if this actually works.
I'll send a RFC patch-set soon.
Thanks for the effort.
Regards,
Abhilash
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[RFC PATCH 1/2] clk: exynos5420: Add alias for MDMA0 controller clock
The MDMA0 controller clock needs to be enabled to allow the
system to be resumed when entering into a suspend state.
The clock is disabled as a part of the runtime pm for the
pl330 DMA driver so the system fails to resume. So to allow
the system to grab the clock and make sure that it stays
enabled during suspend, an alias has to be added so a clock
lookup for a clock is registered.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
drivers/clk/samsung/clk-exynos5420.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 07d666cc6a29..8b49e8b3b548 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -893,7 +893,7 @@ static struct samsung_div_clock exynos5x_div_clks[]
__initdata = {
static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = {
/* G2D */
- GATE(CLK_MDMA0, mdma0, aclk266_g2d, GATE_IP_G2D, 1, 0, 0),
+ GATE_A(CLK_MDMA0, mdma0, aclk266_g2d, GATE_IP_G2D, 1, 0, 0,
mdma0),
GATE(CLK_SSS, sss, aclk266_g2d, GATE_IP_G2D, 2, 0, 0),
GATE(CLK_G2D, g2d, aclk333_g2d, GATE_IP_G2D, 3, 0, 0),
GATE(CLK_SMMU_MDMA0, smmu_mdma0, aclk266_g2d, GATE_IP_G2D, 5, 0, 0),
--
2.1.4
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Re: [PATCH 1/1] Revert ARM: dts: add display power domain for exynos5250
2015-03-23 11:49 GMT+01:00 Javier Martinez Canillas javier.marti...@collabora.co.uk: This reverts commit 2d2c9a8d0a4f90e298315d2f4a282d8bd5d45e5c (ARM: dts: add display power domain for exynos5250). The mentioned commit added a domain definition for the DISP1 power domain and references to it in the appropriate devices but this change breaks the display in at least the Exynos5250 based Snow and Spring Chromebooks. On these machines, the boot-loader enables the DISP1 domain and before the mentioned commit, the kernel didn't know about it so the power domain remained always enabled. But after that commit when the exynos-dp probe is deferred, the DISP1 domain is powered off and on again but the exynos-dp driver fails to configure the video showing the following error: exynos-dp 145b.dp-controller: Timeout of video streamclk ok exynos-dp 145b.dp-controller: unable to config video The same issue happens when the display is turned off and on again using DPMS. So, it seems the DISP1 power domain definition is not complete since the display works with the initialization made by the boot loader but it does not work when the power domain is enabled by the kernel. Having the definition in the DTS makes the power domain to be powered on when needed and powered off when not needed which is better in terms of power consumption but for now is safer to just revert the commit to avoid adding a regression in some machines. Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk I looked at the DP and FIMD drivers and with great help of Andrzej Hajda found the issue: the FIMD driver does not enable DP clock (DP_MIE_CLKCON register). The process looks like: 1. Bootloader sets the DP_MIE_CLKCON to proper value. 2. FIMD is probed, DP power domain is on. 3. FIMD is deffered, DP power domain is turned off. 4. The FIMD registers are reset so DP clock is turned off. 5. DP driver is probed, DP power domain is turned on but clock is not enabled. I'll do some more testing and sent a patch for it till end of Monday so I think we should not revert this commit. Best regards, Krzysztof -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/1] Revert ARM: dts: add display power domain for exynos5250
Hello Krzysztof, On 03/27/2015 03:29 PM, Krzysztof Kozlowski wrote: 2015-03-23 11:49 GMT+01:00 Javier Martinez Canillas I looked at the DP and FIMD drivers and with great help of Andrzej Hajda found the issue: the FIMD driver does not enable DP clock (DP_MIE_CLKCON register). The process looks like: 1. Bootloader sets the DP_MIE_CLKCON to proper value. 2. FIMD is probed, DP power domain is on. 3. FIMD is deffered, DP power domain is turned off. 4. The FIMD registers are reset so DP clock is turned off. 5. DP driver is probed, DP power domain is turned on but clock is not enabled. Great! I knew it was some setup missing that was made by the boot-loader. I'll do some more testing and sent a patch for it till end of Monday so I think we should not revert this commit. Agree, I of course preferred to fix the actual cause instead of relying on the boot-loader to do the initialization but I wasn't able to figure it out so I posted this patch to revert the commit in the meantime. Best regards, Krzysztof Best regards, Javier -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH 2/2] ARM: EXYNOS: Make sure that the Exynos5420 MDMA0 clock is enabled during suspend
Hello Javier,
On 27/03/15 15:21, Javier Martinez Canillas wrote:
Commit ae43b3289186 (ARM: 8202/1: dmaengine: pl330: Add runtime Power
Management support v12) added pm support for the pl330 dma driver but
it makes the clock for the Exynos5420 MDMA0 DMA controller to be gated
during suspend and this clock needs to remain enabled in order to make
the system resume from a system suspend state.
To make sure that the clock is enabled during suspend, enable it prior
to entering a suspend state and disable it once the system has resumed.
Thanks to Abhilash Kesavan for figuring out that this was the issue.
Fixes: ae43b32 (ARM: 8202/1: dmaengine: pl330: Add runtime Power Management
support v12)
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
arch/arm/mach-exynos/suspend.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 1521eaf99265..6dbc0a6d1bb5 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -16,6 +16,7 @@
#include linux/init.h
#include linux/suspend.h
#include linux/syscore_ops.h
+#include linux/clk.h
#include linux/cpu_pm.h
#include linux/io.h
#include linux/irq.h
@@ -79,6 +80,7 @@ static const struct exynos_pm_data *pm_data;
static int exynos5420_cpu_state;
static unsigned int exynos_pmu_spare3;
+static struct clk *clk;
/*
* GIC wake-up support
@@ -374,6 +376,16 @@ static void exynos5420_pm_prepare(void)
{
unsigned int tmp;
+ /*
+ * Exynos5420 requires the MDMA0 controller clock to be
+ * ungated on suspend in order to be resumed correctly.
+ */
+ clk = clk_get(NULL, mdma0);
+ if (IS_ERR(clk))
+ pr_warn(Failed to get mdma0 clk (%ld)\n, PTR_ERR(clk));
I suppose you want this clk_get() call in exynos_pm_init(), now there
is clk_put() missing and this will cause a memory leak.
+ else
+ clk_prepare_enable(clk);
+
/* Set wake-up mask registers */
exynos_pm_set_wakeup_mask();
@@ -516,6 +528,9 @@ static void exynos5420_pm_resume(void)
{
unsigned long tmp;
+ if (!IS_ERR_OR_NULL(clk))
This should be just IS_ERR().
+ clk_disable_unprepare(clk);
+
/* Restore the CPU0 low power state register */
tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
--
Regards,
Sylwester
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Re: [RFC PATCH 2/2] ARM: EXYNOS: Make sure that the Exynos5420 MDMA0 clock is enabled during suspend
Hello Sylwester,
Thanks a lot for your feedback.
On 03/27/2015 03:36 PM, Sylwester Nawrocki wrote:
* GIC wake-up support
@@ -374,6 +376,16 @@ static void exynos5420_pm_prepare(void)
{
unsigned int tmp;
+/*
+ * Exynos5420 requires the MDMA0 controller clock to be
+ * ungated on suspend in order to be resumed correctly.
+ */
+clk = clk_get(NULL, mdma0);
+if (IS_ERR(clk))
+pr_warn(Failed to get mdma0 clk (%ld)\n, PTR_ERR(clk));
I suppose you want this clk_get() call in exynos_pm_init(), now there
Well I wanted to do it in an exynos5420 specific function to avoid
having an of_machine_is_compatible(samsung,exynos5420) but I can
move there if that is preferred.
is clk_put() missing and this will cause a memory leak.
duh, I wonder how I missed that. Thanks for pointing it out.
+else
+clk_prepare_enable(clk);
+
/* Set wake-up mask registers */
exynos_pm_set_wakeup_mask();
@@ -516,6 +528,9 @@ static void exynos5420_pm_resume(void)
{
unsigned long tmp;
+if (!IS_ERR_OR_NULL(clk))
This should be just IS_ERR().
Ok.
+clk_disable_unprepare(clk);
+
/* Restore the CPU0 low power state register */
tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
--
Regards,
Sylwester
Best regards,
Javier
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[RFT PATCHv2] drm/exynos: Enable DP clock to fix display on Exynos5250 and other
After adding display power domain for Exynos5250 in commit
2d2c9a8d0a4f (ARM: dts: add display power domain for exynos5250) the
display on Chromebook Snow and others stopped working after boot.
The reason for this suggested Andrzej Hajda: the DP clock was disabled.
This clock is required by Display Port and is enabled by bootloader.
However when FIMD driver probing was deferred, the display power domain
was turned off. This effectively reset the value of DP clock enable
register.
When exynos-dp is later probed, the clock is not enabled and display is
not properly configured:
exynos-dp 145b.dp-controller: Timeout of video streamclk ok
exynos-dp 145b.dp-controller: unable to config video
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Reported-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Fixes: 2d2c9a8d0a4f (ARM: dts: add display power domain for exynos5250)
Cc: sta...@vger.kernel.org
---
This should fix issue reported by Javier [1][2].
Tested on Chromebook Snow (Exynos 5250). More testing would be great,
especially on other Exynos 5xxx products.
[1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/43889
[2] http://thread.gmane.org/gmane.linux.ports.arm.kernel/400290
Changes since v1:
1. Added missing exynos_drm_fimd.h.
---
drivers/gpu/drm/exynos/exynos_dp_core.c | 10 ++
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 19 +++
drivers/gpu/drm/exynos/exynos_drm_fimd.h | 15 +++
include/video/samsung_fimd.h | 6 ++
4 files changed, 50 insertions(+)
create mode 100644 drivers/gpu/drm/exynos/exynos_drm_fimd.h
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
b/drivers/gpu/drm/exynos/exynos_dp_core.c
index bf17a60b40ed..1dbfba58f909 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -32,10 +32,16 @@
#include drm/bridge/ptn3460.h
#include exynos_dp_core.h
+#include exynos_drm_fimd.h
#define ctx_from_connector(c) container_of(c, struct exynos_dp_device, \
connector)
+static inline struct exynos_drm_crtc *dp_to_crtc(struct exynos_dp_device *dp)
+{
+ return to_exynos_crtc(dp-encoder-crtc);
+}
+
static inline struct exynos_dp_device *
display_to_dp(struct exynos_drm_display *d)
{
@@ -1070,6 +1076,8 @@ static void exynos_dp_poweron(struct exynos_dp_device *dp)
}
}
+ fimd_dp_clock_enable(dp_to_crtc(dp), true);
+
clk_prepare_enable(dp-clock);
exynos_dp_phy_init(dp);
exynos_dp_init_dp(dp);
@@ -1094,6 +1102,8 @@ static void exynos_dp_poweroff(struct exynos_dp_device
*dp)
exynos_dp_phy_exit(dp);
clk_disable_unprepare(dp-clock);
+ fimd_dp_clock_enable(dp_to_crtc(dp), false);
+
if (dp-panel) {
if (drm_panel_unprepare(dp-panel))
DRM_ERROR(failed to turnoff the panel\n);
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index c300e22da8ac..bdf0818dc8f5 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -32,6 +32,7 @@
#include exynos_drm_fbdev.h
#include exynos_drm_crtc.h
#include exynos_drm_iommu.h
+#include exynos_drm_fimd.h
/*
* FIMD stands for Fully Interactive Mobile Display and
@@ -1231,6 +1232,24 @@ static int fimd_remove(struct platform_device *pdev)
return 0;
}
+void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable)
+{
+ struct fimd_context *ctx = crtc-ctx;
+ u32 val;
+
+ /*
+* Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE
+* clock. On these SoCs the bootloader may enable it but any
+* power domain off/on will reset it to disable state.
+*/
+ if (ctx-driver_data != exynos5_fimd_driver_data)
+ return;
+
+ val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
+ writel(DP_MIE_CLK_DP_ENABLE, ctx-regs + DP_MIE_CLKCON);
+}
+EXPORT_SYMBOL_GPL(fimd_dp_clock_enable);
+
struct platform_driver fimd_driver = {
.probe = fimd_probe,
.remove = fimd_remove,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.h
b/drivers/gpu/drm/exynos/exynos_drm_fimd.h
new file mode 100644
index ..b4fcaa568456
--- /dev/null
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef _EXYNOS_DRM_FIMD_H_
+#define _EXYNOS_DRM_FIMD_H_
+
+extern void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable);
+
+#endif /* _EXYNOS_DRM_FIMD_H_ */
diff --git a/include/video/samsung_fimd.h
[PATCH] clk: samsung: exynos4: Disable ARMCLK down feature on Exynos4210 SoC
Commit 42773b28e71d (clk: samsung: exynos4: Enable ARMCLK
down feature) enabled ARMCLK down feature on all Exynos4
SoCs. Unfortunately on Exynos4210 SoC ARMCLK down feature
causes a lockup when ondemand cpufreq governor is used.
Fix it by limiting ARMCLK down feature to Exynos4x12 SoCs.
This patch was tested on:
- Exynos4210 SoC based Trats board
- Exynos4210 SoC based Origen board
- Exynos4412 SoC based Trats2 board
- Exynos4412 SoC based Odroid-U3 board
Cc: Krzysztof Kozlowski k.kozlow...@samsung.com
Cc: Daniel Drake dr...@endlessm.com
Cc: Tomasz Figa t.f...@samsung.com
Cc: Kukjin Kim kg...@kernel.org
Fixes: 42773b28e71d (clk: samsung: exynos4: Enable ARMCLK down feature)
Cc: sta...@vger.kernel.org # v3.17+
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 51462e8..714d6ba 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1354,7 +1354,7 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls]
__initdata = {
VPLL_LOCK, VPLL_CON0, NULL),
};
-static void __init exynos4_core_down_clock(enum exynos4_soc soc)
+static void __init exynos4x12_core_down_clock(void)
{
unsigned int tmp;
@@ -1373,11 +1373,9 @@ static void __init exynos4_core_down_clock(enum
exynos4_soc soc)
__raw_writel(tmp, reg_base + PWR_CTRL1);
/*
-* Disable the clock up feature on Exynos4x12, in case it was
-* enabled by bootloader.
+* Disable the clock up feature in case it was enabled by bootloader.
*/
- if (exynos4_soc == EXYNOS4X12)
- __raw_writel(0x0, reg_base + E4X12_PWR_CTRL2);
+ __raw_writel(0x0, reg_base + E4X12_PWR_CTRL2);
}
/* register exynos4 clocks */
@@ -1474,7 +1472,8 @@ static void __init exynos4_clk_init(struct device_node
*np,
samsung_clk_register_alias(ctx, exynos4_aliases,
ARRAY_SIZE(exynos4_aliases));
- exynos4_core_down_clock(soc);
+ if (soc == EXYNOS4X12)
+ exynos4x12_core_down_clock();
exynos4_clk_sleep_init();
samsung_clk_of_add_provider(np, ctx);
--
1.7.9.5
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[RFT PATCH] drm/exynos: Enable DP clock to fix display on Exynos5250 and other
After adding display power domain for Exynos5250 in commit
2d2c9a8d0a4f (ARM: dts: add display power domain for exynos5250) the
display on Chromebook Snow and others stopped working after boot.
The reason for this suggested Andrzej Hajda: the DP clock was disabled.
This clock is required by Display Port and is enabled by bootloader.
However when FIMD driver probing was deferred, the display power domain
was turned off. This effectively reset the value of DP clock enable
register.
When exynos-dp is later probed, the clock is not enabled and display is
not properly configured:
exynos-dp 145b.dp-controller: Timeout of video streamclk ok
exynos-dp 145b.dp-controller: unable to config video
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Reported-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Fixes: 2d2c9a8d0a4f (ARM: dts: add display power domain for exynos5250)
Cc: sta...@vger.kernel.org
---
This should fix issue reported by Javier [1][2].
Tested on Chromebook Snow (Exynos 5250). More testing would be great,
especially on other Exynos 5xxx products.
[1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/43889
[2] http://thread.gmane.org/gmane.linux.ports.arm.kernel/400290
---
drivers/gpu/drm/exynos/exynos_dp_core.c | 10 ++
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 19 +++
include/video/samsung_fimd.h | 6 ++
3 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
b/drivers/gpu/drm/exynos/exynos_dp_core.c
index bf17a60b40ed..1dbfba58f909 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -32,10 +32,16 @@
#include drm/bridge/ptn3460.h
#include exynos_dp_core.h
+#include exynos_drm_fimd.h
#define ctx_from_connector(c) container_of(c, struct exynos_dp_device, \
connector)
+static inline struct exynos_drm_crtc *dp_to_crtc(struct exynos_dp_device *dp)
+{
+ return to_exynos_crtc(dp-encoder-crtc);
+}
+
static inline struct exynos_dp_device *
display_to_dp(struct exynos_drm_display *d)
{
@@ -1070,6 +1076,8 @@ static void exynos_dp_poweron(struct exynos_dp_device *dp)
}
}
+ fimd_dp_clock_enable(dp_to_crtc(dp), true);
+
clk_prepare_enable(dp-clock);
exynos_dp_phy_init(dp);
exynos_dp_init_dp(dp);
@@ -1094,6 +1102,8 @@ static void exynos_dp_poweroff(struct exynos_dp_device
*dp)
exynos_dp_phy_exit(dp);
clk_disable_unprepare(dp-clock);
+ fimd_dp_clock_enable(dp_to_crtc(dp), false);
+
if (dp-panel) {
if (drm_panel_unprepare(dp-panel))
DRM_ERROR(failed to turnoff the panel\n);
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index c300e22da8ac..bdf0818dc8f5 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -32,6 +32,7 @@
#include exynos_drm_fbdev.h
#include exynos_drm_crtc.h
#include exynos_drm_iommu.h
+#include exynos_drm_fimd.h
/*
* FIMD stands for Fully Interactive Mobile Display and
@@ -1231,6 +1232,24 @@ static int fimd_remove(struct platform_device *pdev)
return 0;
}
+void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable)
+{
+ struct fimd_context *ctx = crtc-ctx;
+ u32 val;
+
+ /*
+* Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE
+* clock. On these SoCs the bootloader may enable it but any
+* power domain off/on will reset it to disable state.
+*/
+ if (ctx-driver_data != exynos5_fimd_driver_data)
+ return;
+
+ val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
+ writel(DP_MIE_CLK_DP_ENABLE, ctx-regs + DP_MIE_CLKCON);
+}
+EXPORT_SYMBOL_GPL(fimd_dp_clock_enable);
+
struct platform_driver fimd_driver = {
.probe = fimd_probe,
.remove = fimd_remove,
diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h
index a20e4a3a8b15..847a0a2b399c 100644
--- a/include/video/samsung_fimd.h
+++ b/include/video/samsung_fimd.h
@@ -436,6 +436,12 @@
#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 0)
#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 0)
+/* Display port clock control */
+#define DP_MIE_CLKCON 0x27c
+#define DP_MIE_CLK_DISABLE 0x0
+#define DP_MIE_CLK_DP_ENABLE 0x2
+#define DP_MIE_CLK_MIE_ENABLE 0x3
+
/* Notes on per-window bpp settings
*
* Value Win0 Win1 Win2 Win3 Win 4
--
1.9.1
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Re: [PATCH] drm: Exynos: Respect framebuffer pitch for FIMD/Mixer
Hello Javier, 2015-03-27 20:08 GMT+09:00 Javier Martinez Canillas jav...@dowhile0.org: Hello Inki, On Fri, Mar 27, 2015 at 2:47 AM, Inki Dae inki@samsung.com wrote: Right, this is not documented but if you have ever checked exynos drm driver tree, then I think you could know how we use the prefix. Of course, I don't like to force the use of this prefix but if you and other people use prefix in the manner of them, exynos drm tree would be a little bit messy. i.e., DRM: EXYNOS, drm: exynos, drm: Exynos, drm/exynos, drm/exynos: fimd, drm: exynos: fimd, DRM: EXYNOS: FIMD, ... so many cases Do you really want this? So I will always say please, use right prefix Otherwise, I will change it while merging as is. And I see that other drm drivers have their own way which is not documented but just implicitly. I agree with you that people should follow the convention for subject lines used in a subsystem and that it is tedious to tell them to fix the subject and resend but I do agree with Tobias that you should rethink your mail filters. For example I've a filter for all the emails that are directly addressed to me or that I'm cc'ed to. It's true that you may get some emails that are not interesting to you just because people cc'ed you in random patches but I think is better to have false positives than to have false negatives. Specially since you are a kernel maintainer and people expect your feedback / ack for patches to get merged. Added a new filter, which will pick up all emails of CCing me. :) Thanks, Inki Dae Thanks, Inki Dae Best regards, Javier -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH 2/2] ARM: EXYNOS: Make sure that the Exynos5420 MDMA0 clock is enabled during suspend
Hello Krzysztof,
Thanks a lot for your feedback.
On 03/27/2015 03:38 PM, Krzysztof Kozlowski wrote:
2015-03-27 15:21 GMT+01:00 Javier Martinez Canillas
javier.marti...@collabora.co.uk:
Commit ae43b3289186 (ARM: 8202/1: dmaengine: pl330: Add runtime Power
Management support v12) added pm support for the pl330 dma driver but
it makes the clock for the Exynos5420 MDMA0 DMA controller to be gated
during suspend and this clock needs to remain enabled in order to make
the system resume from a system suspend state.
To make sure that the clock is enabled during suspend, enable it prior
to entering a suspend state and disable it once the system has resumed.
Thanks to Abhilash Kesavan for figuring out that this was the issue.
Fixes: ae43b32 (ARM: 8202/1: dmaengine: pl330: Add runtime Power Management
support v12)
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Hmmm... isn't a real problem elsewhere - like some clock hierarchy is
wrong or incomplete? This rather looks like workaround for the
problem.
That's a very good question, that's why I sent it as an RFC. I didn't find
anything relevant in the manual but I could certainly be missing something.
@@ -516,6 +528,9 @@ static void exynos5420_pm_resume(void)
{
unsigned long tmp;
+ if (!IS_ERR_OR_NULL(clk))
+ clk_disable_unprepare(clk);
+
Missing clk_put()
Yes, Sylwester already pointed it out. Sorry for missing that.
Best regards,
Krzysztof
Best regards,
Javier
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[PATCH] cpufreq: exynos: remove dead -need_apll_change method
Commit 26ab1c62b6e1 (cpufreq: exynos5250: Set APLL rate
using CCF API) removed the last user of -need_apll_change
method. Remove it and then cleanup exynos_cpufreq_scale()
accordingly.
This patch was tested on Exynos4412 SoC based Trats2 board.
There should be no functional changes caused by this patch.
Cc: Sachin Kamat sachin.ka...@linaro.org
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Kukjin Kim kg...@kernel.org
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
---
drivers/cpufreq/exynos-cpufreq.c | 30 +++---
drivers/cpufreq/exynos-cpufreq.h |1 -
2 files changed, 3 insertions(+), 28 deletions(-)
diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c
index 82d2fbb..01ed166 100644
--- a/drivers/cpufreq/exynos-cpufreq.c
+++ b/drivers/cpufreq/exynos-cpufreq.c
@@ -45,11 +45,9 @@ static int exynos_cpufreq_get_index(unsigned int freq)
static int exynos_cpufreq_scale(unsigned int target_freq)
{
- struct cpufreq_frequency_table *freq_table = exynos_info-freq_table;
unsigned int *volt_table = exynos_info-volt_table;
struct cpufreq_policy *policy = cpufreq_cpu_get(0);
- unsigned int arm_volt, safe_arm_volt = 0;
- unsigned int mpll_freq_khz = exynos_info-mpll_freq_khz;
+ unsigned int arm_volt;
struct device *dev = exynos_info-dev;
unsigned int old_freq;
int index, old_index;
@@ -74,21 +72,10 @@ static int exynos_cpufreq_scale(unsigned int target_freq)
goto out;
}
- /*
-* ARM clock source will be changed APLL to MPLL temporary
-* To support this level, need to control regulator for
-* required voltage level
-*/
- if (exynos_info-need_apll_change != NULL) {
- if (exynos_info-need_apll_change(old_index, index)
- (freq_table[index].frequency mpll_freq_khz)
- (freq_table[old_index].frequency mpll_freq_khz))
- safe_arm_volt = volt_table[exynos_info-pll_safe_idx];
- }
arm_volt = volt_table[index];
/* When the new frequency is higher than current frequency */
- if ((target_freq old_freq) !safe_arm_volt) {
+ if (target_freq old_freq) {
/* Firstly, voltage up to increase frequency */
ret = regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
if (ret) {
@@ -98,21 +85,10 @@ static int exynos_cpufreq_scale(unsigned int target_freq)
}
}
- if (safe_arm_volt) {
- ret = regulator_set_voltage(arm_regulator, safe_arm_volt,
- safe_arm_volt);
- if (ret) {
- dev_err(dev, failed to set cpu voltage to %d\n,
- safe_arm_volt);
- return ret;
- }
- }
-
exynos_info-set_freq(old_index, index);
/* When the new frequency is lower than current frequency */
- if ((target_freq old_freq) ||
- ((target_freq old_freq) safe_arm_volt)) {
+ if (target_freq old_freq) {
/* down the voltage after frequency change */
ret = regulator_set_voltage(arm_regulator, arm_volt,
arm_volt);
diff --git a/drivers/cpufreq/exynos-cpufreq.h b/drivers/cpufreq/exynos-cpufreq.h
index 9f2062a..fe5a105 100644
--- a/drivers/cpufreq/exynos-cpufreq.h
+++ b/drivers/cpufreq/exynos-cpufreq.h
@@ -49,7 +49,6 @@ struct exynos_dvfs_info {
unsigned int*volt_table;
struct cpufreq_frequency_table *freq_table;
void (*set_freq)(unsigned int, unsigned int);
- bool (*need_apll_change)(unsigned int, unsigned int);
void __iomem*cmu_regs;
};
--
1.7.9.5
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[PATCH 00/10] drm/exynos: Add atomic modesetting support
From: Gustavo Padovan gustavo.pado...@collabora.co.uk Hi, Here goes the full support for atomic modesetting on exynos. I've split the patches in the various phases of atomic support. These patches sits on top of the clean up patches I've sent yesterday to this mailing list[1]. Gustavo [1] http://lists.freedesktop.org/archives/dri-devel/2015-March/080074.html Gustavo Padovan (10): drm/exynos: atomic phase 1: use drm_plane_helper_update() drm/exynos: atomic phase 1: use drm_plane_helper_disable() drm/exynos: atomic phase 1: add .mode_set_nofb() callback drm/exynos: atomic phase 2: wire up state reset(), duplicate() and destroy() drm/exynos: atomic phase 2: keep track of framebuffer pointer drm/exynos: atomic phase 3: atomic updates of planes drm/exynos: atomic phase 3: use atomic .set_config helper drm/exynos: atomic phase 3: convert page flips drm/exynos: remove exported functions from exynos_drm_plane drm/exynos: atomic dpms support drivers/gpu/drm/bridge/ptn3460.c | 4 + drivers/gpu/drm/exynos/exynos_dp_core.c | 6 +- drivers/gpu/drm/exynos/exynos_drm_connector.c | 6 +- drivers/gpu/drm/exynos/exynos_drm_crtc.c | 226 -- drivers/gpu/drm/exynos/exynos_drm_dpi.c | 6 +- drivers/gpu/drm/exynos/exynos_drm_drv.c | 2 + drivers/gpu/drm/exynos/exynos_drm_drv.h | 4 +- drivers/gpu/drm/exynos/exynos_drm_dsi.c | 6 +- drivers/gpu/drm/exynos/exynos_drm_encoder.c | 27 +-- drivers/gpu/drm/exynos/exynos_drm_fb.c| 12 +- drivers/gpu/drm/exynos/exynos_drm_fbdev.c | 3 - drivers/gpu/drm/exynos/exynos_drm_plane.c | 113 +++-- drivers/gpu/drm/exynos/exynos_drm_plane.h | 11 -- drivers/gpu/drm/exynos/exynos_drm_vidi.c | 6 +- drivers/gpu/drm/exynos/exynos_hdmi.c | 6 +- 15 files changed, 185 insertions(+), 253 deletions(-) -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 03/10] drm/exynos: atomic phase 1: add .mode_set_nofb() callback
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
The new atomic infrastructure needs the .mode_set_nofb() callback to
update CRTC timings before setting any plane.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 60 +---
1 file changed, 9 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 1c0d936..35f101f 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -81,59 +81,16 @@ exynos_drm_crtc_mode_fixup(struct drm_crtc *crtc,
return true;
}
-static int
-exynos_drm_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode, int x, int y,
- struct drm_framebuffer *old_fb)
-{
- struct drm_framebuffer *fb = crtc-primary-fb;
- unsigned int crtc_w;
- unsigned int crtc_h;
- int ret;
-
- /*
-* copy the mode data adjusted by mode_fixup() into crtc-mode
-* so that hardware can be seet to proper mode.
-*/
- memcpy(crtc-mode, adjusted_mode, sizeof(*adjusted_mode));
-
- ret = exynos_check_plane(crtc-primary, fb);
- if (ret 0)
- return ret;
-
- crtc_w = fb-width - x;
- crtc_h = fb-height - y;
- exynos_plane_mode_set(crtc-primary, crtc, fb, 0, 0,
- crtc_w, crtc_h, x, y, crtc_w, crtc_h);
-
- return 0;
-}
-
-static int exynos_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
- struct drm_framebuffer *old_fb)
+static void
+exynos_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);
- struct drm_framebuffer *fb = crtc-primary-fb;
- unsigned int crtc_w;
- unsigned int crtc_h;
- int ret;
- /* when framebuffer changing is requested, crtc's dpms should be on */
- if (exynos_crtc-dpms DRM_MODE_DPMS_ON) {
- DRM_ERROR(failed framebuffer changing request.\n);
- return -EPERM;
- }
-
- ret = exynos_check_plane(crtc-primary, fb);
- if (ret)
- return ret;
-
- crtc_w = fb-width - x;
- crtc_h = fb-height - y;
- exynos_update_plane(crtc-primary, crtc, fb, 0, 0,
- crtc_w, crtc_h, x, y, crtc_w, crtc_h);
+ if (WARN_ON(!crtc-state))
+ return;
- return 0;
+ if (exynos_crtc-ops-commit)
+ exynos_crtc-ops-commit(exynos_crtc);
}
static void exynos_drm_crtc_disable(struct drm_crtc *crtc)
@@ -158,8 +115,9 @@ static struct drm_crtc_helper_funcs
exynos_crtc_helper_funcs = {
.prepare= exynos_drm_crtc_prepare,
.commit = exynos_drm_crtc_commit,
.mode_fixup = exynos_drm_crtc_mode_fixup,
- .mode_set = exynos_drm_crtc_mode_set,
- .mode_set_base = exynos_drm_crtc_mode_set_base,
+ .mode_set = drm_helper_crtc_mode_set,
+ .mode_set_nofb = exynos_drm_crtc_mode_set_nofb,
+ .mode_set_base = drm_helper_crtc_mode_set_base,
.disable= exynos_drm_crtc_disable,
};
--
2.1.0
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[PATCH 09/10] drm/exynos: remove exported functions from exynos_drm_plane
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Now that no one is using the functions exported by exynos_drm_plane due
to the atomic conversion we can make remove some of the them or make them
static.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_plane.c | 91 +--
drivers/gpu/drm/exynos/exynos_drm_plane.h | 11
2 files changed, 38 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c
b/drivers/gpu/drm/exynos/exynos_drm_plane.c
index e83908a..7f8f962 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_plane.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c
@@ -62,35 +62,12 @@ static int exynos_plane_get_size(int start, unsigned
length, unsigned last)
return size;
}
-int exynos_check_plane(struct drm_plane *plane, struct drm_framebuffer *fb)
-{
- struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane);
- int nr;
- int i;
-
- nr = exynos_drm_fb_get_buf_cnt(fb);
- for (i = 0; i nr; i++) {
- struct exynos_drm_gem_buf *buffer = exynos_drm_fb_buffer(fb, i);
-
- if (!buffer) {
- DRM_DEBUG_KMS(buffer is null\n);
- return -EFAULT;
- }
-
- exynos_plane-dma_addr[i] = buffer-dma_addr;
-
- DRM_DEBUG_KMS(buffer: %d, dma_addr = 0x%lx\n,
- i, (unsigned long)exynos_plane-dma_addr[i]);
- }
-
- return 0;
-}
-
-void exynos_plane_mode_set(struct drm_plane *plane, struct drm_crtc *crtc,
- struct drm_framebuffer *fb, int crtc_x, int crtc_y,
- unsigned int crtc_w, unsigned int crtc_h,
- uint32_t src_x, uint32_t src_y,
- uint32_t src_w, uint32_t src_h)
+static void exynos_plane_mode_set(struct drm_plane *plane, struct drm_crtc
*crtc,
+ struct drm_framebuffer *fb,
+ int crtc_x, int crtc_y,
+ unsigned int crtc_w, unsigned int crtc_h,
+ uint32_t src_x, uint32_t src_y,
+ uint32_t src_w, uint32_t src_h)
{
struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane);
unsigned int actual_w;
@@ -141,24 +118,6 @@ void exynos_plane_mode_set(struct drm_plane *plane, struct
drm_crtc *crtc,
plane-crtc = crtc;
}
-void
-exynos_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
-struct drm_framebuffer *fb, int crtc_x, int crtc_y,
-unsigned int crtc_w, unsigned int crtc_h,
-uint32_t src_x, uint32_t src_y,
-uint32_t src_w, uint32_t src_h)
-{
- struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);
- struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane);
-
- exynos_plane_mode_set(plane, crtc, fb, crtc_x, crtc_y,
- crtc_w, crtc_h, src_x 16, src_y 16,
- src_w 16, src_h 16);
-
- if (exynos_crtc-ops-win_commit)
- exynos_crtc-ops-win_commit(exynos_crtc, exynos_plane-zpos);
-}
-
static struct drm_plane_funcs exynos_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
@@ -171,19 +130,45 @@ static struct drm_plane_funcs exynos_plane_funcs = {
static int exynos_plane_atomic_check(struct drm_plane *plane,
struct drm_plane_state *state)
{
- return exynos_check_plane(plane, state-fb);
+ struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane);
+ struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(plane-crtc);
+ int nr;
+ int i;
+
+ nr = exynos_drm_fb_get_buf_cnt(state-fb);
+ for (i = 0; i nr; i++) {
+ struct exynos_drm_gem_buf *buffer =
+ exynos_drm_fb_buffer(state-fb, i);
+
+ if (!buffer) {
+ DRM_DEBUG_KMS(buffer is null\n);
+ return -EFAULT;
+ }
+
+ exynos_plane-dma_addr[i] = buffer-dma_addr;
+
+ DRM_DEBUG_KMS(buffer: %d, dma_addr = 0x%lx\n,
+ i, (unsigned long)exynos_plane-dma_addr[i]);
+ }
+
+ return 0;
}
static void exynos_plane_atomic_update(struct drm_plane *plane,
struct drm_plane_state *old_state)
{
struct drm_plane_state *state = plane-state;
+ struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(state-crtc);
+ struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane);
- exynos_update_plane(plane, state-crtc, state-fb,
- state-crtc_x, state-crtc_y,
-
[PATCH 04/10] drm/exynos: atomic phase 2: wire up state reset(), duplicate() and destroy()
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Set CRTC, planes and connectors to use the default implementations from
the atomic helper library. The helpers will work to keep track of state
for each DRM object.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/bridge/ptn3460.c | 4
drivers/gpu/drm/exynos/exynos_dp_core.c | 4
drivers/gpu/drm/exynos/exynos_drm_connector.c | 4
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 6 ++
drivers/gpu/drm/exynos/exynos_drm_dpi.c | 4
drivers/gpu/drm/exynos/exynos_drm_drv.c | 2 ++
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 4
drivers/gpu/drm/exynos/exynos_drm_plane.c | 4
drivers/gpu/drm/exynos/exynos_drm_vidi.c | 4
drivers/gpu/drm/exynos/exynos_hdmi.c | 4
10 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/bridge/ptn3460.c b/drivers/gpu/drm/bridge/ptn3460.c
index 826833e..30da10c 100644
--- a/drivers/gpu/drm/bridge/ptn3460.c
+++ b/drivers/gpu/drm/bridge/ptn3460.c
@@ -27,6 +27,7 @@
#include drm_crtc.h
#include drm_crtc_helper.h
+#include drm_atomic_helper.h
#include drm_edid.h
#include drmP.h
@@ -263,6 +264,9 @@ static struct drm_connector_funcs ptn3460_connector_funcs =
{
.fill_modes = drm_helper_probe_single_connector_modes,
.detect = ptn3460_detect,
.destroy = ptn3460_connector_destroy,
+ .reset = drm_atomic_helper_connector_reset,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
};
int ptn3460_bridge_attach(struct drm_bridge *bridge)
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
b/drivers/gpu/drm/exynos/exynos_dp_core.c
index bf17a60..6704d5c 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -28,6 +28,7 @@
#include drm/drmP.h
#include drm/drm_crtc.h
#include drm/drm_crtc_helper.h
+#include drm/drm_atomic_helper.h
#include drm/drm_panel.h
#include drm/bridge/ptn3460.h
@@ -952,6 +953,9 @@ static struct drm_connector_funcs exynos_dp_connector_funcs
= {
.fill_modes = drm_helper_probe_single_connector_modes,
.detect = exynos_dp_detect,
.destroy = exynos_dp_connector_destroy,
+ .reset = drm_atomic_helper_connector_reset,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
};
static int exynos_dp_get_modes(struct drm_connector *connector)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_connector.c
b/drivers/gpu/drm/exynos/exynos_drm_connector.c
index ba9b3d5..980b085 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_connector.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_connector.c
@@ -13,6 +13,7 @@
#include drm/drmP.h
#include drm/drm_crtc_helper.h
+#include drm/drm_atomic_helper.h
#include drm/exynos_drm.h
#include exynos_drm_drv.h
@@ -182,6 +183,9 @@ static struct drm_connector_funcs exynos_connector_funcs = {
.fill_modes = exynos_drm_connector_fill_modes,
.detect = exynos_drm_connector_detect,
.destroy= exynos_drm_connector_destroy,
+ .reset = drm_atomic_helper_connector_reset,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
};
struct drm_connector *exynos_drm_connector_create(struct drm_device *dev,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 35f101f..44e73d0 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -14,6 +14,8 @@
#include drm/drmP.h
#include drm/drm_crtc_helper.h
+#include drm/drm_atomic.h
+#include drm/drm_atomic_helper.h
#include exynos_drm_crtc.h
#include exynos_drm_drv.h
@@ -194,8 +196,12 @@ static struct drm_crtc_funcs exynos_crtc_funcs = {
.set_config = drm_crtc_helper_set_config,
.page_flip = exynos_drm_crtc_page_flip,
.destroy= exynos_drm_crtc_destroy,
+ .reset = drm_atomic_helper_crtc_reset,
+ .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
};
+
struct exynos_drm_crtc *exynos_drm_crtc_create(struct drm_device *drm_dev,
struct drm_plane *plane,
int pipe,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dpi.c
b/drivers/gpu/drm/exynos/exynos_drm_dpi.c
index 37678cf..ced5c23 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dpi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dpi.c
@@ -13,6 +13,7 @@
#include drm/drmP.h
#include drm/drm_crtc_helper.h
#include drm/drm_panel.h
+#include drm/drm_atomic_helper.h
#include linux/regulator/consumer.h
[PATCH 01/10] drm/exynos: atomic phase 1: use drm_plane_helper_update()
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Rip out the check from exynos_update_plane() and create
exynos_check_plane() for the check phase enabling use to use
the atomic helpers to call our check and update phases when updating
planes.
Update all users of exynos_update_plane() accordingly to call
exynos_check_plane() before.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 29
drivers/gpu/drm/exynos/exynos_drm_plane.c | 37 ++-
drivers/gpu/drm/exynos/exynos_drm_plane.h | 2 +-
3 files changed, 43 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index eb49195..1c0d936 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -116,6 +116,7 @@ static int exynos_drm_crtc_mode_set_base(struct drm_crtc
*crtc, int x, int y,
struct drm_framebuffer *fb = crtc-primary-fb;
unsigned int crtc_w;
unsigned int crtc_h;
+ int ret;
/* when framebuffer changing is requested, crtc's dpms should be on */
if (exynos_crtc-dpms DRM_MODE_DPMS_ON) {
@@ -123,11 +124,16 @@ static int exynos_drm_crtc_mode_set_base(struct drm_crtc
*crtc, int x, int y,
return -EPERM;
}
+ ret = exynos_check_plane(crtc-primary, fb);
+ if (ret)
+ return ret;
+
crtc_w = fb-width - x;
crtc_h = fb-height - y;
+ exynos_update_plane(crtc-primary, crtc, fb, 0, 0,
+ crtc_w, crtc_h, x, y, crtc_w, crtc_h);
- return exynos_update_plane(crtc-primary, crtc, fb, 0, 0,
- crtc_w, crtc_h, x, y, crtc_w, crtc_h);
+ return 0;
}
static void exynos_drm_crtc_disable(struct drm_crtc *crtc)
@@ -164,7 +170,6 @@ static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc,
{
struct drm_device *dev = crtc-dev;
struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);
- struct drm_framebuffer *old_fb = crtc-primary-fb;
unsigned int crtc_w, crtc_h;
int ret;
@@ -183,6 +188,10 @@ static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc,
goto out;
}
+ ret = exynos_check_plane(crtc-primary, fb);
+ if (ret)
+ goto out;
+
ret = drm_vblank_get(dev, exynos_crtc-pipe);
if (ret) {
DRM_DEBUG(failed to acquire vblank counter\n);
@@ -201,17 +210,9 @@ static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc,
crtc-primary-fb = fb;
crtc_w = fb-width - crtc-x;
crtc_h = fb-height - crtc-y;
- ret = exynos_update_plane(crtc-primary, crtc, fb, 0, 0,
- crtc_w, crtc_h, crtc-x, crtc-y,
- crtc_w, crtc_h);
- if (ret) {
- crtc-primary-fb = old_fb;
- spin_lock_irq(dev-event_lock);
- exynos_crtc-event = NULL;
- drm_vblank_put(dev, exynos_crtc-pipe);
- spin_unlock_irq(dev-event_lock);
- return ret;
- }
+ exynos_update_plane(crtc-primary, crtc, fb, 0, 0,
+ crtc_w, crtc_h, crtc-x, crtc-y,
+ crtc_w, crtc_h);
return 0;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c
b/drivers/gpu/drm/exynos/exynos_drm_plane.c
index 2b0479e..5a37816 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_plane.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c
@@ -140,21 +140,15 @@ void exynos_plane_mode_set(struct drm_plane *plane,
struct drm_crtc *crtc,
plane-crtc = crtc;
}
-int
+void
exynos_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
struct drm_framebuffer *fb, int crtc_x, int crtc_y,
unsigned int crtc_w, unsigned int crtc_h,
uint32_t src_x, uint32_t src_y,
uint32_t src_w, uint32_t src_h)
{
-
struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);
struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane);
- int ret;
-
- ret = exynos_check_plane(plane, fb);
- if (ret 0)
- return ret;
exynos_plane_mode_set(plane, crtc, fb, crtc_x, crtc_y,
crtc_w, crtc_h, src_x 16, src_y 16,
@@ -162,8 +156,6 @@ exynos_update_plane(struct drm_plane *plane, struct
drm_crtc *crtc,
if (exynos_crtc-ops-win_commit)
exynos_crtc-ops-win_commit(exynos_crtc, exynos_plane-zpos);
-
- return 0;
}
static int exynos_disable_plane(struct drm_plane *plane)
@@ -179,11 +171,34 @@ static int exynos_disable_plane(struct drm_plane *plane)
}
static struct drm_plane_funcs exynos_plane_funcs = {
- .update_plane = exynos_update_plane,
+ .update_plane = drm_plane_helper_update,
[PATCH 02/10] drm/exynos: atomic phase 1: use drm_plane_helper_disable()
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
The atomic helper to disable planes also uses the optional
.atomic_disable() helper. The unique operation it does is calling
.win_disable()
exynos_drm_fb_get_buf_cnt() needs a fb check too to avoid a null pointer.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_fb.c| 2 +-
drivers/gpu/drm/exynos/exynos_drm_plane.c | 26 +-
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.c
b/drivers/gpu/drm/exynos/exynos_drm_fb.c
index d346d1e..470456d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fb.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fb.c
@@ -136,7 +136,7 @@ unsigned int exynos_drm_fb_get_buf_cnt(struct
drm_framebuffer *fb)
exynos_fb = to_exynos_fb(fb);
- return exynos_fb-buf_cnt;
+ return exynos_fb ? exynos_fb-buf_cnt : 0;
}
struct drm_framebuffer *
diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c
b/drivers/gpu/drm/exynos/exynos_drm_plane.c
index 5a37816..2152a24 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_plane.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c
@@ -158,21 +158,9 @@ exynos_update_plane(struct drm_plane *plane, struct
drm_crtc *crtc,
exynos_crtc-ops-win_commit(exynos_crtc, exynos_plane-zpos);
}
-static int exynos_disable_plane(struct drm_plane *plane)
-{
- struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane);
- struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(plane-crtc);
-
- if (exynos_crtc-ops-win_disable)
- exynos_crtc-ops-win_disable(exynos_crtc,
- exynos_plane-zpos);
-
- return 0;
-}
-
static struct drm_plane_funcs exynos_plane_funcs = {
.update_plane = drm_plane_helper_update,
- .disable_plane = exynos_disable_plane,
+ .disable_plane = drm_plane_helper_disable,
.destroy= drm_plane_cleanup,
};
@@ -194,9 +182,21 @@ static void exynos_plane_atomic_update(struct drm_plane
*plane,
state-src_w 16, state-src_h 16);
}
+static void exynos_plane_atomic_disable(struct drm_plane *plane,
+ struct drm_plane_state *old_state)
+{
+ struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane);
+ struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(old_state-crtc);
+
+ if (exynos_crtc-ops-win_disable)
+ exynos_crtc-ops-win_disable(exynos_crtc,
+ exynos_plane-zpos);
+}
+
static const struct drm_plane_helper_funcs plane_helper_funcs = {
.atomic_check = exynos_plane_atomic_check,
.atomic_update = exynos_plane_atomic_update,
+ .atomic_disable = exynos_plane_atomic_disable,
};
static void exynos_plane_attach_zpos_property(struct drm_plane *plane,
--
2.1.0
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[PATCH 08/10] drm/exynos: atomic phase 3: convert page flips
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
PageFlips now use the atomic helper to work through the atomic modesetting
API. Async page flips are not supported yet.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 63 +---
drivers/gpu/drm/exynos/exynos_drm_fb.c | 9 -
2 files changed, 9 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index b0888d4..0db7b91 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -123,67 +123,6 @@ static struct drm_crtc_helper_funcs
exynos_crtc_helper_funcs = {
.disable= exynos_drm_crtc_disable,
};
-static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc,
-struct drm_framebuffer *fb,
-struct drm_pending_vblank_event *event,
-uint32_t page_flip_flags)
-{
- struct drm_device *dev = crtc-dev;
- struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);
- unsigned int crtc_w, crtc_h;
- int ret;
-
- /* when the page flip is requested, crtc's dpms should be on */
- if (exynos_crtc-dpms DRM_MODE_DPMS_ON) {
- DRM_ERROR(failed page flip request.\n);
- return -EINVAL;
- }
-
- if (!event)
- return -EINVAL;
-
- spin_lock_irq(dev-event_lock);
- if (exynos_crtc-event) {
- ret = -EBUSY;
- goto out;
- }
-
- ret = exynos_check_plane(crtc-primary, fb);
- if (ret)
- goto out;
-
- ret = drm_vblank_get(dev, exynos_crtc-pipe);
- if (ret) {
- DRM_DEBUG(failed to acquire vblank counter\n);
- goto out;
- }
-
- exynos_crtc-event = event;
- spin_unlock_irq(dev-event_lock);
-
- /*
-* the pipe from user always is 0 so we can set pipe number
-* of current owner to event.
-*/
- event-pipe = exynos_crtc-pipe;
-
- crtc-primary-fb = fb;
- crtc_w = fb-width - crtc-x;
- crtc_h = fb-height - crtc-y;
- exynos_update_plane(crtc-primary, crtc, fb, 0, 0,
- crtc_w, crtc_h, crtc-x, crtc-y,
- crtc_w, crtc_h);
-
- if (crtc-primary-state)
- drm_atomic_set_fb_for_plane(crtc-primary-state, fb);
-
- return 0;
-
-out:
- spin_unlock_irq(dev-event_lock);
- return ret;
-}
-
static void exynos_drm_crtc_destroy(struct drm_crtc *crtc)
{
struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);
@@ -197,7 +136,7 @@ static void exynos_drm_crtc_destroy(struct drm_crtc *crtc)
static struct drm_crtc_funcs exynos_crtc_funcs = {
.set_config = drm_atomic_helper_set_config,
- .page_flip = exynos_drm_crtc_page_flip,
+ .page_flip = drm_atomic_helper_page_flip,
.destroy= exynos_drm_crtc_destroy,
.reset = drm_atomic_helper_crtc_reset,
.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.c
b/drivers/gpu/drm/exynos/exynos_drm_fb.c
index b83ceea..b4bc3ef 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fb.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fb.c
@@ -307,11 +307,18 @@ static void exynos_drm_output_poll_changed(struct
drm_device *dev)
exynos_drm_fbdev_init(dev);
}
+static int exynos_atomic_commit(struct drm_device *dev,
+ struct drm_atomic_state *state,
+ bool async)
+{
+ return drm_atomic_helper_commit(dev, state, false);
+}
+
static const struct drm_mode_config_funcs exynos_drm_mode_config_funcs = {
.fb_create = exynos_user_fb_create,
.output_poll_changed = exynos_drm_output_poll_changed,
.atomic_check = drm_atomic_helper_check,
- .atomic_commit = drm_atomic_helper_commit,
+ .atomic_commit = exynos_atomic_commit,
};
void exynos_drm_mode_config_init(struct drm_device *dev)
--
2.1.0
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[PATCH 05/10] drm/exynos: atomic phase 2: keep track of framebuffer pointer
From: Gustavo Padovan gustavo.pado...@collabora.co.uk Use drm_atomic_set_fb_for_plane() in the legacy page_flip path to keep track of the framebuffer pointer and reference. Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk --- drivers/gpu/drm/exynos/exynos_drm_crtc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c index 44e73d0..b080e83 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c @@ -174,6 +174,9 @@ static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc, crtc_w, crtc_h, crtc-x, crtc-y, crtc_w, crtc_h); + if (crtc-primary-state) + drm_atomic_set_fb_for_plane(crtc-primary-state, fb); + return 0; out: -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 06/10] drm/exynos: atomic phase 3: atomic updates of planes
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Now that phase 1 and 2 are complete we can switch the update/disable_plane
callbacks to their atomic version.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_fb.c| 3 +++
drivers/gpu/drm/exynos/exynos_drm_plane.c | 4 ++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.c
b/drivers/gpu/drm/exynos/exynos_drm_fb.c
index 470456d..b83ceea 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fb.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fb.c
@@ -16,6 +16,7 @@
#include drm/drm_crtc.h
#include drm/drm_crtc_helper.h
#include drm/drm_fb_helper.h
+#include drm/drm_atomic_helper.h
#include uapi/drm/exynos_drm.h
#include exynos_drm_drv.h
@@ -309,6 +310,8 @@ static void exynos_drm_output_poll_changed(struct
drm_device *dev)
static const struct drm_mode_config_funcs exynos_drm_mode_config_funcs = {
.fb_create = exynos_user_fb_create,
.output_poll_changed = exynos_drm_output_poll_changed,
+ .atomic_check = drm_atomic_helper_check,
+ .atomic_commit = drm_atomic_helper_commit,
};
void exynos_drm_mode_config_init(struct drm_device *dev)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c
b/drivers/gpu/drm/exynos/exynos_drm_plane.c
index 3cd628e..e83908a 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_plane.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c
@@ -160,8 +160,8 @@ exynos_update_plane(struct drm_plane *plane, struct
drm_crtc *crtc,
}
static struct drm_plane_funcs exynos_plane_funcs = {
- .update_plane = drm_plane_helper_update,
- .disable_plane = drm_plane_helper_disable,
+ .update_plane = drm_atomic_helper_update_plane,
+ .disable_plane = drm_atomic_helper_disable_plane,
.destroy= drm_plane_cleanup,
.reset = drm_atomic_helper_plane_reset,
.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
--
2.1.0
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[PATCH 07/10] drm/exynos: atomic phase 3: use atomic .set_config helper
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Now that phase 1 and 2 are complete switch .set_config helper to
use the atomic one.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index b080e83..b0888d4 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -196,7 +196,7 @@ static void exynos_drm_crtc_destroy(struct drm_crtc *crtc)
}
static struct drm_crtc_funcs exynos_crtc_funcs = {
- .set_config = drm_crtc_helper_set_config,
+ .set_config = drm_atomic_helper_set_config,
.page_flip = exynos_drm_crtc_page_flip,
.destroy= exynos_drm_crtc_destroy,
.reset = drm_atomic_helper_crtc_reset,
--
2.1.0
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Re: [RFT PATCHv2] drm/exynos: Enable DP clock to fix display on Exynos5250 and other
Hello Krzysztof, On 03/27/2015 05:08 PM, Krzysztof Kozlowski wrote: After adding display power domain for Exynos5250 in commit 2d2c9a8d0a4f (ARM: dts: add display power domain for exynos5250) the display on Chromebook Snow and others stopped working after boot. The reason for this suggested Andrzej Hajda: the DP clock was disabled. This clock is required by Display Port and is enabled by bootloader. However when FIMD driver probing was deferred, the display power domain was turned off. This effectively reset the value of DP clock enable register. When exynos-dp is later probed, the clock is not enabled and display is not properly configured: exynos-dp 145b.dp-controller: Timeout of video streamclk ok exynos-dp 145b.dp-controller: unable to config video Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com Reported-by: Javier Martinez Canillas javier.marti...@collabora.co.uk Fixes: 2d2c9a8d0a4f (ARM: dts: add display power domain for exynos5250) Cc: sta...@vger.kernel.org --- This should fix issue reported by Javier [1][2]. I tested this patch and does indeed solves both issues I reported The exynos-dp probe deferral does not make the display to not be working and also disabling and enabling the display with: with /sys/devices/platform/exynos-drm/graphics/fb0/blank works. Thanks a lot for fixing this issue. On an Exynos5250 Snow Chromebook: Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk Best regards, Javier -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH v2 1/2] clk: exynos5420: Add alias for MDMA0 controller clock
The MDMA0 controller clock needs to be enabled to allow the
system to be resumed when entering into a suspend state.
The clock is disabled as a part of the runtime pm for the
pl330 DMA driver so the system fails to resume. So to allow
the system to grab the clock and make sure that it stays
enabled during suspend, an alias has to be added so a clock
lookup for a clock is registered.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v1: None.
drivers/clk/samsung/clk-exynos5420.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 07d666cc6a29..8b49e8b3b548 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -893,7 +893,7 @@ static struct samsung_div_clock exynos5x_div_clks[]
__initdata = {
static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = {
/* G2D */
- GATE(CLK_MDMA0, mdma0, aclk266_g2d, GATE_IP_G2D, 1, 0, 0),
+ GATE_A(CLK_MDMA0, mdma0, aclk266_g2d, GATE_IP_G2D, 1, 0, 0,
mdma0),
GATE(CLK_SSS, sss, aclk266_g2d, GATE_IP_G2D, 2, 0, 0),
GATE(CLK_G2D, g2d, aclk333_g2d, GATE_IP_G2D, 3, 0, 0),
GATE(CLK_SMMU_MDMA0, smmu_mdma0, aclk266_g2d, GATE_IP_G2D, 5, 0, 0),
--
2.1.4
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[RFC PATCH v2 2/2] ARM: EXYNOS: Make sure that the Exynos5420 MDMA0 clock is enabled during suspend
Commit ae43b3289186 (ARM: 8202/1: dmaengine: pl330: Add runtime Power
Management support v12) added pm support for the pl330 dma driver but
it makes the clock for the Exynos5420 MDMA0 DMA controller to be gated
during suspend and this clock needs to remain enabled in order to make
the system resume from a system suspend state.
To make sure that the clock is enabled during suspend, enable it prior
to entering a suspend state and disable it once the system has resumed.
Thanks to Abhilash Kesavan for figuring out that this was the issue.
Fixes: ae43b32 (ARM: 8202/1: dmaengine: pl330: Add runtime Power Management
support v12)
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
The patch is an RFC because I'm not sure if this is the proper fix or if
is just fixing a symptom rather than the cause. Any suggestions are more
than welcomed.
Changes since v1:
- Call clk_put() after disabling the clock. Suggested by Sylwester Nawrocki.
- Use only IS_ERR() instead IS_ERR_OR_NULL(). Suggested by Sylwester Nawrocki.
arch/arm/mach-exynos/suspend.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 1521eaf99265..8a297fc1fa76 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -16,6 +16,7 @@
#include linux/init.h
#include linux/suspend.h
#include linux/syscore_ops.h
+#include linux/clk.h
#include linux/cpu_pm.h
#include linux/io.h
#include linux/irq.h
@@ -79,6 +80,7 @@ static const struct exynos_pm_data *pm_data;
static int exynos5420_cpu_state;
static unsigned int exynos_pmu_spare3;
+static struct clk *clk;
/*
* GIC wake-up support
@@ -374,6 +376,16 @@ static void exynos5420_pm_prepare(void)
{
unsigned int tmp;
+ /*
+* Exynos5420 requires the MDMA0 controller clock to be
+* ungated on suspend in order to be resumed correctly.
+*/
+ clk = clk_get(NULL, mdma0);
+ if (IS_ERR(clk))
+ pr_warn(Failed to get mdma0 clk (%ld)\n, PTR_ERR(clk));
+ else
+ clk_prepare_enable(clk);
+
/* Set wake-up mask registers */
exynos_pm_set_wakeup_mask();
@@ -516,6 +528,11 @@ static void exynos5420_pm_resume(void)
{
unsigned long tmp;
+ if (!IS_ERR(clk)) {
+ clk_disable_unprepare(clk);
+ clk_put(clk);
+ }
+
/* Restore the CPU0 low power state register */
tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
--
2.1.4
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Re: [PATCH 00/16 v2] iommu: Move domain allocation into drivers
Am Donnerstag, 26. März 2015, 13:43:03 schrieb Joerg Roedel: Changes v1-v2: * Rebased to v4.0-rc5 * Converted domain-types to a bit-field Hi, here is patch-set to replace the existing domain_init and domain_destroy iommu-ops with the new domain_alloc and domain_free callbacks The new callbacks move the allocation of iommu domains into the iommu driver, allowing them to put a generic iommu_domain struct into their own domain struct. This makes domain handling in the drivers more cache efficient and prepares the introduction of default domains in another patch-set. While at it, this patch-set also introduces domain types. These are internal to the iommu core code for now, there are three of them: * DMA-API domains * Identity mapped domains * Domains unmanaged by the iommu-core, used for iommu-api so that the users can create their own mappings The patches have been compile tested for x86, ARM and PPC and runtime tested on x86 (Intel VT-d and AMD IOMMU). Please review. core and Rockchip bits Tested-by: Heiko Stuebner he...@sntech.de -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] cpufreq: exynos: remove dead -need_apll_change method
On 27 March 2015 at 22:02, Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com wrote: Commit 26ab1c62b6e1 (cpufreq: exynos5250: Set APLL rate using CCF API) removed the last user of -need_apll_change method. Remove it and then cleanup exynos_cpufreq_scale() accordingly. This patch was tested on Exynos4412 SoC based Trats2 board. There should be no functional changes caused by this patch. Cc: Sachin Kamat sachin.ka...@linaro.org Cc: Lukasz Majewski l.majew...@samsung.com Cc: Kukjin Kim kg...@kernel.org Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com --- drivers/cpufreq/exynos-cpufreq.c | 30 +++--- drivers/cpufreq/exynos-cpufreq.h |1 - 2 files changed, 3 insertions(+), 28 deletions(-) Acked-by: Viresh Kumar viresh.ku...@linaro.org @Kukjin: please take it through your tree. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 00/16 v2] iommu: Move domain allocation into drivers
On Thu, 2015-03-26 at 13:43 +0100, Joerg Roedel wrote: Changes v1-v2: * Rebased to v4.0-rc5 * Converted domain-types to a bit-field Hi, here is patch-set to replace the existing domain_init and domain_destroy iommu-ops with the new domain_alloc and domain_free callbacks The new callbacks move the allocation of iommu domains into the iommu driver, allowing them to put a generic iommu_domain struct into their own domain struct. This makes domain handling in the drivers more cache efficient and prepares the introduction of default domains in another patch-set. While at it, this patch-set also introduces domain types. These are internal to the iommu core code for now, there are three of them: * DMA-API domains * Identity mapped domains * Domains unmanaged by the iommu-core, used for iommu-api so that the users can create their own mappings The patches have been compile tested for x86, ARM and PPC and runtime tested on x86 (Intel VT-d and AMD IOMMU). Please review. For 1-5,16 Reviewed-by: Alex Williamson alex.william...@redhat.com My only comment/question is whether you'd want to consider using ERR_PTR() return values from domain_alloc(). It's an alloc functions, so NULL == -ENOMEM is pretty standard, but we could at least have the interface to the iommu driver return more info even if we continue to mask that as NULL out to the IOMMU API users for now. Thanks, Alex -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
