Hi,
2015-06-04 13:13 GMT+09:00 Jiang Liu jiang@linux.intel.com:
Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc while we
already have a pointer to corresponding irq_desc.
Signed-off-by: Jiang Liu jiang@linux.intel.com
Acked-by: Linus Walleij linus.wall...@linaro.org
---
IRQ signal before driver probe is needless because driver sends
current state after platform booting done.
So, this patch clears MUIC IRQ bits before request IRQ.
Signed-off-by: Jaewon Kim jaewon02@samsung.com
---
drivers/extcon/extcon-max77843.c |9 +
1 file
Hi Jaewon,
On 06/05/2015 01:32 PM, Jaewon Kim wrote:
IRQ signal before driver probe is needless because driver sends
current state after platform booting done.
So, this patch clears MUIC IRQ bits before request IRQ.
Signed-off-by: Jaewon Kim jaewon02@samsung.com
---
On 06/05/2015 01:54 PM, MyungJoo Ham wrote:
IRQ signal before driver probe is needless because driver sends
current state after platform booting done.
So, this patch clears MUIC IRQ bits before request IRQ.
Signed-off-by: Jaewon Kim jaewon02@samsung.com
---
IRQ signal before driver probe is needless because driver sends
current state after platform booting done.
So, this patch clears MUIC IRQ bits before request IRQ.
Signed-off-by: Jaewon Kim jaewon02@samsung.com
---
drivers/extcon/extcon-max77843.c |9 +
1 file changed, 9
Am 03.06.2015 um 21:57 schrieb grygorii.stras...@linaro.org:
...
So few comments from above:
- registering devices later during the System boot may improve boot time.
But resolving of all deferred probes may NOT improve boot time ;)
Have you seen smth like this?
If someone is out for
On 05/28, Uwe Kleine-König wrote:
Since commit 2893c379461a (clk: make strings in parent name arrays
const) the name of parent clocks can be const. So add more const in
several clock drivers.
Signed-off-by: Uwe Kleine-König u.kleine-koe...@pengutronix.de
---
Applied to clk-next
--
Am 03.06.2015 um 23:12 schrieb Rob Clark:
On Mon, May 25, 2015 at 10:53 AM, Tomeu Vizoso
tomeu.viz...@collabora.com wrote:
Hello,
I have a problem with the panel on my Tegra Chromebook taking longer than
expected to be ready during boot (Stéphane Marchesin reported what is
basically the
On Thu, Jun 04, 2015 at 10:31:45AM +0200, Michal Suchanek wrote:
You might want to try to run the bus at 60MHz or 80MHz and then the
values would probably again be different.
The first two values are set in DT so the logical place for setting
the third is also in DT.
Otherwise you would
Javier Martinez Canillas javier.marti...@collabora.co.uk writes:
Hello Kevin,
On 06/04/2015 03:08 AM, Kevin Hilman wrote:
riku.voi...@linaro.org writes:
From: Riku Voipio riku.voi...@linaro.org
CONFIG_USB_HSIC_USB3503 is needed by exynos5250-arndale for the on-board
asix network
On 06/04/2015 11:39 AM, Tomeu Vizoso wrote:
On 3 June 2015 at 21:57, grygorii.stras...@linaro.org
grygorii.stras...@linaro.org wrote:
On 05/28/2015 07:33 AM, Rob Herring wrote:
On Mon, May 25, 2015 at 9:53 AM, Tomeu Vizoso tomeu.viz...@collabora.com
wrote:
I have a problem with the panel on
On Thursday, June 04, 2015 at 06:21:32 AM, Michal Suchanek wrote:
On 4 June 2015 at 00:53, Marek Vasut ma...@denx.de wrote:
On Wednesday, June 03, 2015 at 11:26:39 PM, Michal Suchanek wrote:
Hello,
Hi,
this patch series makes it possible to access the SPI NOR flash in the
Samsung
On 4 June 2015 at 17:28, Marek Vasut ma...@denx.de wrote:
On Thursday, June 04, 2015 at 06:54:00 AM, Michal Suchanek wrote:
On 4 June 2015 at 00:58, Marek Vasut ma...@denx.de wrote:
On Wednesday, June 03, 2015 at 11:26:40 PM, Michal Suchanek wrote:
On Exynos it is necessary to set SPI
On Thursday, June 04, 2015 at 06:31:45 AM, Michal Suchanek wrote:
On 4 June 2015 at 01:03, Marek Vasut ma...@denx.de wrote:
On Wednesday, June 03, 2015 at 11:26:41 PM, Michal Suchanek wrote:
On sunxi the SPI controller currently does not have DMA support and
fails any transfer larger than
On Thursday, June 04, 2015 at 06:54:00 AM, Michal Suchanek wrote:
On 4 June 2015 at 00:58, Marek Vasut ma...@denx.de wrote:
On Wednesday, June 03, 2015 at 11:26:40 PM, Michal Suchanek wrote:
On Exynos it is necessary to set SPI controller parameters that apply to
a SPI slave in a DT subnode
On Thursday, June 04, 2015 at 04:04:18 AM, Krzysztof Kozlowski wrote:
On 04.06.2015 06:26, Michal Suchanek wrote:
The Snow has onboard SPI NOR flash which contains the bootloader.
Add DT node for this flash chip. The flash is rated 133MHz but the pl330
controller can transfer only up to
exynos_dsi_host_transfer() can be called through a panel driver while
DSI is turning down. It is possible because the function checks only
whether DSI is initialized or not, and there is a moment which DSI is
set by uninitialized, but DSI is still turning down. To prevent it,
DSI must be set by
On Wed, Jun 3, 2015 at 11:26 PM, Michal Suchanek hramr...@gmail.com wrote:
On sunxi the SPI controller currently does not have DMA support and fails
any transfer larger than 63 bytes.
This is a driver limitation, not a hardware limitation.
On Exynos the pl330 DMA controller fails any transfer
On 04.06.2015 12:51, Krzysztof Kozlowski wrote:
On 04.06.2015 08:11, Kukjin Kim wrote:
On 06/01/15 20:34, Krzysztof Kozlowski wrote:
W dniu 01.06.2015 o 19:10, Marek Szyprowski pisze:
Hello,
Main changes for Exynos SYSMMU (IOMMU) driver has been finally scheduled
for merging - see
Hello Kevin,
On 06/04/2015 03:08 AM, Kevin Hilman wrote:
riku.voi...@linaro.org writes:
From: Riku Voipio riku.voi...@linaro.org
CONFIG_USB_HSIC_USB3503 is needed by exynos5250-arndale for the on-board
asix network controller. Enable it so networking works with
multi_v7_defconfig out of
Hello Michal,
On Wed, Jun 3, 2015 at 11:26 PM, Michal Suchanek hramr...@gmail.com wrote:
Although there is only one choice of chipselect it is necessary to
specify it. The driver cannot claim the gpio otherwise.
Signed-off-by: Michal Suchanek hramr...@gmail.com
---
On Thu, Jun 4, 2015 at 11:16 AM, Mark Brown broo...@kernel.org wrote:
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -18,6 +18,7 @@
#include linux/interrupt.h
#include linux/delay.h
#include linux/clk.h
+#include linux/clk-provider.h
Whatever you're doing here this
On Thu, Jun 04, 2015 at 11:33:37AM +0200, Michal Suchanek wrote:
On 4 June 2015 at 11:16, Mark Brown broo...@kernel.org wrote:
Also for this patch (which just adds some trace) there isn't any clear
reason for it to be sent as part of the series at all, it doesn't help
deliver the
On Thu, Jun 04, 2015 at 12:52:19PM +0200, Michal Suchanek wrote:
There is no code interdependency with the other patches so if it's
preferred I can send patches like this separately.
Yes, that's better practice.
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On 4 June 2015 at 12:26, Mark Brown broo...@kernel.org wrote:
On Thu, Jun 04, 2015 at 11:33:37AM +0200, Michal Suchanek wrote:
On 4 June 2015 at 11:16, Mark Brown broo...@kernel.org wrote:
Also for this patch (which just adds some trace) there isn't any clear
reason for it to be sent as
On 06/01/2015 03:12 PM, Ben Gamari wrote:
On 06/01/2015 06:10 AM, Marek Szyprowski wrote:
This patch adds System MMU nodes to all defined devices that are specific
to Exynos5420/5800/5422 series.
Apologies in advance if Thunderbird mangles this message; my usual mail
configuration has
From: Gwendal Grignou gwen...@chromium.org
Chromebooks can have more than one Embedded Controller so the
cros_ec device id has to be incremented for each EC registered.
Add a new structure to represent multiple EC as different char
devices (e.g: /dev/cros_ec, /dev/cros_pd). It connects to
Commit 1b84f2a4cd4a (mfd: cros_ec: Use fixed size arrays to transfer
data with the EC) modified the struct cros_ec_command fields to not
use pointers for the input and output buffers and use fixed length
arrays instead.
This change was made because the cros_ec ioctl API uses that struct
The MFD driver should only have the logic to instantiate its child devices
and setup any shared resources that will be used by the subdevices drivers.
The cros_ec MFD is more complex than expected since it also has helpers to
communicate with the EC. So the driver will only get more bigger as
Hello,
Newer Chromebooks have more than one Embedded Controller (EC) in the
system. These additional ECs are connected through I2C with a host EC
which is the one that is connected to the Application Processor (AP)
through different transports (I2C, SPI or LPC).
So on these platforms,
From: Stephen Barber smbar...@chromium.org
Add proto v3 support to the SPI, I2C, and LPC.
Signed-off-by: Stephen Barber smbar...@chromium.org
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Heiko Stuebner he...@sntech.de
Reviewed-by: Gwendal Grignou
From: Stephen Barber smbar...@chromium.org
Update cros_ec_commands.h to the latest version in the EC
firmware sources and add power domain and passthru commands.
Also, update lightbar to use new command names.
Signed-off-by: Stephen Barber smbar...@chromium.org
Reviewed-by: Randall Spangler
On 4 June 2015 at 08:42, Geert Uytterhoeven ge...@linux-m68k.org wrote:
On Wed, Jun 3, 2015 at 11:26 PM, Michal Suchanek hramr...@gmail.com wrote:
On sunxi the SPI controller currently does not have DMA support and fails
any transfer larger than 63 bytes.
This is a driver limitation, not a
On 3 June 2015 at 21:57, grygorii.stras...@linaro.org
grygorii.stras...@linaro.org wrote:
Hi Tomeu,
On 05/28/2015 07:33 AM, Rob Herring wrote:
On Mon, May 25, 2015 at 9:53 AM, Tomeu Vizoso tomeu.viz...@collabora.com
wrote:
I have a problem with the panel on my Tegra Chromebook taking longer
From: Alexandru M Stan ams...@chromium.org
Some ECs need a little time for waking up before they can accept
SPI data at a high speed. Add a google,cros-ec-spi-pre-delay
property to the DT binding to configure this.
If this property isn't set, then no delay will be added. However,
if set it will
From: Alexandru M Stan ams...@chromium.org
Some ECs need a little time for waking up before they can accept
SPI data at a high speed. This is configurable via a DT property
google,cros-ec-spi-pre-delay.
This patch makes the cros_ec_spi driver to cause a delay before
the beginning of a SPI
From: Stephen Barber smbar...@chromium.org
Add support in cros_ec.c to handle EC host command protocol v3.
For v3+, probe for maximum shared protocol version and max
request, response, and passthrough sizes. For now, this will
always fall back to v2, since there is no bus-specific code
for
On Wed, Jun 03, 2015 at 09:26:42PM -, Michal Suchanek wrote:
The SPI NOR transfers mysteriously fail so add more debug prints about
SPI transactions.
Please try to only send patches to relevant people - the list of
recipients for this is so large that it only barely fits on a single
screen
Hello,
On 4 June 2015 at 11:16, Mark Brown broo...@kernel.org wrote:
On Wed, Jun 03, 2015 at 09:26:42PM -, Michal Suchanek wrote:
The SPI NOR transfers mysteriously fail so add more debug prints about
SPI transactions.
Please try to only send patches to relevant people - the list of
On Thu, Jun 04, 2015 at 11:30:15AM +0200, Geert Uytterhoeven wrote:
On Thu, Jun 4, 2015 at 11:16 AM, Mark Brown broo...@kernel.org wrote:
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -18,6 +18,7 @@
#include linux/interrupt.h
#include linux/delay.h
#include
Hi Marek,
On 2015년 06월 03일 17:26, Marek Szyprowski wrote:
One should not do any assumptions on the stare of the fimd hardware
during driver initialization, so to properly reset fimd before enabling
IOMMU, one should ensure that all power domains and clocks are really
enabled. This patch adds
On 2015년 06월 04일 22:08, Inki Dae wrote:
Hi Marek,
On 2015년 06월 03일 17:26, Marek Szyprowski wrote:
One should not do any assumptions on the stare of the fimd hardware
during driver initialization, so to properly reset fimd before enabling
IOMMU, one should ensure that all power domains and
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