On Tue, Aug 3, 2010 at 9:19 AM, Kukjin Kim kgene@samsung.com wrote:
MyungJoo Ham wrote:
On Mon, Aug 2, 2010 at 2:30 PM, Kukjin Kim kgene@samsung.com wrote:
MyungJoo Ham wrote:
Many MUX and clock dividers have a status bit so that users can wait
until the status is stable. When
S5PV210 CPUFREQ Initial Support.
This is a series of patches to enable CPUFREQ for S5PV210.
Although this works without PMIC's DVS support, it is not
as effective without DVS support as supposed. AVS is not
supported in this version.
At the patch revision v6, the following patches are updated
Early products of S5PV210, EVT0, had several errata that require
kernel to avoid using some parts/instructions of the CPU or to
add protection instructions. There are products with such early
production CPUs; thus, we want to distinguish them in kernel.
This patch is to distinguish such products.
S5PV210 requires msys/dsys info as well; thus, we've included those at
struct s3c_freq, which is used by CPUFREQ of S5PV210.
Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/plat-samsung/include/plat/cpu-freq.h |6 ++
CPUFREQ of S5PV210 uses different APLL settings according to
different CPU frequencies. We provide such settings values for
CPUFREQ at pll.h.
Note that at 1GHz of ARMCLK, APLL should be 1GHz and for other lower
ARMCLK, APLL should be 800MHz.
Signed-off-by: MyungJoo Ham myungjoo@samsung.com
The CPUFREQ driver requires an access to DMCx registers. We
define virtual addresses of DMCx registers.
Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/plat-s5p/include/plat/map-s5p.h |3 +++
1 files changed, 3
The CPUFREQ driver requires an access to DMCx registers. We
define physical addresses and mapping between physical and virtual
addresses of DMCx registers.
Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Previously, most of CLK_DIV/SRC register accessing mask and shift
values were used at arch/arm/mach-s5pv210/clock.c only; thus we
had not been using macros for these. However, as CPUFREQ uses
those shift and mask values as well, we'd better define them at a single
location, whose proper location
S5PV210 CPUFREQ Support.
This CPUFREQ may work without PMIC's DVS support. However, it is not
as effective without DVS support as supposed. AVS is not supported in
this version.
Note that CLK_SRC of some clocks including ARMCLK, G3D, G2D, MFC,
and ONEDRAM are modified directly without updating
This patch performs minor clocks cleanup for S5PC100 SoC. HSMMC special
clocks has been renamed back to sclk_mmc to match the common style of
clock names. This clock has been also added to sdhci clock source list.
The duplicate HCLK clock entry for sdhci-s3c has been disabled.
Signed-off-by:
This patch performs minor clocks cleanup for S5PV210 SoC. The duplicate
HCLK clock entry for sdhci-s3c has been disabled and the index of a reserved
entry has been fixed.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Hello,
This short patch series performs a little cleanup in clock source
definitions for S5PC100 and S5PV210 SoCs.
A complete list of patches:
[PATCH 1/2] ARM: S5PC100: cleanup hsmmc clock definitions
[PATCH 2/2] ARM: S5PV210: cleanup hsmmc clock definitions
Best regards
--
Marek Szyprowski
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