Mark Brown wrote:
Hi :-)
On Fri, Sep 17, 2010 at 06:58:52PM +0900, Kukjin Kim wrote:
This patch adds common regulator driver for samsung power domain.
A consumer of controlling power domain uses regulator framework API,
So new samsung pd driver is inserted into regulator directory.
This patch adds CPUFREQ for S5PV210/S5PC110.
Changes since v1:
- Added MOUT_DMC0 and SCLK_DMC0 for checking the dmc0 clock in CPUFREQ driver.
- Removed hardcoding of DRAM refresh counter.
- Added to calculate refresh counter function based on DRAM operation freq.
[PATCH v2 1/6] ARM: S5PV210:
From: Jaecheol Lee jc@samsung.com
This patch adds some CMU(Clock Management Unit) registers for
supporting CPUFREQ and some drivers.
Signed-off-by: Jaecheol Lee jc@samsung.com
Signed-off-by: Sangbeom Kim sbki...@samsung.com
---
arch/arm/mach-s5pv210/include/mach/regs-clock.h | 31
From: Jaecheol Lee jc@samsung.com
This patch adds MOUT_DMC0 and SCLK_DMC0 for checking the dmc0 clock
in CPUFREQ driver.
Signed-off-by: Jaecheol Lee jc@samsung.com
Signed-off-by: Sangbeom Kim sbki...@samsung.com
---
arch/arm/mach-s5pv210/clock.c | 32
From: Jaecheol Lee jc@samsung.com
This patch adds ARCH_HAS_CPUFREQ in arch/arm/Kconfig for S5PV210,
and updates mach-s5pv210/Makefile for supporting build CPUFREQ driver.
Signed-off-by: Jaecheol Lee jc@samsung.com
Signed-off-by: Sangbeom Kim sbki...@samsung.com
---
arch/arm/Kconfig
From: Jaecheol Lee jc@samsung.com
This patch adds CPUFREQ driver for supporting DFS(Dynamic Frequency Scaling).
Signed-off-by: Jaecheol Lee jc@samsung.com
Signed-off-by: Sangbeom Kim sbki...@samsung.com
---
Changes since v1:
- Removed hardcoding of DRAM refresh counter
- Added to
From: Jaecheol Lee jc@samsung.com
Current fout_apll has fixed rate value. So CPUFREQ driver gets
incorrect value when finding current CPU frequency. Because some
operation level need to change APLL.
Added get_rate function for fout_apll can give correct frequency
value when calling get_rate
From: Jaecheol Lee jc@samsung.com
This patch adds DMC(DRAM Memory Controller) map_desc table.
Because some driver such as CPUFREQ need to access DMC register.
Signed-off-by: Jaecheol Lee jc@samsung.com
Signed-off-by: Sangbeom Kim sbki...@samsung.com
---
arch/arm/mach-s5pv210/cpu.c
From: Jemings Ko jemi...@samsung.com
This patch adds support Watchdog Timer for S5PV310 and S5PC210.
Signed-off-by: Jemings Ko jemi...@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
NOTE: tested on SMDKV310 and SMDKC210.
arch/arm/Kconfig |1 +
From: Changhwan Youn chaos.y...@samsung.com
This patch adds support RTC for S5PV310 and S5PC210.
Signed-off-by: Changhwan Youn chaos.y...@samsung.com
Signed-off-by: Jemings Ko jemi...@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
NOTE: tested on SMDKV310 and SMDKC210.
On Mon, Sep 20, 2010 at 03:12:34PM +0900, Kukjin Kim wrote:
The reason the implementation is located in machine-specific code is that
the way to handle power domain in S5PV210 and S5PV310 is different but we
can handle this using platform_device_id.
Yes, I think it's reasonable to implement
Since commit 67a38950f0917aecfe1a3e46720d8bbb0020 there is no need
to set pixel clock for the s3c-fb driver's window information.
The correct pixel clock value can be automatically calculated from
the other screen parameters. This patch removes the redundant pixel clock
parameter.
Signed-off-by:
Hello,
This patch series updates the devices supported by Samsung Goni board.
The patch series has been prepared against latest kgene/for-next kernel
tree.
This is a second version of this patch series. It has been updated to
fix the issues reported by Kukjin Kim and Mark Brown.
The complete
Add the necessary definitions and mapping information to enable the
s3c-hsotg gadget to build.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
s5pv210 otg
---
arch/arm/mach-s5pv210/cpu.c |5 +
Add required platform definitions for S6E63M0 LCD controller on Samsung
Goni board.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-s5pv210/mach-goni.c | 71 +
1 files changed,
Add required platform definitions for si470x radio device on Samsung
Goni board.
Signed-off-by: Joonyoung Shim jy0922.s...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
arch/arm/mach-s5pv210/Kconfig |2 ++
Change the default upper_margin and vsync_len to get rid of repeated last
line on the display.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-s5pv210/mach-goni.c |4 ++--
1 files changed, 2 insertions(+), 2
Add required platform definitions for s3c-hsotg driver to enable usb
gadget support on Samsung Goni board.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-s5pv210/Kconfig |1 +
Add required platform definitions for MMC power regulators on Samsung
Goni board. GPIO pin GONI_EXT_FLASH_EN has been transferred from machine
startup code to fixed voltage regulator.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
On Mon, Sep 20, 2010 at 02:55:37PM +0200, Marek Szyprowski wrote:
Add required platform definitions for MMC power regulators on Samsung
Goni board. GPIO pin GONI_EXT_FLASH_EN has been transferred from machine
startup code to fixed voltage regulator.
Signed-off-by: Marek Szyprowski
In the commit f522886e202a34a2191dd5d471b3c4d46410a9a0 a merge conflict
in the sdhci-s3c driver been fixed. However the fix used incorrect
spinlock operation - it cause a race with sdhci interrupt service. The
correct way to solve it is to use spin_lock_irqsave/irqrestore() calls.
Signed-off-by:
Currently the code in gpiolib.c tries to register GPIO BANKA to BANKM.
ARCH_NR_GPIOS on the other hand is set only to 256, which would be the
equivalent of BANKA to BANKH. Thus the registration of all other banks will
fail.
This patch fixes this by setting S3C_GPIO_END according to the selected
Currently the {set,get}_pull callbacks of the s3c24xx_gpiocfg_default structure
are not initalized for the s3c2442 cpu type. This results in a NULL-pointer
deref upon calling s3c_gpio_setpull.
The s3c2442 has pulldowns instead of pullups compared to the s3c2440.
The method of controlling them is
On 20/09/10 23:00, Lars-Peter Clausen wrote:
Currently the {set,get}_pull callbacks of the s3c24xx_gpiocfg_default
structure
are not initalized for the s3c2442 cpu type. This results in a NULL-pointer
deref upon calling s3c_gpio_setpull.
The s3c2442 has pulldowns instead of pullups
On Mon, Sep 20, 2010 at 03:03:42PM +0200, Marek Szyprowski wrote:
In the commit f522886e202a34a2191dd5d471b3c4d46410a9a0 a merge conflict
in the sdhci-s3c driver been fixed. However the fix used incorrect
spinlock operation - it cause a race with sdhci interrupt service. The
correct way to
On Tue, 21 Sep 2010 02:17:11 +0100 Chris Ball c...@laptop.org wrote:
On Mon, Sep 20, 2010 at 03:03:42PM +0200, Marek Szyprowski wrote:
In the commit f522886e202a34a2191dd5d471b3c4d46410a9a0 a merge conflict
in the sdhci-s3c driver been fixed. However the fix used incorrect
spinlock
On 09/21/2010 01:41 AM, Ben Dooks wrote:
On 20/09/10 23:00, Lars-Peter Clausen wrote:
Currently the {set,get}_pull callbacks of the s3c24xx_gpiocfg_default structure
are not initalized for the s3c2442 cpu type. This results in a NULL-pointer
deref upon calling s3c_gpio_setpull.
The s3c2442
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