date:20111026

[PATCH 3/3] ARM: EXYNOS: Support ASV for Exynos4210

2011-10-26 Thread Jongpill Lee

This patch adds function for exynos4210's asv driver.
On Exynos4210, we can get ASV result using by HPM and IDS value.
And asv result is sent through INFORM2 register.

Signed-off-by: Jongpill Lee 
---
 arch/arm/mach-exynos4/Makefile  |2 +-
 arch/arm/mach-exynos4/asv-4210.c|  338 +++
 arch/arm/mach-exynos4/asv.c |8 +
 arch/arm/mach-exynos4/include/mach/asv.h|2 +
 arch/arm/mach-exynos4/include/mach/map.h|2 +
 arch/arm/mach-exynos4/include/mach/regs-clock.h |   18 ++
 arch/arm/mach-exynos4/include/mach/regs-iem.h   |   27 ++
 7 files changed, 396 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-exynos4/asv-4210.c
 create mode 100644 arch/arm/mach-exynos4/include/mach/regs-iem.h

diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 0f3affe..8627669 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -12,7 +12,7 @@ obj-  :=
 
 # Core support for EXYNOS4 system
 
-obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o asv.o
+obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o asv.o 
asv-4210.o
 obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o irq-eint.o dma.o pmu.o
 obj-$(CONFIG_CPU_EXYNOS4210)   += clock-exynos4210.o
 obj-$(CONFIG_SOC_EXYNOS4212)   += clock-exynos4212.o
diff --git a/arch/arm/mach-exynos4/asv-4210.c b/arch/arm/mach-exynos4/asv-4210.c
new file mode 100644
index 000..81a1c67
--- /dev/null
+++ b/arch/arm/mach-exynos4/asv-4210.c
@@ -0,0 +1,338 @@
+/* linux/arch/arm/mach-exynos/asv-4210.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * EXYNOS4210 - ASV(Adaptive Supply Voltage) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include 
+#include 
+#include 
+
+enum target_asv {
+   EXYNOS4210_1200,
+   EXYNOS4210_1400,
+   EXYNOS4210_SINGLE_1200,
+};
+
+struct asv_judge_table exynos4210_1200_limit[] = {
+   /* HPM , IDS */
+   {8 , 4},
+   {11 , 8},
+   {14 , 12},
+   {18 , 17},
+   {21 , 27},
+   {23 , 45},
+   {25 , 55},
+};
+
+static struct asv_judge_table exynos4210_1400_limit[] = {
+   /* HPM , IDS */
+   {13 , 8},
+   {17 , 12},
+   {22 , 32},
+   {26 , 52},
+};
+
+static struct asv_judge_table exynos4210_single_1200_limit[] = {
+   /* HPM , IDS */
+   {8 , 4},
+   {14 , 12},
+   {21 , 27},
+   {25 , 55},
+};
+
+static int exynos4210_check_vdd_arm(void)
+{
+   /* It will be support */
+   return 0;
+}
+
+static int exynos4210_asv_pre_clock_init(void)
+{
+   struct clk *clk_hpm;
+   struct clk *clk_copy;
+   struct clk *clk_parent;
+
+   /* PWI clock setting */
+   clk_copy = clk_get(NULL, "sclk_pwi");
+   if (IS_ERR(clk_copy)) {
+   pr_info("EXYNOS4210: ASV : SCLK_PWI clock get error\n");
+   return -EINVAL;
+   } else {
+   clk_parent = clk_get(NULL, "xusbxti");
+
+   if (IS_ERR(clk_parent)) {
+   pr_info("EXYNOS4210: ASV: MOUT_APLL clock get error\n");
+   clk_put(clk_copy);
+   return -EINVAL;
+   }
+   if (clk_set_parent(clk_copy, clk_parent))
+   pr_info("EXYNOS4210: ASV: Unable to set parent %s of 
clock %s.\n",
+   clk_parent->name, clk_copy->name);
+
+   clk_put(clk_parent);
+   }
+   clk_set_rate(clk_copy, 480);
+
+   clk_put(clk_copy);
+
+   /* HPM clock setting */
+   clk_copy = clk_get(NULL, "dout_copy");
+   if (IS_ERR(clk_copy)) {
+   pr_info("EXYNOS4210: ASV: DOUT_COPY clock get error\n");
+   return -EINVAL;
+   } else {
+   clk_parent = clk_get(NULL, "mout_mpll");
+   if (IS_ERR(clk_parent)) {
+   pr_info("EXYNOS4210: ASV: MOUT_APLL clock get error\n");
+   clk_put(clk_copy);
+   return -EINVAL;
+   }
+   if (clk_set_parent(clk_copy, clk_parent))
+   pr_info("EXYNOS4210: ASV: Unable to set parent %s of 
clock %s.\n",
+   clk_parent->name, clk_copy->name);
+
+   clk_put(clk_parent);
+   }
+
+   clk_set_rate(clk_copy, (400 * 1000 * 1000));
+
+   clk_put(clk_copy);
+
+   clk_hpm = clk_get(NULL, "sclk_hpm");
+   if (IS_ERR(clk_hpm)) {
+   pr_info("EXYNOS4210: ASV: Fail to get sclk_hpm\n");
+   return -EINVAL;
+   }
+
+   clk_set_rate(clk_hpm, (200 * 1000 * 1000))

[PATCH 1/3] ARM: EXYNOS: Add ASV feature for Exynos4 series

2011-10-26 Thread Jongpill Lee

This patch adds ASV feature for exynos4 seires.
Asv(Adoptive support voltage) feature support to get spec of SoC.
And we can use to adjust voltage for operation SoC usign by ASV result.

Signed-off-by: Jongpill Lee 
---
 arch/arm/mach-exynos4/Makefile   |2 +-
 arch/arm/mach-exynos4/asv.c  |   78 ++
 arch/arm/mach-exynos4/include/mach/asv.h |   42 
 3 files changed, 121 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-exynos4/asv.c
 create mode 100644 arch/arm/mach-exynos4/include/mach/asv.h

diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 2bb18f4..0f3affe 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -12,7 +12,7 @@ obj-  :=
 
 # Core support for EXYNOS4 system
 
-obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o
+obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o asv.o
 obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o irq-eint.o dma.o pmu.o
 obj-$(CONFIG_CPU_EXYNOS4210)   += clock-exynos4210.o
 obj-$(CONFIG_SOC_EXYNOS4212)   += clock-exynos4212.o
diff --git a/arch/arm/mach-exynos4/asv.c b/arch/arm/mach-exynos4/asv.c
new file mode 100644
index 000..498fac0
--- /dev/null
+++ b/arch/arm/mach-exynos4/asv.c
@@ -0,0 +1,78 @@
+/* linux/arch/arm/mach-exynos4/asv.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * EXYNOS4 - ASV(Adaptive Supply Voltage) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+static struct samsung_asv *exynos_asv;
+
+static int __init exynos_asv_init(void)
+{
+   exynos_asv = kzalloc(sizeof(struct samsung_asv), GFP_KERNEL);
+   if (!exynos_asv)
+   goto out1;
+
+   /* I will add asv driver of exynos4 series to regist */
+
+   if (exynos_asv->check_vdd_arm) {
+   if (exynos_asv->check_vdd_arm()) {
+   pr_info("EXYNOS: It is wrong vdd_arm\n");
+   goto out2;
+   }
+   }
+
+   /* Get HPM Delay value */
+   if (exynos_asv->get_hpm) {
+   if (exynos_asv->get_hpm(exynos_asv)) {
+   pr_info("EXYNOS: Fail to get HPM Value\n");
+   goto out2;
+   }
+   } else {
+   pr_info("EXYNOS: There is no get hpm function\n");
+   goto out2;
+   }
+
+   /* Get IDS ARM Value */
+   if (exynos_asv->get_ids) {
+   if (exynos_asv->get_ids(exynos_asv)) {
+   pr_info("EXYNOS: Fail to get IDS Value\n");
+   goto out2;
+   }
+   } else {
+   pr_info("EXYNOS: There is no get ids function\n");
+   goto out2;
+   }
+
+   if (exynos_asv->store_result) {
+   if (exynos_asv->store_result(exynos_asv)) {
+   pr_info("EXYNOS: Can not success to store result\n");
+   goto out2;
+   }
+   } else {
+   pr_info("EXYNOS: No store_result function\n");
+   goto out2;
+   }
+
+   return 0;
+out2:
+   kfree(exynos_asv);
+out1:
+   return -EINVAL;
+}
+device_initcall_sync(exynos_asv_init);
diff --git a/arch/arm/mach-exynos4/include/mach/asv.h 
b/arch/arm/mach-exynos4/include/mach/asv.h
new file mode 100644
index 000..038a872
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/asv.h
@@ -0,0 +1,42 @@
+/* linux/arch/arm/mach-exynos4/include/mach/asv.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * EXYNOS4 - Adoptive Support Voltage Header file
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_ASV_H
+#define __ASM_ARCH_ASV_H __FILE__
+
+#define JUDGE_TABLE_ENDNULL
+
+#define LOOP_CNT   10
+
+struct asv_judge_table {
+   unsigned int hpm_limit; /* HPM value to decide group of target */
+   unsigned int ids_limit; /* IDS value to decide group of target */
+};
+
+struct samsung_asv {
+   unsigned int pkg_id;/* fused value for pakage */
+   unsigned int ids_offset;/* ids_offset of chip */
+   unsigned int ids_mask;  /* ids_mask of chip */
+   unsigned int hpm_result;/* hpm value of chip */
+   unsigned int ids_result;/* ids value of chip */
+   int (*check_vdd_arm)(void); /* check vdd_arm value, this 
function is selectab

[PATCH 2/3] ARM: EXYNOS: Add clock for Exynos4210 asv feature

2011-10-26 Thread Jongpill Lee

This patch adds clock for exynos4210 asv feature
which name is sclk_pwi,sclk_hpm,dout_copy.
These clock is used for HPM devices

Signed-off-by: Jongpill Lee 
---
 arch/arm/mach-exynos4/clock.c |   35 ++-
 1 files changed, 34 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index db61691..230f851 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -306,6 +306,25 @@ static struct clksrc_clk clk_periphclk = {
.reg_div= { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
 };
 
+static struct clk *clkset_mout_hpm_list[] = {
+   [0] = &clk_mout_apll.clk,
+   [1] = &clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources clkset_sclk_hpm = {
+   .sources= clkset_mout_hpm_list,
+   .nr_sources = ARRAY_SIZE(clkset_mout_hpm_list),
+};
+
+static struct clksrc_clk clk_dout_copy = {
+   .clk= {
+   .name   = "dout_copy",
+   },
+   .sources = &clkset_sclk_hpm,
+   .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 20, .size = 1 },
+   .reg_div = { .reg = S5P_CLKDIV_CPU1, .shift = 0, .size = 3 },
+};
+
 /* Core list of CMU_CORE side */
 
 struct clk *clkset_corebus_list[] = {
@@ -1239,7 +1258,20 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit= (1 << 16),
},
.reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
-   }
+   }, {
+   .clk= {
+   .name   = "sclk_hpm",
+   .parent = &clk_dout_copy.clk,
+   },
+   .reg_div = { .reg = S5P_CLKDIV_CPU1, .shift = 4, .size = 3 },
+   }, {
+   .clk= {
+   .name   = "sclk_pwi",
+   },
+   .sources = &clkset_group,
+   .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 16, .size = 4 },
+   .reg_div = { .reg = S5P_CLKDIV_DMC1, .shift = 8, .size = 4 },
+   },
 };
 
 /* Clock initialization code */
@@ -1253,6 +1285,7 @@ static struct clksrc_clk *sysclks[] = {
&clk_armclk,
&clk_aclk_corem0,
&clk_aclk_cores,
+   &clk_dout_copy,
&clk_aclk_corem1,
&clk_periphclk,
&clk_mout_corebus,
-- 
1.7.1

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[PATCH 0/3] ASV support for Exynos4 series

2011-10-26 Thread Jongpill Lee

[PATCH 1/3] ARM: EXYNOS: Add ASV feature for Exynos4 series
[PATCH 2/3] ARM: EXYNOS: Add clock for Exynos4210 asv feature
[PATCH 3/3] ARM: EXYNOS: Support ASV for Exynos4210
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Re: [PATCH V5 1/3] SDHCI: S3C: Use generic clock names for sdhci bus clock options

2011-10-26 Thread Chris Ball

Hi Rajeshwari, Kukjin,

On Fri, Oct 14 2011, Rajeshwari Shinde wrote:
> This patch modifies the driver to stop depending on the clock names
> being passed from the platform and switch over to bus clock lookup
> using generic clock names.
>
> Signed-off-by: Rajeshwari Shinde 
> ---
>  drivers/mmc/host/sdhci-s3c.c |6 ++
>  1 files changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
> index 82709b6..a5fde87 100644
> --- a/drivers/mmc/host/sdhci-s3c.c
> +++ b/drivers/mmc/host/sdhci-s3c.c
> @@ -435,14 +435,12 @@ static int __devinit sdhci_s3c_probe(struct 
> platform_device *pdev)
>  
>   for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
>   struct clk *clk;
> - char *name = pdata->clocks[ptr];
> + char name[14];
>  
> - if (name == NULL)
> - continue;
> + sprintf(name, "mmc_busclk.%d", ptr);

Let's use snprintf() here instead -- it's better to have fewer uses of
sprintf() to audit.

>   clk = clk_get(dev, name);
>   if (IS_ERR(clk)) {
> - dev_err(dev, "failed to get clock %s\n", name);
>   continue;
>   }

Thanks,

- Chris.
-- 
Chris Ball  
One Laptop Per Child
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Re: [PATCH RESEND V4] mmc: core: HS200 mode support for eMMC 4.5

2011-10-26 Thread Chris Ball

Hi Girish,

On Wed, Oct 26 2011, Girish K S wrote:
> This patch adds the support of the HS200 bus speed for eMMC 4.5 devices.
> The eMMC 4.5 devices have support for 200MHz bus speed.The mmc core and
> host modules have been touched to add support for this module.
>
> It is necessary to know the card type in the sdhci.c file to add support
> for eMMC tuning function. So card.h file is included to import the card
> data structure.
>
> cc: Chris Ball 
> Signed-off-by: Girish K S 

The long case statements and conditionals in this patch make it pretty
dense/ugly -- can you think of a way to avoid doing this to the code?
Also, it would be good to hear if anyone else has tested/is using this
patch.

Is having a new mmc_card_hs200() test desirable, compared to just
reusing mmc_card_highspeed() and checking the ext_csd.card_type?

Thanks,

- Chris.
-- 
Chris Ball  
One Laptop Per Child
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[PATCH] ARM: EXYNOS4: Enable Bluetooth on ORIGEN

2011-10-26 Thread Sangwook Lee

This patch enables Bluetooth support on ORIGEN board.

Signed-off-by: Sangwook 
---
 arch/arm/mach-exynos4/mach-origen.c |   32 
 1 files changed, 32 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos4/mach-origen.c 
b/arch/arm/mach-exynos4/mach-origen.c
index f80b563..f8c50d7 100644
--- a/arch/arm/mach-exynos4/mach-origen.c
+++ b/arch/arm/mach-exynos4/mach-origen.c
@@ -20,6 +20,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -232,6 +233,7 @@ static struct regulator_init_data __initdata 
max8997_ldo9_data = {
.min_uV = 280,
.max_uV = 280,
.apply_uV   = 1,
+   .always_on  = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem  = {
.disabled   = 1,
@@ -275,6 +277,7 @@ static struct regulator_init_data __initdata 
max8997_ldo14_data = {
.min_uV = 180,
.max_uV = 180,
.apply_uV   = 1,
+   .always_on  = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem  = {
.disabled   = 1,
@@ -290,6 +293,7 @@ static struct regulator_init_data __initdata 
max8997_ldo17_data = {
.min_uV = 330,
.max_uV = 330,
.apply_uV   = 1,
+   .always_on  = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem  = {
.disabled   = 1,
@@ -588,6 +592,21 @@ static struct s3c_fb_platdata origen_lcd_pdata __initdata 
= {
.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
 };
 
+/* Bluetooth rfkill gpio platform data */
+struct rfkill_gpio_platform_data origen_bt_pdata = {
+   .reset_gpio = EXYNOS4_GPX2(2),
+   .shutdown_gpio = -1,
+   .type = RFKILL_TYPE_BLUETOOTH,
+   .name = "origen-bt",
+};
+
+/* Bluetooth Platform device */
+static struct platform_device origen_device_bluetooth = {
+   .name = "rfkill_gpio",
+   .id = -1,
+   .dev.platform_data = &origen_bt_pdata,
+};
+
 static struct platform_device *origen_devices[] __initdata = {
&s3c_device_hsmmc2,
&s3c_device_hsmmc0,
@@ -615,6 +634,7 @@ static struct platform_device *origen_devices[] __initdata 
= {
&exynos4_device_pd[PD_MFC],
&origen_device_gpiokeys,
&origen_lcd_hv070wsa,
+   &origen_device_bluetooth,
 };
 
 /* LCD Backlight data */
@@ -628,6 +648,16 @@ static struct platform_pwm_backlight_data origen_bl_data = 
{
.pwm_period_ns  = 1000,
 };
 
+static void __init origen_bt_setup(void)
+{
+   gpio_request(EXYNOS4_GPA0(0), "GPIO BT_UART");
+   /* 4 UART Pins configuration */
+   s3c_gpio_cfgrange_nopull(EXYNOS4_GPA0(0), 4, S3C_GPIO_SFN(2));
+   /* Setup BT Reset, this gpio will be requesed by rfkill-gpio */
+   s3c_gpio_cfgpin(EXYNOS4_GPX2(2), S3C_GPIO_OUTPUT);
+   s3c_gpio_setpull(EXYNOS4_GPX2(2), S3C_GPIO_PULL_NONE);
+}
+
 static void s5p_tv_setup(void)
 {
/* Direct HPD to HDMI chip */
@@ -687,6 +717,8 @@ static void __init origen_machine_init(void)
s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
 
samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data);
+
+   origen_bt_setup();
 }
 
 MACHINE_START(ORIGEN, "ORIGEN")
-- 
1.7.4.1

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Re: [PATCH] ARM: mx5: Use CLKDEV_INIT for creating clk_lookup instance

2011-10-26 Thread Sascha Hauer

On Thu, Oct 20, 2011 at 05:19:51PM +0530, Padmavathi Venna wrote:
> A common macro CLKDEV_INIT was added for creating clk_lookup
> instance in include/linux/clkdev.h. So replace _REGISTER_CLOCK
> macro with CLKDEV_INIT.

The patches are fine this way. Let's wait until the trees from next are
merged. It's not necessary to risk merge conflicts for this cleanup.

Sascha

> 
> Suggested-by: Russell King 
> Acked-by: Amit Kucheria 
> Signed-off-by: Padmavathi Venna 
> ---
>  arch/arm/mach-mx5/clock-mx51-mx53.c |  149 
> +--
>  1 files changed, 71 insertions(+), 78 deletions(-)
> 
> diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c 
> b/arch/arm/mach-mx5/clock-mx51-mx53.c
> index 2b9bd1f..d198515 100644
> --- a/arch/arm/mach-mx5/clock-mx51-mx53.c
> +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
> @@ -1422,97 +1422,90 @@ DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, 
> MXC_CCM_CCGRx_CG6_OFFSET,
>  DEFINE_CLOCK(pata_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG0_OFFSET,
>   NULL, NULL, &ipg_clk, &spba_clk);
>  
> -#define _REGISTER_CLOCK(d, n, c) \
> -   { \
> - .dev_id = d, \
> - .con_id = n, \
> - .clk = &c,   \
> -   },
> -
>  static struct clk_lookup mx51_lookups[] = {
>   /* i.mx51 has the i.mx21 type uart */
> - _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
> - _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
> - _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
> - _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
> + CLKDEV_INIT("imx21-uart.0", NULL, &uart1_clk),
> + CLKDEV_INIT("imx21-uart.1", NULL, &uart2_clk),
> + CLKDEV_INIT("imx21-uart.2", NULL, &uart3_clk),
> + CLKDEV_INIT(NULL, "gpt", &gpt_clk),
>   /* i.mx51 has the i.mx27 type fec */
> - _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
> - _REGISTER_CLOCK("mxc_pwm.0", "pwm", pwm1_clk)
> - _REGISTER_CLOCK("mxc_pwm.1", "pwm", pwm2_clk)
> - _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
> - _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
> - _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk)
> - _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
> - _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_ahb_clk)
> - _REGISTER_CLOCK("mxc-ehci.0", "usb_phy1", usb_phy1_clk)
> - _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
> - _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_ahb_clk)
> - _REGISTER_CLOCK("mxc-ehci.2", "usb", usboh3_clk)
> - _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk)
> - _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
> - _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
> - _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
> - _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
> - _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
> - _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
> - _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
> + CLKDEV_INIT("imx27-fec.0", NULL, &fec_clk),
> + CLKDEV_INIT("mxc_pwm.0", "pwm", &pwm1_clk),
> + CLKDEV_INIT("mxc_pwm.1", "pwm", &pwm2_clk),
> + CLKDEV_INIT("imx-i2c.0", NULL, &i2c1_clk),
> + CLKDEV_INIT("imx-i2c.1", NULL, &i2c2_clk),
> + CLKDEV_INIT("imx-i2c.2", NULL, &hsi2c_clk),
> + CLKDEV_INIT("mxc-ehci.0", "usb", &usboh3_clk),
> + CLKDEV_INIT("mxc-ehci.0", "usb_ahb", &usb_ahb_clk),
> + CLKDEV_INIT("mxc-ehci.0", "usb_phy1", &usb_phy1_clk),
> + CLKDEV_INIT("mxc-ehci.1", "usb", &usboh3_clk),
> + CLKDEV_INIT("mxc-ehci.1", "usb_ahb", &usb_ahb_clk),
> + CLKDEV_INIT("mxc-ehci.2", "usb", &usboh3_clk),
> + CLKDEV_INIT("mxc-ehci.2", "usb_ahb", &usb_ahb_clk),
> + CLKDEV_INIT("fsl-usb2-udc", "usb", &usboh3_clk),
> + CLKDEV_INIT("fsl-usb2-udc", "usb_ahb", &ahb_clk),
> + CLKDEV_INIT("imx-keypad", NULL, &dummy_clk),
> + CLKDEV_INIT("mxc_nand", NULL, &nfc_clk),
> + CLKDEV_INIT("imx-ssi.0", NULL, &ssi1_clk),
> + CLKDEV_INIT("imx-ssi.1", NULL, &ssi2_clk),
> + CLKDEV_INIT("imx-ssi.2", NULL, &ssi3_clk),
>   /* i.mx51 has the i.mx35 type sdma */
> - _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
> - _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
> - _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk)
> - _REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk)
> - _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
> - _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
> + CLKDEV_INIT("imx35-sdma", NULL, &sdma_clk),
> + CLKDEV_INIT(NULL, "ckih", &ckih_clk),
> + CLKDEV_INIT(NULL, "ckih2", &ckih2_clk),
> + CLKDEV_INIT(NULL, "gpt_32k", &gpt_32k_clk),
> + CLKDEV_INIT("imx51-ecspi.0", NULL, &ecspi1_clk),
> + CLKDEV_INIT("imx51-ecspi.1", NULL, &ecspi2_clk),
>   /* i.mx51 has the i.mx35 type cspi */
> - _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk)
> - _REGISTER_CLOCK("sdhci-esdhc-imx51.0", NULL, esdhc1_clk)
> - _REGISTER_CLOCK("sdhci-esdhc-imx51.1", NULL, esdhc2_clk)
> - _REGISTER_CLOCK("sdhci-esdhc-imx51.2", NULL, esdhc3_clk)
> - _REGISTER_CLOCK("sdhci-

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