[PATCH 1/3] ARM: SAMSUNG: Add support for EXYNOS SS USB 3.0 DRD controller
Cc: Kukjin Kim kgene.kim at samsung.com Cc: Greg Kroah-Hartman gregkh at suse.de Cc: Felipe Balbi balbi at ti.com Adds DRD global register definitions and related platform data. Signed-off-by: Anton Tikhomirov av.tikhomi...@samsung.com --- .../include/plat/regs-usb3-exynos-drd.h| 305 arch/arm/plat-samsung/include/plat/udc-ss.h| 21 ++ arch/arm/plat-samsung/include/plat/usb-phy.h |1 + 3 files changed, 327 insertions(+), 0 deletions(-) create mode 100644 arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd.h create mode 100644 arch/arm/plat-samsung/include/plat/udc-ss.h diff --git a/arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd.h b/arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd.h new file mode 100644 index 000..7006dc4 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd.h @@ -0,0 +1,305 @@ +/* arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd.h + * + * Copyright (c) 2011 Samsung Electronics Co. Ltd + * Author: Anton Tikhomirov av.tikhomi...@samsung.com + * + * Exynos SuperSpeed USB 3.0 DRD Controller Global registers + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __SAMSUNG_PLAT_REGS_USB3_EXYNOS_DRD_H +#define __SAMSUNG_PLAT_REGS_USB3_EXYNOS_DRD_H __FILE__ + +#define EXYNOS_USB3_REG(x) (x) + +#define EXYNOS_USB3_GSBUSCFG0 EXYNOS_USB3_REG(0xC100) +#define EXYNOS_USB3_GSBUSCFG0_SBusStoreAndForward (1 12) +#define EXYNOS_USB3_GSBUSCFG0_DatBigEnd(1 11) +#define EXYNOS_USB3_GSBUSCFG0_INCR256BrstEna (1 7) +#define EXYNOS_USB3_GSBUSCFG0_INCR128BrstEna (1 6) +#define EXYNOS_USB3_GSBUSCFG0_INCR64BrstEna(1 5) +#define EXYNOS_USB3_GSBUSCFG0_INCR32BrstEna(1 4) +#define EXYNOS_USB3_GSBUSCFG0_INCR16BrstEna(1 3) +#define EXYNOS_USB3_GSBUSCFG0_INCR8BrstEna (1 2) +#define EXYNOS_USB3_GSBUSCFG0_INCR4BrstEna (1 1) +#define EXYNOS_USB3_GSBUSCFG0_INCRBrstEna (1 0) + +#define EXYNOS_USB3_GSBUSCFG1 EXYNOS_USB3_REG(0xC104) +#define EXYNOS_USB3_GSBUSCFG1_EN1KPAGE (1 12) +#define EXYNOS_USB3_GSBUSCFG1_BREQLIMIT_MASK (0xf 8) +#define EXYNOS_USB3_GSBUSCFG1_BREQLIMIT_SHIFT 8 +#define EXYNOS_USB3_GSBUSCFG1_BREQLIMIT(_x)((_x) 8) + + +#define EXYNOS_USB3_GTXTHRCFG EXYNOS_USB3_REG(0xC108) +#define EXYNOS_USB3_GTXTHRCFG_USBTxPktCntSel (1 29) +#define EXYNOS_USB3_GTXTHRCFG_USBTxPktCnt_MASK (0xf 24) +#define EXYNOS_USB3_GTXTHRCFG_USBTxPktCnt_SHIFT24 +#define EXYNOS_USB3_GTXTHRCFG_USBTxPktCnt(_x) ((_x) 24) +#define EXYNOS_USB3_GTXTHRCFG_USBMaxTxBurstSize_MASK (0xff 16) +#define EXYNOS_USB3_GTXTHRCFG_USBMaxTxBurstSize_SHIFT 16 +#define EXYNOS_USB3_GTXTHRCFG_USBMaxTxBurstSize(_x)((_x) 16) + + +#define EXYNOS_USB3_GRXTHRCFG EXYNOS_USB3_REG(0xC10C) +#define EXYNOS_USB3_GRXTHRCFG_USBRxPktCntSel (1 29) +#define EXYNOS_USB3_GRXTHRCFG_USBRxPktCnt_MASK (0xf 24) +#define EXYNOS_USB3_GRXTHRCFG_USBRxPktCnt_SHIFT24 +#define EXYNOS_USB3_GRXTHRCFG_USBRxPktCnt(_x) ((_x) 24) +#define EXYNOS_USB3_GRXTHRCFG_USBMaxRxBurstSize_MASK (0x1f 19) +#define EXYNOS_USB3_GRXTHRCFG_USBMaxRxBurstSize_SHIFT 19 +#define EXYNOS_USB3_GRXTHRCFG_USBMaxRxBurstSize(_x)((_x) 19) + + +#define EXYNOS_USB3_GCTL EXYNOS_USB3_REG(0xC110) +#define EXYNOS_USB3_GCTL_PwrDnScale_MASK (0x1fff 19) +#define EXYNOS_USB3_GCTL_PwrDnScale_SHIFT 19 +#define EXYNOS_USB3_GCTL_PwrDnScale(_x)((_x) 19) +#define EXYNOS_USB3_GCTL_U2RSTECN (1 16) +#define EXYNOS_USB3_GCTL_FRMSCLDWN_MASK(0x3 14) +#define EXYNOS_USB3_GCTL_FRMSCLDWN_SHIFT 14 +#define EXYNOS_USB3_GCTL_FRMSCLDWN(_x) ((_x) 14) +#define EXYNOS_USB3_GCTL_PrtCapDir_MASK(0x3 12) +#define EXYNOS_USB3_GCTL_PrtCapDir_SHIFT 12 +#define EXYNOS_USB3_GCTL_PrtCapDir(_x) ((_x) 12) +#define EXYNOS_USB3_GCTL_CoreSoftReset (1 11) +#define EXYNOS_USB3_GCTL_LocalLpBkEn (1 10) +#define EXYNOS_USB3_GCTL_LpbkEn(1 9) +#define EXYNOS_USB3_GCTL_DebugAttach (1 8) +#define EXYNOS_USB3_GCTL_RAMClkSel_MASK(0x3 6) +#define EXYNOS_USB3_GCTL_RAMClkSel_SHIFT 6 +#define EXYNOS_USB3_GCTL_RAMClkSel(_x) ((_x) 6) +#define EXYNOS_USB3_GCTL_ScaleDown_MASK(0x3 4) +#define EXYNOS_USB3_GCTL_ScaleDown_SHIFT 4 +#define EXYNOS_USB3_GCTL_ScaleDown(_x) ((_x) 4) +#define EXYNOS_USB3_GCTL_DisScramble
[PATCH 2/3] USB: SET SEL request definition
Cc: Kukjin Kim kgene.kim at samsung.com Cc: Greg Kroah-Hartman gregkh at suse.de Cc: Felipe Balbi balbi at ti.com Adds SET SEL standard request definition as defined by ch9 of the USB3.0 specification. Signed-off-by: Anton Tikhomirov av.tikhomi...@samsung.com --- include/linux/usb/ch9.h |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/linux/usb/ch9.h b/include/linux/usb/ch9.h index 61b2905..76ff771 100644 --- a/include/linux/usb/ch9.h +++ b/include/linux/usb/ch9.h @@ -88,6 +88,7 @@ #define USB_REQ_GET_INTERFACE 0x0A #define USB_REQ_SET_INTERFACE 0x0B #define USB_REQ_SYNCH_FRAME0x0C +#define USB_REQ_SET_SEL0x30 #define USB_REQ_SET_ENCRYPTION 0x0D/* Wireless USB */ #define USB_REQ_GET_ENCRYPTION 0x0E -- 1.7.1 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] USB: EXYNOS USB3.0 device controller driver
Hi, On Mon, Feb 06, 2012 at 05:13:28PM +0900, Anton Tikhomirov wrote: Cc: Kukjin Kim kgene.kim at samsung.com Cc: Greg Kroah-Hartman gregkh at suse.de Cc: Felipe Balbi balbi at ti.com you can add the correct email, actually, but they should follow your Signed-off-by line. Adds Exynos USB3.0 device controller driver to support USB peripherals on Exynos5 chips. Signed-off-by: Anton Tikhomirov av.tikhomi...@samsung.com --- drivers/usb/gadget/Kconfig | 13 + drivers/usb/gadget/Makefile|1 + drivers/usb/gadget/exynos_ss_udc.c | 2511 drivers/usb/gadget/exynos_ss_udc.h | 342 + 4 files changed, 2867 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/gadget/exynos_ss_udc.c create mode 100644 drivers/usb/gadget/exynos_ss_udc.h diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 7ecb68a..8d3bc6e 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -268,6 +268,19 @@ config USB_S3C_HSOTG The Samsung S3C64XX USB2.0 high-speed gadget controller integrated into the S3C64XX series SoC. +config USB_EXYNOS_SS_UDC + tristate EXYNOS SuperSpeed USB 3.0 Device controller + depends on EXYNOS_DEV_SS_UDC + select USB_GADGET_DUALSPEED + select USB_GADGET_SUPERSPEED + help + The Samsung Exynos SuperSpeed USB 3.0 device controller + integrated into the Exynos5 series SoC. + + Say y to link the driver statically, or m to build a + dynamically linked module called exynos_ss_udc and force all + gadget drivers to also be dynamically linked. + config USB_IMX tristate Freescale i.MX1 USB Peripheral Controller depends on ARCH_MXC diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index b7f6eef..092bc76 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_USB_FSL_QE)+= fsl_qe_udc.o obj-$(CONFIG_USB_CI13XXX_PCI)+= ci13xxx_pci.o obj-$(CONFIG_USB_S3C_HSOTG) += s3c-hsotg.o obj-$(CONFIG_USB_S3C_HSUDC) += s3c-hsudc.o +obj-$(CONFIG_USB_EXYNOS_SS_UDC) += exynos_ss_udc.o obj-$(CONFIG_USB_LANGWELL) += langwell_udc.o obj-$(CONFIG_USB_EG20T) += pch_udc.o obj-$(CONFIG_USB_MV_UDC) += mv_udc.o diff --git a/drivers/usb/gadget/exynos_ss_udc.c b/drivers/usb/gadget/exynos_ss_udc.c new file mode 100644 index 000..aaad33c --- /dev/null +++ b/drivers/usb/gadget/exynos_ss_udc.c @@ -0,0 +1,2511 @@ +/* linux/drivers/usb/gadget/exynos_ss_udc.c + * + * Copyright 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS SuperSpeed USB 3.0 Device Controlle driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include linux/kernel.h +#include linux/module.h +#include linux/spinlock.h +#include linux/interrupt.h +#include linux/platform_device.h +#include linux/dma-mapping.h +#include linux/delay.h +#include linux/io.h +#include linux/slab.h +#include linux/clk.h + +#include linux/usb/ch9.h +#include linux/usb/gadget.h + +#include asm/byteorder.h + +#include mach/map.h + +#include plat/regs-usb3-exynos-drd.h +#include plat/udc-ss.h +#include plat/usb-phy.h do _NOT_ depend on any arch-specific crap please. Registers can be defined on the C source code and other stuff could sit on linux/usb/ or linux/platform_data/ depending on what it is. I want to be able to compile this with whatever (cross) compiler I have available. +#include exynos_ss_udc.h + +static void exynos_ss_udc_kill_all_requests(struct exynos_ss_udc *udc, + struct exynos_ss_udc_ep *udc_ep, + int result); +static void exynos_ss_udc_complete_setup(struct usb_ep *ep, + struct usb_request *req); +static void exynos_ss_udc_complete_request(struct exynos_ss_udc *udc, +struct exynos_ss_udc_ep *udc_ep, +struct exynos_ss_udc_req *udc_req, +int result); +static void exynos_ss_udc_start_req(struct exynos_ss_udc *udc, + struct exynos_ss_udc_ep *udc_ep, + struct exynos_ss_udc_req *udc_req, + bool continuing); +static void exynos_ss_udc_ep_activate(struct exynos_ss_udc *udc, + struct exynos_ss_udc_ep *udc_ep); +static void exynos_ss_udc_ep_deactivate(struct exynos_ss_udc *udc, + struct exynos_ss_udc_ep *udc_ep); +static int exynos_ss_udc_start(struct usb_gadget *gadget, +struct
Re: [PATCH v3 2/2] mmc: sdhci-s3c: add platform data for the second capability
Hi,
On Mon, Feb 06 2012, Jaehoon Chung wrote:
This patch is added host_caps2 in sdhci-s3c.c
It's necessary that use the second capabilities.
And removed the duplicated host_caps.
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Changelog v3:
- based-on latest mmc-next tree
Changelog v2:
- remove the duplicated host_caps.
drivers/mmc/host/sdhci-s3c.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index d065e37..46b9782 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -521,9 +521,6 @@ static int __devinit sdhci_s3c_probe(struct
platform_device *pdev)
if (pdata-cd_type == S3C_SDHCI_CD_PERMANENT)
host-mmc-caps = MMC_CAP_NONREMOVABLE;
- if (pdata-host_caps)
- host-mmc-caps |= pdata-host_caps;
-
if (pdata-pm_caps)
host-mmc-pm_caps |= pdata-pm_caps;
@@ -547,6 +544,9 @@ static int __devinit sdhci_s3c_probe(struct
platform_device *pdev)
if (pdata-host_caps)
host-mmc-caps |= pdata-host_caps;
+ if (pdata-host_caps2)
+ host-mmc-caps2 |= pdata-host_caps2;
+
ret = sdhci_add_host(host);
if (ret) {
dev_err(dev, sdhci_add_host() failed\n);
In case you'd rather merge both of these via the samsung-soc tree:
Acked-by: Chris Ball c...@laptop.org
- Chris.
--
Chris Ball c...@laptop.org http://printf.net/
One Laptop Per Child
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Re: [PATCH 2/3] USB: SET SEL request definition
On Mon, Feb 06, 2012 at 05:12:33PM +0900, Anton Tikhomirov wrote: Cc: Kukjin Kim kgene.kim at samsung.com Cc: Greg Kroah-Hartman gregkh at suse.de Cc: Felipe Balbi balbi at ti.com What is that mess? It belongs, with real email addresses, below your signed-off-by line, if at all. Adds SET SEL standard request definition as defined by ch9 of the USB3.0 specification. Signed-off-by: Anton Tikhomirov av.tikhomi...@samsung.com --- include/linux/usb/ch9.h |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/linux/usb/ch9.h b/include/linux/usb/ch9.h index 61b2905..76ff771 100644 --- a/include/linux/usb/ch9.h +++ b/include/linux/usb/ch9.h @@ -88,6 +88,7 @@ #define USB_REQ_GET_INTERFACE0x0A #define USB_REQ_SET_INTERFACE0x0B #define USB_REQ_SYNCH_FRAME 0x0C +#define USB_REQ_SET_SEL 0x30 #define USB_REQ_SET_ENCRYPTION 0x0D/* Wireless USB */ #define USB_REQ_GET_ENCRYPTION 0x0E Why did you insert this out of order? greg please note my email address change as well k-h -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT PULL] Samsung fixes-2 for v3.3
Hi, On Mon, Jan 30, 2012 at 10:10 PM, Kukjin Kim kgene@samsung.com wrote: Hi Arnd, Olof, Please pull 2nd Samsung fixes for v3.3, from following: git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git v3.3-samsung-fixes-2 If any problems, please kindly let me know. Thanks, pulled. Sorry for the delay; overlooked it for the last batch. -Olof -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] misc: c2c: Add C2C(Chip to Chip) device driver for EXYNOS
On Sat, Feb 04, 2012 at 05:15:03PM +0900, Kisang Lee wrote:
Cc: Arnd Bergmann arnd at arndb.de
Cc: Greg Kroah-Hartman greg at kroah.com
Signed-off-by: Kisang Lee kisang80@samsung.com
What is a chip to chip driver? It looks like there is some overlap with
the remoteproc work that Ohad Ben-Cohen has been doing, or I think there
was also some work for communicating with things like basebands?
Perhaps even UIO?
+ if (opp_val == C2C_OPP100)
+ req_clk = c2c_con.clk_opp100;
+ else if (opp_val == C2C_OPP50)
+ req_clk = c2c_con.clk_opp50;
+ else if (opp_val == C2C_OPP25)
+ req_clk = c2c_con.clk_opp25;
This looks like a switch statement.
+ dev_info(c2c_con.c2c_dev, Get C2C sclk rate : %ld\n,
+ clk_get_rate(c2c_con.c2c_sclk));
+ dev_info(c2c_con.c2c_dev, Get C2C aclk rate : %ld\n,
+ clk_get_rate(c2c_con.c2c_aclk));
+ break;
+ default:
+ dev_info(c2c_con.c2c_dev, ---C2C Operation Number---\n);
+ dev_info(c2c_con.c2c_dev, 1. C2C Reset\n);
+ dev_info(c2c_con.c2c_dev, 2. Set OPP25\n);
+ dev_info(c2c_con.c2c_dev, 3. Set OPP50\n);
+ dev_info(c2c_con.c2c_dev, 4. Set OPP100\n);
These log messages probably shouldn't be in.
+static irqreturn_t c2c_sscm0_irq(int irq, void *data)
+{
+ /* Nothing here yet */
+ return IRQ_HANDLED;
+}
This doesn't look terribly clever - if the interrupt has been asserted
and we don't do anything to handle it won't we end up spinning for ever
with repeated calls to the interrupt handler?
+ if (opp_val == C2C_OPP100)
+ req_clk = c2c_con.clk_opp100;
+ else if (opp_val == C2C_OPP50)
+ req_clk = c2c_con.clk_opp50;
+ else if (opp_val == C2C_OPP25)
+ req_clk = c2c_con.clk_opp25;
This and the surrounding code looks a lot like the code I commented on
above - shouldn't this be factored out into a single function called
from both places?
+ /* resource for AP's SSCM region */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(pdev-dev, no memory resource defined(AP's SSCM)\n);
+ return -ENOENT;
+ }
devm_requets_and_ioremap() perhaps?
+#ifdef CONFIG_PM
+static int samsung_c2c_suspend(struct platform_device *dev, pm_message_t pm)
+{
+ /* Nothing here yet */
+ return 0;
+}
+
+static int samsung_c2c_resume(struct platform_device *dev)
+{
+ /* Nothing here yet */
+ return 0;
+}
+#else
+#define samsung_c2c_suspend NULL
+#define samsung_c2c_resume NULL
+#endif
No need to include this if it doesn't do anything.
+static struct platform_driver samsung_c2c_driver = {
+ .probe = samsung_c2c_probe,
+ .remove = __devexit_p(samsung_c2c_remove),
+ .suspend= samsung_c2c_suspend,
+ .resume = samsung_c2c_resume,
If you were including pm operations they should be in the pm_ops rather
than using the platform-specific variants - this makes it easier to do
things like runtime PM later.
+static int __init samsung_c2c_init(void)
+{
+ return platform_driver_register(samsung_c2c_driver);
+}
+module_init(samsung_c2c_init);
module_platform_driver().
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Re: [PATCH 4/4] [SCSI] ufshcd: SCSI error handling
On Mon, Feb 6, 2012 at 12:46 PM, Amit Sahrawat
amit.sahrawa...@gmail.com wrote:
Hi,
In function:
+static int ufshcd_abort(struct scsi_cmnd *cmd)
+{...
- int err;
+ int err = -1;
...
+ spin_lock_irqsave(host-host_lock, flags);
+ pos = (1 tag);
+
+ /* check if command is still pending */
+ if (!(hba-outstanding_reqs pos)) {
- err = -1;
- spin_unlock_irqrestore(host-host_lock, flags);
+ goto out;
+ }
...
...
+out:
+ spin_unlock_irqrestore(host-host_lock, flags);
+ return err;
+}
this will also take of matching out
spin_lock_irqsave()-spin_unlock_irqrestore() before exiting the
function.
That will not work again.
In case if (!(hba-outstanding_reqs pos)) is false,
i.e if the command for which the abort is issued still exists,
ufshcd_issue_tm_cmd() will be called and if no error returned
by the function, the code after out: will be executed. Which will
try to spin_unlock_irqrestore,
even though no lock has been acquired.
In function:
+static int
+ufshcd_issue_tm_cmd(struct ufs_hba *hba,
+ struct ufshcd_lrb *lrbp,
+ u8 tm_function)
...
+ spin_lock_irqsave(host-host_lock, flags);
+
+ /* If task management queue is full */
+ if (!ufshcd_is_tmq_full(hba-outstanding_tasks)) {
+ dev_err(hba-pdev-dev, Task management queue full\n);
I think this will map to a Buffered printf - which can potentially
result in BUG: Schedule while atomic()...
+ spin_unlock_irqrestore(host-host_lock, flags);
+ return err;
+ }
So, it could be like this:
ok, Thanks, I'll look into it.
+ spin_lock_irqsave(host-host_lock, flags);
+
+ /* If task management queue is full */
+ if (!ufshcd_is_tmq_full(hba-outstanding_tasks)) {
+ spin_unlock_irqrestore(host-host_lock, flags);
+ dev_err(hba-pdev-dev, Task management queue full\n);
+ return err;
+ }
Thanks Regards,
Amit Sahrawat
On Thu, Feb 2, 2012 at 10:27 AM, Vinayak Holikatti
vinholika...@gmail.com wrote:
From: Santosh Yaraganavi santos...@gmail.com
UFSHCD SCSI error handling includes following implementations,
- Abort task
- Device reset
- Host reset
Signed-off-by: Santosh Yaraganavi santos...@gmail.com
Signed-off-by: Vinayak Holikatti vinholika...@gmail.com
Reviewed-by: Arnd Bergmann a...@arndb.de
Reviewed-by: Saugata Das saugata@linaro.org
Reviewed-by: Vishak G visha...@samsung.com
Reviewed-by: Girish K S girish.shivananja...@linaro.org
---
drivers/scsi/ufs/ufshcd.c | 312
+
1 files changed, 312 insertions(+), 0 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 1bfae84..7589dd1 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -76,6 +76,8 @@
#define NULL 0
#endif /* NULL */
+#define UFSHCD_MAX_TM_SLOTS 0xFF
+
#define BYTES_TO_DWORDS(p) (p 2)
#define UFSHCD_MMIO_BASE (hba-mmio_base)
@@ -83,6 +85,7 @@ enum {
UFSHCD_MAX_CHANNEL = 1,
UFSHCD_MAX_ID = 1,
UFSHCD_MAX_LUNS = 8,
+ UFSHCD_MAX_TM_CMDS = 8,
UFSHCD_CMD_PER_LUN = 16,
UFSHCD_CAN_QUEUE = 32,
BYTES_128 = 128,
@@ -149,6 +152,7 @@ struct uic_command {
* @host: Scsi_Host instance of the driver
* @pdev: PCI device handle
* @lrb: local reference block
+ * @outstanding_tasks: Bits representing outstanding task requests
* @outstanding_reqs: Bits representing outstanding transfer requests
* @capabilities: UFS Controller Capabilities
* @nutrs: Transfer Request Queue depth supported by controller
@@ -192,6 +196,7 @@ struct ufs_hba {
struct ufshcd_lrb *lrb;
+ u32 outstanding_tasks;
u32 outstanding_reqs;
u32 capabilities;
@@ -200,6 +205,8 @@ struct ufs_hba {
u32 ufs_version;
struct uic_command active_uic_cmd;
+ wait_queue_head_t ufshcd_tm_wait_queue;
+ u8 tm_condition[UFSHCD_MAX_TM_CMDS];
u32 ufshcd_state;
u32 int_enable_mask;
@@ -278,6 +285,30 @@ static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb
*lrbp)
}
/**
+ * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
+ * @task_req_descp: pointer to utp_task_req_desc structure
+ *
+ * This function is used to get the OCS field from UTMRD
+ * Returns the OCS field in the UTMRD
+ */
+static inline int
+ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
+{
+ return task_req_descp-header.dword_2 MASK_OCS;
+}
+
+/**
+ * ufshcd_is_tmq_full - checks if the task management slots are full
+ * @outstanding_tasks: contains the task management doorbell value
+ *
+ * Returns 1 if a free slot available, 0 if task slots are full
+ */
+static inline int ufshcd_is_tmq_full(u32
Re: [PATCH 1/3] ARM: SAMSUNG: Add support for EXYNOS SS USB 3.0 DRD controller
On Mon, Feb 6, 2012 at 5:11 PM, Anton Tikhomirov av.tikhomi...@samsung.com wrote: Cc: Kukjin Kim kgene.kim at samsung.com Cc: Greg Kroah-Hartman gregkh at suse.de Cc: Felipe Balbi balbi at ti.com Adds DRD global register definitions and related platform data. Signed-off-by: Anton Tikhomirov av.tikhomi...@samsung.com Hi, --- .../include/plat/regs-usb3-exynos-drd.h | 305 If special reason, please move to the proper drivers/usb. Thank you, Kyungmin Park arch/arm/plat-samsung/include/plat/udc-ss.h | 21 ++ arch/arm/plat-samsung/include/plat/usb-phy.h | 1 + 3 files changed, 327 insertions(+), 0 deletions(-) create mode 100644 arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd.h create mode 100644 arch/arm/plat-samsung/include/plat/udc-ss.h diff --git a/arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd.h b/arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd.h new file mode 100644 index 000..7006dc4 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd.h @@ -0,0 +1,305 @@ +/* arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd.h + * + * Copyright (c) 2011 Samsung Electronics Co. Ltd + * Author: Anton Tikhomirov av.tikhomi...@samsung.com + * + * Exynos SuperSpeed USB 3.0 DRD Controller Global registers + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __SAMSUNG_PLAT_REGS_USB3_EXYNOS_DRD_H +#define __SAMSUNG_PLAT_REGS_USB3_EXYNOS_DRD_H __FILE__ + +#define EXYNOS_USB3_REG(x) (x) + +#define EXYNOS_USB3_GSBUSCFG0 EXYNOS_USB3_REG(0xC100) +#define EXYNOS_USB3_GSBUSCFG0_SBusStoreAndForward (1 12) +#define EXYNOS_USB3_GSBUSCFG0_DatBigEnd (1 11) +#define EXYNOS_USB3_GSBUSCFG0_INCR256BrstEna (1 7) +#define EXYNOS_USB3_GSBUSCFG0_INCR128BrstEna (1 6) +#define EXYNOS_USB3_GSBUSCFG0_INCR64BrstEna (1 5) +#define EXYNOS_USB3_GSBUSCFG0_INCR32BrstEna (1 4) +#define EXYNOS_USB3_GSBUSCFG0_INCR16BrstEna (1 3) +#define EXYNOS_USB3_GSBUSCFG0_INCR8BrstEna (1 2) +#define EXYNOS_USB3_GSBUSCFG0_INCR4BrstEna (1 1) +#define EXYNOS_USB3_GSBUSCFG0_INCRBrstEna (1 0) + +#define EXYNOS_USB3_GSBUSCFG1 EXYNOS_USB3_REG(0xC104) +#define EXYNOS_USB3_GSBUSCFG1_EN1KPAGE (1 12) +#define EXYNOS_USB3_GSBUSCFG1_BREQLIMIT_MASK (0xf 8) +#define EXYNOS_USB3_GSBUSCFG1_BREQLIMIT_SHIFT 8 +#define EXYNOS_USB3_GSBUSCFG1_BREQLIMIT(_x) ((_x) 8) + + +#define EXYNOS_USB3_GTXTHRCFG EXYNOS_USB3_REG(0xC108) +#define EXYNOS_USB3_GTXTHRCFG_USBTxPktCntSel (1 29) +#define EXYNOS_USB3_GTXTHRCFG_USBTxPktCnt_MASK (0xf 24) +#define EXYNOS_USB3_GTXTHRCFG_USBTxPktCnt_SHIFT 24 +#define EXYNOS_USB3_GTXTHRCFG_USBTxPktCnt(_x) ((_x) 24) +#define EXYNOS_USB3_GTXTHRCFG_USBMaxTxBurstSize_MASK (0xff 16) +#define EXYNOS_USB3_GTXTHRCFG_USBMaxTxBurstSize_SHIFT 16 +#define EXYNOS_USB3_GTXTHRCFG_USBMaxTxBurstSize(_x) ((_x) 16) + + +#define EXYNOS_USB3_GRXTHRCFG EXYNOS_USB3_REG(0xC10C) +#define EXYNOS_USB3_GRXTHRCFG_USBRxPktCntSel (1 29) +#define EXYNOS_USB3_GRXTHRCFG_USBRxPktCnt_MASK (0xf 24) +#define EXYNOS_USB3_GRXTHRCFG_USBRxPktCnt_SHIFT 24 +#define EXYNOS_USB3_GRXTHRCFG_USBRxPktCnt(_x) ((_x) 24) +#define EXYNOS_USB3_GRXTHRCFG_USBMaxRxBurstSize_MASK (0x1f 19) +#define EXYNOS_USB3_GRXTHRCFG_USBMaxRxBurstSize_SHIFT 19 +#define EXYNOS_USB3_GRXTHRCFG_USBMaxRxBurstSize(_x) ((_x) 19) + + +#define EXYNOS_USB3_GCTL EXYNOS_USB3_REG(0xC110) +#define EXYNOS_USB3_GCTL_PwrDnScale_MASK (0x1fff 19) +#define EXYNOS_USB3_GCTL_PwrDnScale_SHIFT 19 +#define EXYNOS_USB3_GCTL_PwrDnScale(_x) ((_x) 19) +#define EXYNOS_USB3_GCTL_U2RSTECN (1 16) +#define EXYNOS_USB3_GCTL_FRMSCLDWN_MASK (0x3 14) +#define EXYNOS_USB3_GCTL_FRMSCLDWN_SHIFT 14 +#define EXYNOS_USB3_GCTL_FRMSCLDWN(_x) ((_x) 14) +#define EXYNOS_USB3_GCTL_PrtCapDir_MASK (0x3 12) +#define EXYNOS_USB3_GCTL_PrtCapDir_SHIFT 12 +#define EXYNOS_USB3_GCTL_PrtCapDir(_x) ((_x) 12) +#define EXYNOS_USB3_GCTL_CoreSoftReset (1 11) +#define EXYNOS_USB3_GCTL_LocalLpBkEn (1 10) +#define EXYNOS_USB3_GCTL_LpbkEn (1 9) +#define EXYNOS_USB3_GCTL_DebugAttach (1 8) +#define EXYNOS_USB3_GCTL_RAMClkSel_MASK (0x3 6) +#define EXYNOS_USB3_GCTL_RAMClkSel_SHIFT 6 +#define EXYNOS_USB3_GCTL_RAMClkSel(_x)
Re: [PATCH v3 2/2] mmc: sdhci-s3c: add platform data for the second capability
Hi Kukjin..
I want to merge these patchset with Chris's ACK at Samsung-SoC tree
Samsung-SoC need to set MMC_CAP2_BROKEN_VOLTAGE..So this patch is need.
Best Regards,
Jaehoon Chung
On 02/06/2012 08:19 PM, Chris Ball wrote:
Hi,
On Mon, Feb 06 2012, Jaehoon Chung wrote:
This patch is added host_caps2 in sdhci-s3c.c
It's necessary that use the second capabilities.
And removed the duplicated host_caps.
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Changelog v3:
- based-on latest mmc-next tree
Changelog v2:
- remove the duplicated host_caps.
drivers/mmc/host/sdhci-s3c.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index d065e37..46b9782 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -521,9 +521,6 @@ static int __devinit sdhci_s3c_probe(struct
platform_device *pdev)
if (pdata-cd_type == S3C_SDHCI_CD_PERMANENT)
host-mmc-caps = MMC_CAP_NONREMOVABLE;
-if (pdata-host_caps)
-host-mmc-caps |= pdata-host_caps;
-
if (pdata-pm_caps)
host-mmc-pm_caps |= pdata-pm_caps;
@@ -547,6 +544,9 @@ static int __devinit sdhci_s3c_probe(struct
platform_device *pdev)
if (pdata-host_caps)
host-mmc-caps |= pdata-host_caps;
+if (pdata-host_caps2)
+host-mmc-caps2 |= pdata-host_caps2;
+
ret = sdhci_add_host(host);
if (ret) {
dev_err(dev, sdhci_add_host() failed\n);
In case you'd rather merge both of these via the samsung-soc tree:
Acked-by: Chris Ball c...@laptop.org
- Chris.
--
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Re: [PATCH 3/3] USB: EXYNOS USB3.0 device controller driver
Hi Felipe, I'm sorry for the misunderstanding from our side. We will implement the glue layer for our Exynos SoC and reuse the dwc3 driver. Thank you. Felipe Balbi wrote: Hi, On Mon, Feb 06, 2012 at 05:13:28PM +0900, Anton Tikhomirov wrote: Cc: Kukjin Kim kgene.kim at samsung.com Cc: Greg Kroah-Hartman gregkh at suse.de Cc: Felipe Balbi balbi at ti.com you can add the correct email, actually, but they should follow your Signed-off-by line. Adds Exynos USB3.0 device controller driver to support USB peripherals on Exynos5 chips. Signed-off-by: Anton Tikhomirov av.tikhomi...@samsung.com --- drivers/usb/gadget/Kconfig | 13 + drivers/usb/gadget/Makefile|1 + drivers/usb/gadget/exynos_ss_udc.c | 2511 drivers/usb/gadget/exynos_ss_udc.h | 342 + 4 files changed, 2867 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/gadget/exynos_ss_udc.c create mode 100644 drivers/usb/gadget/exynos_ss_udc.h diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 7ecb68a..8d3bc6e 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -268,6 +268,19 @@ config USB_S3C_HSOTG The Samsung S3C64XX USB2.0 high-speed gadget controller integrated into the S3C64XX series SoC. +config USB_EXYNOS_SS_UDC + tristate EXYNOS SuperSpeed USB 3.0 Device controller + depends on EXYNOS_DEV_SS_UDC + select USB_GADGET_DUALSPEED + select USB_GADGET_SUPERSPEED + help + The Samsung Exynos SuperSpeed USB 3.0 device controller + integrated into the Exynos5 series SoC. + + Say y to link the driver statically, or m to build a + dynamically linked module called exynos_ss_udc and force all + gadget drivers to also be dynamically linked. + config USB_IMX tristate Freescale i.MX1 USB Peripheral Controller depends on ARCH_MXC diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index b7f6eef..092bc76 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_USB_FSL_QE) += fsl_qe_udc.o obj-$(CONFIG_USB_CI13XXX_PCI) += ci13xxx_pci.o obj-$(CONFIG_USB_S3C_HSOTG)+= s3c-hsotg.o obj-$(CONFIG_USB_S3C_HSUDC)+= s3c-hsudc.o +obj-$(CONFIG_USB_EXYNOS_SS_UDC) += exynos_ss_udc.o obj-$(CONFIG_USB_LANGWELL) += langwell_udc.o obj-$(CONFIG_USB_EG20T)+= pch_udc.o obj-$(CONFIG_USB_MV_UDC) += mv_udc.o diff --git a/drivers/usb/gadget/exynos_ss_udc.c b/drivers/usb/gadget/exynos_ss_udc.c new file mode 100644 index 000..aaad33c --- /dev/null +++ b/drivers/usb/gadget/exynos_ss_udc.c @@ -0,0 +1,2511 @@ +/* linux/drivers/usb/gadget/exynos_ss_udc.c + * + * Copyright 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS SuperSpeed USB 3.0 Device Controlle driver + * + * This program is free software; you can redistribute it and/or +modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include linux/kernel.h +#include linux/module.h +#include linux/spinlock.h +#include linux/interrupt.h +#include linux/platform_device.h +#include linux/dma-mapping.h +#include linux/delay.h +#include linux/io.h +#include linux/slab.h +#include linux/clk.h + +#include linux/usb/ch9.h +#include linux/usb/gadget.h + +#include asm/byteorder.h + +#include mach/map.h + +#include plat/regs-usb3-exynos-drd.h #include plat/udc-ss.h +#include plat/usb-phy.h do _NOT_ depend on any arch-specific crap please. Registers can be defined on the C source code and other stuff could sit on linux/usb/ or linux/platform_data/ depending on what it is. I want to be able to compile this with whatever (cross) compiler I have available. +#include exynos_ss_udc.h + +static void exynos_ss_udc_kill_all_requests(struct exynos_ss_udc *udc, + struct exynos_ss_udc_ep *udc_ep, + int result); +static void exynos_ss_udc_complete_setup(struct usb_ep *ep, +struct usb_request *req); +static void exynos_ss_udc_complete_request(struct exynos_ss_udc *udc, + struct exynos_ss_udc_ep *udc_ep, + struct exynos_ss_udc_req *udc_req, + int result); +static void exynos_ss_udc_start_req(struct exynos_ss_udc *udc, + struct exynos_ss_udc_ep *udc_ep, + struct exynos_ss_udc_req *udc_req, + bool continuing); +static void exynos_ss_udc_ep_activate(struct exynos_ss_udc *udc, + struct exynos_ss_udc_ep *udc_ep);
Re: [PATCH 2/3] USB: SET SEL request definition
Hi, Greg KH wrote: On Mon, Feb 06, 2012 at 05:12:33PM +0900, Anton Tikhomirov wrote: Cc: Kukjin Kim kgene.kim at samsung.com Cc: Greg Kroah-Hartman gregkh at suse.de Cc: Felipe Balbi balbi at ti.com What is that mess? It belongs, with real email addresses, below your signed-off-by line, if at all. Adds SET SEL standard request definition as defined by ch9 of the USB3.0 specification. Signed-off-by: Anton Tikhomirov av.tikhomi...@samsung.com --- include/linux/usb/ch9.h |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/linux/usb/ch9.h b/include/linux/usb/ch9.h index 61b2905..76ff771 100644 --- a/include/linux/usb/ch9.h +++ b/include/linux/usb/ch9.h @@ -88,6 +88,7 @@ #define USB_REQ_GET_INTERFACE 0x0A #define USB_REQ_SET_INTERFACE 0x0B #define USB_REQ_SYNCH_FRAME0x0C +#define USB_REQ_SET_SEL0x30 #define USB_REQ_SET_ENCRYPTION 0x0D/* Wireless USB */ #define USB_REQ_GET_ENCRYPTION 0x0E Why did you insert this out of order? greg please note my email address change as well k-h 'Set SEL' is a standard device request according to USB3.0 spec. Wireless USB requests are not mentioned in USB3.0 spec (and moreover are not in ch9 of it). So I put the definition to an appropriate group in my opinion. If you insist I will move the definition below Wireless USB group with a space between. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] USB: EXYNOS USB3.0 device controller driver
Hi, (please don't top-post) On Tue, Feb 07, 2012 at 03:31:31PM +0900, Anton Tikhomirov wrote: I'm sorry for the misunderstanding from our side. We will implement the glue layer for our Exynos SoC and reuse the dwc3 driver. no problem. You could have saved a few months worth of work ;-) -- balbi signature.asc Description: Digital signature
Re: [PATCH 1/4] [SCSI] ufshcd: UFS Host controller driver
Hi,
On Thu, Feb 02, 2012 at 10:27:26AM +0530, Vinayak Holikatti wrote:
+/**
+ * ufshcd_uic_cc_handler - handle UIC command completion
+ * @work: pointer to a work queue structure
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static void ufshcd_uic_cc_handler (struct work_struct *work)
+{
+ struct ufs_hba *hba;
+
+ hba = container_of(work, struct ufs_hba, uic_workq);
+
+ if ((UIC_CMD_DME_LINK_STARTUP == hba-active_uic_cmd.command)
this is so annoying. Please invert all these constructs:
if ((hcd-active_uic_cmd.command == UIC_CMD_DME_LINK_STARTUP)
and so on.
+ !(ufshcd_get_uic_cmd_result(hba))) {
+
+ if (ufshcd_make_hba_operational(hba))
+ dev_err(hba-pdev-dev,
+ cc: hba not operational state\n);
+ return;
+ }
+}
+
+/**
+ * ufshcd_sl_intr - Interrupt service routine
+ * @hba: per adapter instance
+ * @intr_status: contains interrupts generated by the controller
+ */
+static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
+{
+ if (intr_status UIC_COMMAND_COMPL)
+ schedule_work(hba-uic_workq);
+}
+
+/**
+ * ufshcd_intr - Main interrupt service routine
+ * @irq: irq number
+ * @__hba: pointer to adapter instance
+ *
+ * Returns IRQ_HANDLED - If interrupt is valid
+ * IRQ_NONE - If invalid interrupt
+ */
+static irqreturn_t ufshcd_intr(int irq, void *__hba)
+{
+ unsigned long flags;
+ u32 intr_status;
+ irqreturn_t retval = IRQ_NONE;
+ struct ufs_hba *hba = __hba;
+
+ spin_lock_irqsave(hba-host-host_lock, flags);
+ intr_status = readl(UFSHCD_MMIO_BASE + REG_INTERRUPT_STATUS);
+
+ if (intr_status) {
+ ufshcd_sl_intr(hba, intr_status);
+
+ /* If UFSHCI 1.0 then clear interrupt status register */
+ if (UFSHCI_VERSION_10 == hba-ufs_version)
+ writel(intr_status,
+(UFSHCD_MMIO_BASE + REG_INTERRUPT_STATUS));
+ retval = IRQ_HANDLED;
+ }
+ spin_unlock_irqrestore(hba-host-host_lock, flags);
+ return retval;
+}
+
+static struct scsi_host_template ufshcd_driver_template = {
+ .module = THIS_MODULE,
+ .name = UFSHCD,
+ .proc_name = UFSHCD,
+ .this_id= -1,
+};
+
+/**
+ * ufshcd_shutdown - main funciton to put the controller in reset state
+ * @pdev: pointer to PCI device handle
+ */
+static void ufshcd_shutdown(struct pci_dev *pdev)
+{
+ ufshcd_hba_stop((struct ufs_hba *)pci_get_drvdata(pdev));
+}
+
+#ifdef CONFIG_PM
+/**
+ * ufshcd_suspend - suspend power management function
+ * @pdev: pointer to PCI device handle
+ * @state: power state
+ *
+ * Returns -ENOSYS
+ */
+static int ufshcd_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ return -ENOSYS;
+}
+
+/**
+ * ufshcd_resume - resume power management function
+ * @pdev: pointer to PCI device handle
+ *
+ * Returns -ENOSYS
+ */
+static int ufshcd_resume(struct pci_dev *pdev)
+{
+ return -ENOSYS;
+}
+#endif /* CONFIG_PM */
+
+/**
+ * ufshcd_hba_free - free allocated memory for
+ * host memory space data structures
+ * @hba: per adapter instance
+ */
+static void ufshcd_hba_free(struct ufs_hba *hba)
+{
+ iounmap(UFSHCD_MMIO_BASE);
+ ufshcd_free_hba_memory(hba);
+ pci_release_regions(hba-pdev);
+}
+
+/**
+ * ufshcd_remove - deallocate PCI/SCSI host and host memory space
+ * data structure memory
+ * @pdev - pointer to PCI handle
+ */
+static void ufshcd_remove(struct pci_dev *pdev)
+{
+ struct ufs_hba *hba = pci_get_drvdata(pdev);
+
+ /* disable interrupts */
+ ufshcd_int_config(hba, UFSHCD_INT_DISABLE);
+ free_irq(pdev-irq, hba);
+
+ ufshcd_hba_stop(hba);
+ ufshcd_hba_free(hba);
+
+ scsi_remove_host(hba-host);
+ scsi_host_put(hba-host);
+ pci_set_drvdata(pdev, NULL);
+ pci_clear_master(pdev);
+ pci_disable_device(pdev);
+}
+
+/**
+ * ufshcd_set_dma_mask - Set dma addressing
+ * @pdev: PCI device struct
+ *
+ * Returns 0 for success, non-zero for failure
+ */
+static int ufshcd_set_dma_mask(struct pci_dev *pdev)
+{
+ int err;
+
+ do {
+ err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
+ if (!err) {
+ err = pci_set_consistent_dma_mask(pdev,
+ DMA_BIT_MASK(64));
+ break;
+ }
+ err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
+ if (!err)
+ err = pci_set_consistent_dma_mask(pdev,
+ DMA_BIT_MASK(32));
+ } while (0);
+
+ return err;
+}
+
+/**
+ * ufshcd_probe - probe routine of the driver
+ * @pdev: pointer to
