[PATCH v2] ARM: EXYNOS: Add touchscreen support to SMDK4X12

[Sachin Kamat]

Pixcir touchscreen device support is added to SMDK4X12 boards.

Signed-off-by: Sachin Kamat 
---
This patch is based on Kukjin Kim's latest for-next branch.

Changes since v1:
Incorporated Kukjin's review comments
-reduced mdelay
-removed a unnecessary gpio
---
 arch/arm/mach-exynos/mach-smdk4x12.c |   31 ++-
 1 files changed, 30 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c 
b/arch/arm/mach-exynos/mach-smdk4x12.c
index 2623f3b..b3207ea 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -9,9 +9,11 @@
  * published by the Free Software Foundation.
 */
 
+#include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -207,8 +209,33 @@ static struct i2c_board_info smdk4x12_i2c_devs3[] 
__initdata = {
/* nothing here yet */
 };
 
+static void smdk4x12_ts_gpio_setup(void)
+{
+   int gpio_reset = EXYNOS4_GPM3(4);
+
+   gpio_request_one(gpio_reset, GPIOF_OUT_INIT_LOW, "TOUCH RESET");
+   mdelay(2);
+   gpio_direction_output(gpio_reset, 1);
+   mdelay(30);
+}
+
+static int smdk4x12_ts_get_value(void)
+{
+   return 1;
+}
+
+static struct pixcir_ts_platform_data smdk4x12_ts_data = {
+   .attb_read_val = smdk4x12_ts_get_value,
+   .x_max = 480,
+   .y_max = 800,
+};
+
 static struct i2c_board_info smdk4x12_i2c_devs7[] __initdata = {
-   /* nothing here yet */
+   {
+   I2C_BOARD_INFO("pixcir_ts", 0x5C),
+   .irq= IRQ_EINT(22),
+   .platform_data  = &smdk4x12_ts_data,
+   }
 };
 
 static struct samsung_bl_gpio_info smdk4x12_bl_gpio_info = {
@@ -336,6 +363,8 @@ static void __init smdk4x12_machine_init(void)
 
s5p_fimd0_set_platdata(&smdk4x12_lcd_pdata);
 
+   smdk4x12_ts_gpio_setup();
+
platform_add_devices(smdk4x12_devices, ARRAY_SIZE(smdk4x12_devices));
 }
 
-- 
1.7.4.1

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Re: [PATCH 1/1] ARM: EXYNOS: Add touchscreen support to SMDK4X12

[Sachin Kamat]

On 13/07/2012, Kukjin Kim  wrote:
> Sachin Kamat wrote:
>>
>> Pixcir touchscreen device support is added to SMDK4X12 boards.
>>
>> Signed-off-by: Sachin Kamat 
>> ---
>>  arch/arm/mach-exynos/mach-smdk4x12.c |   32
>> +++-
>>  1 files changed, 31 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-
>> exynos/mach-smdk4x12.c
>> index fe772d8..0af6088 100644
>> --- a/arch/arm/mach-exynos/mach-smdk4x12.c
>> +++ b/arch/arm/mach-exynos/mach-smdk4x12.c
>> @@ -9,10 +9,12 @@
>>   * published by the Free Software Foundation.
>>  */
>>
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>> @@ -203,8 +205,34 @@ static struct i2c_board_info smdk4x12_i2c_devs3[]
>> __initdata = {
>>  /* nothing here yet */
>>  };
>>
>> +static void smdk4x12_ts_gpio_setup(void)
>> +{
>> +int gpio_reset = EXYNOS4_GPM3(4);
>> +
>> +gpio_request_one(gpio_reset, GPIOF_OUT_INIT_LOW, "TOUCH RESET");
>> +mdelay(20);
>> +gpio_direction_output(gpio_reset, 1);
>
> Do you want to set the gpio_reset value from 0 to 1 with 20m delays? Why?
Yes right. I found lower value (2m) should be fine.

>
>> +mdelay(30);
>> +s3c_gpio_setpull(EXYNOS4_GPX2(6), S3C_GPIO_PULL_NONE);
>
> Hmm...don't we need gpio_reqeust()? and what's the gpx2(6)?

This gpio is not needed. I will remove this and send the updated patch.

>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim , Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
>


-- 
With warm regards,
Sachin
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[PATCH RESEND v2 2/2] ARM: EXYNOS: Add gscaler device from DT

[Shaik Ameer Basha]

This patch adds,
- 4 Gscaler devices to the DT device list
- Gscaler specific entries to the machine file
- binding documentation for Gscaler entries

Signed-off-by: Abhilash Kesavan 
Signed-off-by: Leela Krishna Amudala 
Signed-off-by: Shaik Ameer Basha 
---
 .../devicetree/bindings/media/exynos5-gsc.txt  |   16 ++
 arch/arm/boot/dts/exynos5250.dtsi  |   31 
 arch/arm/mach-exynos/include/mach/map.h|3 ++
 arch/arm/mach-exynos/mach-exynos5-dt.c |8 +
 4 files changed, 58 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/exynos5-gsc.txt

diff --git a/Documentation/devicetree/bindings/media/exynos5-gsc.txt 
b/Documentation/devicetree/bindings/media/exynos5-gsc.txt
new file mode 100644
index 000..f743c60
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/exynos5-gsc.txt
@@ -0,0 +1,16 @@
+* Samsung Exynos5 Gscaler device
+
+Gscaler is used for scaling and color space conversion on EXYNOS5 SoCs.
+
+Required properties:
+- compatible: should be "samsung,exynos-gsc"
+- reg: should contian Gsaler physical address location and length.
+- interrupts: should contain Gscaler interrupt number
+
+Example:
+
+gsc_0:  gsc@0x13e0 {
+   compatible = "samsung,exynos-gsc";
+   reg = <0x13e0 0x1000>;
+   interrupts = <0 85 0>;
+};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 4272b29..b945c00 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -23,6 +23,13 @@
compatible = "samsung,exynos5250";
interrupt-parent = <&gic>;
 
+   aliases {
+   gsc0 = &gsc_0;
+   gsc1 = &gsc_1;
+   gsc2 = &gsc_2;
+   gsc3 = &gsc_3;
+   };
+
gic:interrupt-controller@10481000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
@@ -424,4 +431,28 @@
#gpio-cells = <4>;
};
};
+
+   gsc_0:  gsc@0x13e0 {
+   compatible = "samsung,exynos-gsc";
+   reg = <0x13e0 0x1000>;
+   interrupts = <0 85 0>;
+   };
+
+   gsc_1:  gsc@0x13e1 {
+   compatible = "samsung,exynos-gsc";
+   reg = <0x13e1 0x1000>;
+   interrupts = <0 86 0>;
+   };
+
+   gsc_2:  gsc@0x13e2 {
+   compatible = "samsung,exynos-gsc";
+   reg = <0x13e2 0x1000>;
+   interrupts = <0 87 0>;
+   };
+
+   gsc_3:  gsc@0x13e3 {
+   compatible = "samsung,exynos-gsc";
+   reg = <0x13e3 0x1000>;
+   interrupts = <0 88 0>;
+   };
 };
diff --git a/arch/arm/mach-exynos/include/mach/map.h 
b/arch/arm/mach-exynos/include/mach/map.h
index ca4aa89..e68d249 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -121,6 +121,9 @@
 #define EXYNOS4_PA_SYSMMU_MFC_L0x1362
 #define EXYNOS4_PA_SYSMMU_MFC_R0x1363
 
+/* x = 0...3 */
+#define EXYNOS5_PA_GSC(x)  (0x13e0 + ((x) * 0x1))
+
 #define EXYNOS5_PA_SYSMMU_MDMA10x10A4
 #define EXYNOS5_PA_SYSMMU_SSS  0x10A5
 #define EXYNOS5_PA_SYSMMU_2D   0x10A6
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c 
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 7b1e11a..9eb83b6 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -50,6 +50,14 @@ static const struct of_dev_auxdata 
exynos5250_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
+   OF_DEV_AUXDATA("samsung,exynos-gsc", EXYNOS5_PA_GSC(0),
+   "exynos-gsc.0", NULL),
+   OF_DEV_AUXDATA("samsung,exynos-gsc", EXYNOS5_PA_GSC(1),
+   "exynos-gsc.1", NULL),
+   OF_DEV_AUXDATA("samsung,exynos-gsc", EXYNOS5_PA_GSC(2),
+   "exynos-gsc.2", NULL),
+   OF_DEV_AUXDATA("samsung,exynos-gsc", EXYNOS5_PA_GSC(3),
+   "exynos-gsc.3", NULL),
{},
 };
 
-- 
1.7.0.4

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[PATCH RESEND v2 1/2] ARM: EXYNOS: Add clock support for Gscaler

[Shaik Ameer Basha]

Add required clock support for Gscaler for exynos5

Signed-off-by: Abhilash Kesavan 
Signed-off-by: Leela Krishna Amudala 
Signed-off-by: Prathyush K 
Signed-off-by: Shaik Ameer Basha 
---
 arch/arm/mach-exynos/clock-exynos5.c |   79 ++
 1 files changed, 79 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/clock-exynos5.c 
b/arch/arm/mach-exynos/clock-exynos5.c
index fefa336..c8293a3 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -741,6 +741,26 @@ static struct clk exynos5_init_clocks_off[] = {
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit= (1 << 14),
}, {
+   .name   = "gscl",
+   .devname= "exynos-gsc.0",
+   .enable = exynos5_clk_ip_gscl_ctrl,
+   .ctrlbit= (1 << 0),
+   }, {
+   .name   = "gscl",
+   .devname= "exynos-gsc.1",
+   .enable = exynos5_clk_ip_gscl_ctrl,
+   .ctrlbit= (1 << 1),
+   }, {
+   .name   = "gscl",
+   .devname= "exynos-gsc.2",
+   .enable = exynos5_clk_ip_gscl_ctrl,
+   .ctrlbit= (1 << 2),
+   }, {
+   .name   = "gscl",
+   .devname= "exynos-gsc.3",
+   .enable = exynos5_clk_ip_gscl_ctrl,
+   .ctrlbit= (1 << 3),
+   }, {
.name   = SYSMMU_CLOCK_NAME,
.devname= SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
.enable = &exynos5_clk_ip_mfc_ctrl,
@@ -1116,6 +1136,61 @@ static struct clksrc_clk exynos5_clksrcs[] = {
},
 };
 
+/* For ACLK_300_gscl_mid */
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
+   .clk= {
+   .name   = "mout_aclk_300_gscl_mid",
+   },
+   .sources = &exynos5_clkset_aclk,
+   .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
+};
+
+/* For ACLK_300_gscl */
+struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
+   [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
+   [1] = &exynos5_clk_sclk_vpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
+   .sources= exynos5_clkset_aclk_300_gscl_list,
+   .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
+   .clk= {
+   .name   = "mout_aclk_300_gscl",
+   },
+   .sources = &exynos5_clkset_aclk_300_gscl,
+   .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_aclk_300_gscl = {
+   .clk= {
+   .name   = "dout_aclk_300_gscl",
+   .parent = &exynos5_clk_mout_aclk_300_gscl.clk,
+   },
+   .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 12, .size = 3 },
+};
+
+/* Possible clock sources for aclk_300_gscl_sub Mux */
+static struct clk *clk_src_gscl_300_list[] = {
+   [0] = &clk_ext_xtal_mux,
+   [1] = &exynos5_clk_dout_aclk_300_gscl.clk,
+};
+
+static struct clksrc_sources clk_src_gscl_300 = {
+   .sources= clk_src_gscl_300_list,
+   .nr_sources = ARRAY_SIZE(clk_src_gscl_300_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
+   .clk= {
+   .name   = "aclk_300_gscl",
+   },
+   .sources = &clk_src_gscl_300,
+   .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
+};
+
 /* Clock initialization code */
 static struct clksrc_clk *exynos5_sysclks[] = {
&exynos5_clk_mout_apll,
@@ -1139,6 +1214,10 @@ static struct clksrc_clk *exynos5_sysclks[] = {
&exynos5_clk_aclk_266,
&exynos5_clk_aclk_200,
&exynos5_clk_aclk_166,
+   &exynos5_clk_aclk_300_gscl,
+   &exynos5_clk_dout_aclk_300_gscl,
+   &exynos5_clk_mout_aclk_300_gscl,
+   &exynos5_clk_mout_aclk_300_gscl_mid,
&exynos5_clk_aclk_66_pre,
&exynos5_clk_aclk_66,
&exynos5_clk_dout_mmc0,
-- 
1.7.0.4

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[PATCH RESEND v2 0/2] Add device tree and clock support for Gscaler.

[Shaik Ameer Basha]

This patch series adds clock support for Gscaler and device node
 entries for Gscaler on exynos5.

This patch is based on Kukjin Kim's (linux-samsung) for-next branch.
https://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git

changes since v1:
- Addressed review comments from Sylwester Nawrocki
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg11177.html
- Addressed review comments from Sachin Kamat
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg11176.html
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg11178.html

Resending this patch for posting to devicetree-disc...@lists.ozlabs.org

Shaik Ameer Basha (2):
  ARM: EXYNOS: Add clock support for Gscaler
  ARM: EXYNOS: Add gscaler device from DT

 .../devicetree/bindings/media/exynos5-gsc.txt  |   16 
 arch/arm/boot/dts/exynos5250.dtsi  |   31 
 arch/arm/mach-exynos/clock-exynos5.c   |   79 
 arch/arm/mach-exynos/include/mach/map.h|3 +
 arch/arm/mach-exynos/mach-exynos5-dt.c |8 ++
 5 files changed, 137 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/exynos5-gsc.txt

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[PATCH v2 2/2] ARM: EXYNOS: Add G2D related clock entries for SMDK4X12

[Sachin Kamat]

Adds G2D related clock entries for SMDK4X12 boards.

Signed-off-by: Sachin Kamat 
---
 arch/arm/mach-exynos/clock-exynos4212.c |   41 +-
 1 files changed, 39 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-exynos/clock-exynos4212.c 
b/arch/arm/mach-exynos/clock-exynos4212.c
index da397d2..8fba0b5 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -68,12 +68,45 @@ static struct clksrc_clk clk_mout_mpll_user = {
.reg_src= { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
 };
 
+static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
+   .clk= {
+   .name   = "mout_g2d0",
+   },
+   .sources = &exynos4_clkset_mout_g2d0,
+   .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
+};
+
+static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
+   .clk= {
+   .name   = "mout_g2d1",
+   },
+   .sources = &exynos4_clkset_mout_g2d1,
+   .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
+};
+
+static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
+   [0] = &exynos4x12_clk_mout_g2d0.clk,
+   [1] = &exynos4x12_clk_mout_g2d1.clk,
+};
+
+static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
+   .sources= exynos4x12_clkset_mout_g2d_list,
+   .nr_sources = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
+};
+
 static struct clksrc_clk *sysclks[] = {
&clk_mout_mpll_user,
 };
 
 static struct clksrc_clk clksrcs[] = {
-   /* nothing here yet */
+   {
+   .clk= {
+   .name   = "sclk_fimg2d",
+   },
+   .sources = &exynos4x12_clkset_mout_g2d,
+   .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 
},
+   .reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 
},
+   },
 };
 
 static struct clk init_clocks_off[] = {
@@ -102,7 +135,11 @@ static struct clk init_clocks_off[] = {
.devname= "exynos-fimc-lite.1",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit= (1 << 3),
-   }
+   }, {
+   .name   = "fimg2d",
+   .enable = exynos4_clk_ip_dmc_ctrl,
+   .ctrlbit= (1 << 23),
+   },
 };
 
 #ifdef CONFIG_PM_SLEEP
-- 
1.7.4.1

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[PATCH v2 1/2] ARM: EXYNOS: Move G2D clock entries to clock-exynos4210.c file

[Sachin Kamat]

G2D clock registers are different in Exynos4210 and Exynos4X12 SoCs.
Hence moving the SoC specific G2D clock entries from common clock file
(clock-exynos4.c) to Exynos4210 specific clock file (clock-exynos4210.c).

Signed-off-by: Sachin Kamat 
---
 arch/arm/mach-exynos/clock-exynos4.c|   41 +-
 arch/arm/mach-exynos/clock-exynos4.h|3 ++
 arch/arm/mach-exynos/clock-exynos4210.c |   37 
 3 files changed, 42 insertions(+), 39 deletions(-)

diff --git a/arch/arm/mach-exynos/clock-exynos4.c 
b/arch/arm/mach-exynos/clock-exynos4.c
index bcb7db4..18d59d3 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -620,10 +620,6 @@ static struct clk exynos4_init_clocks_off[] = {
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit= (1 << 27),
}, {
-   .name   = "fimg2d",
-   .enable = exynos4_clk_ip_image_ctrl,
-   .ctrlbit= (1 << 0),
-   }, {
.name   = "mfc",
.devname= "s5p-mfc",
.enable = exynos4_clk_ip_mfc_ctrl,
@@ -819,47 +815,21 @@ static struct clk *exynos4_clkset_mout_g2d0_list[] = {
[1] = &exynos4_clk_sclk_apll.clk,
 };
 
-static struct clksrc_sources exynos4_clkset_mout_g2d0 = {
+struct clksrc_sources exynos4_clkset_mout_g2d0 = {
.sources= exynos4_clkset_mout_g2d0_list,
.nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
 };
 
-static struct clksrc_clk exynos4_clk_mout_g2d0 = {
-   .clk= {
-   .name   = "mout_g2d0",
-   },
-   .sources = &exynos4_clkset_mout_g2d0,
-   .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
-};
-
 static struct clk *exynos4_clkset_mout_g2d1_list[] = {
[0] = &exynos4_clk_mout_epll.clk,
[1] = &exynos4_clk_sclk_vpll.clk,
 };
 
-static struct clksrc_sources exynos4_clkset_mout_g2d1 = {
+struct clksrc_sources exynos4_clkset_mout_g2d1 = {
.sources= exynos4_clkset_mout_g2d1_list,
.nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
 };
 
-static struct clksrc_clk exynos4_clk_mout_g2d1 = {
-   .clk= {
-   .name   = "mout_g2d1",
-   },
-   .sources = &exynos4_clkset_mout_g2d1,
-   .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
-};
-
-static struct clk *exynos4_clkset_mout_g2d_list[] = {
-   [0] = &exynos4_clk_mout_g2d0.clk,
-   [1] = &exynos4_clk_mout_g2d1.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_mout_g2d = {
-   .sources= exynos4_clkset_mout_g2d_list,
-   .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d_list),
-};
-
 static struct clk *exynos4_clkset_mout_mfc0_list[] = {
[0] = &exynos4_clk_mout_mpll.clk,
[1] = &exynos4_clk_sclk_apll.clk,
@@ -1126,13 +1096,6 @@ static struct clksrc_clk exynos4_clksrcs[] = {
.reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 
},
}, {
.clk= {
-   .name   = "sclk_fimg2d",
-   },
-   .sources = &exynos4_clkset_mout_g2d,
-   .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 
},
-   .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 
},
-   }, {
-   .clk= {
.name   = "sclk_mfc",
.devname= "s5p-mfc",
},
diff --git a/arch/arm/mach-exynos/clock-exynos4.h 
b/arch/arm/mach-exynos/clock-exynos4.h
index 28a1197..bd12d5f 100644
--- a/arch/arm/mach-exynos/clock-exynos4.h
+++ b/arch/arm/mach-exynos/clock-exynos4.h
@@ -23,6 +23,9 @@ extern struct clksrc_sources exynos4_clkset_group;
 extern struct clk *exynos4_clkset_aclk_top_list[];
 extern struct clk *exynos4_clkset_group_list[];
 
+extern struct clksrc_sources exynos4_clkset_mout_g2d0;
+extern struct clksrc_sources exynos4_clkset_mout_g2d1;
+
 extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
 extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
 extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c 
b/arch/arm/mach-exynos/clock-exynos4210.c
index b8689ff..fed4c26 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -48,6 +48,32 @@ static struct clksrc_clk *sysclks[] = {
/* nothing here yet */
 };
 
+static struct clksrc_clk exynos4210_clk_mout_g2d0 = {
+   .clk= {
+   .name   = "mout_g2d0",
+   },
+   .sources = &exynos4_clkset_mout_g2d0,
+   .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk exynos4210_clk_mout_g2d1 = {
+   .clk= {
+   .name   = "mout_g

[PATCH v2 0/2] ARM: EXYNOS: G2D clock support to Exynos4

[Sachin Kamat]

This patch series moves the SoC specific G2D clock entries from common clock-
file (clock-exynos4.c) to Exynos4210 specific clock file (clock-exynos4210.c)
since G2D clock registers are different in Exynos4210 and Exynos4X12 SoCs
and adds support for Exynos4x12 G2D clock.

Changes since v1:
Incorporated Kukjin's comments to use exynos4210/4x12 in structure names
instead of exynos4 for better clarity.

This series is based on Kukjin Kim's latest next/devel-samsung branch.

Sachin Kamat (2):
  ARM: EXYNOS: Move G2D clock entries to clock-exynos4210.c file
  ARM: EXYNOS: Add G2D related clock entries for SMDK4X12

 arch/arm/mach-exynos/clock-exynos4.c|   41 +-
 arch/arm/mach-exynos/clock-exynos4.h|3 ++
 arch/arm/mach-exynos/clock-exynos4210.c |   37 
 arch/arm/mach-exynos/clock-exynos4212.c |   41 +-
 4 files changed, 81 insertions(+), 41 deletions(-)

-- 
1.7.4.1

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Re: [PATCH v3 5/6] mmc: dw_mmc: add device tree support

[Girish K S]

On 16 July 2012 09:45, Girish K S  wrote:
> On 12 July 2012 18:24, Thomas Abraham  wrote:
>> Add device tree based discovery support.
>>
>> Signed-off-by: Thomas Abraham 
>> ---
>>  .../devicetree/bindings/mmc/synposis-dw-mshc.txt   |  108 +++
>>  drivers/mmc/host/dw_mmc-pltfm.c|   24 +++
>>  drivers/mmc/host/dw_mmc.c  |  201 
>> +++-
>>  drivers/mmc/host/dw_mmc.h  |9 +
>>  include/linux/mmc/dw_mmc.h |2 +
>>  5 files changed, 338 insertions(+), 6 deletions(-)
>>  create mode 100644 
>> Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt 
>> b/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
>> new file mode 100644
>> index 000..3acd6c9
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
>> @@ -0,0 +1,108 @@
>> +* Synopsis Designware Mobile Storage Host Controller
>> +
>> +The Synopsis designware mobile storage host controller is used to interface
>> +a SoC with storage medium such as eMMC or SD/MMC cards.
>> +
>> +Required Properties:
>> +
>> +* compatible: should be one of the following
>> +   - snps,dw-mshc: for controllers compliant with synopsis dw-mshc.
>> +
>> +* reg: physical base address of the dw-mshc controller and size of its 
>> memory
>> +  region.
>> +
>> +* interrupts: interrupt specifier for the controller. The format and value 
>> of
>> +  the interrupt specifier depends on the interrupt parent for the 
>> controller.
>> +
>> +* #address-cells: should be 1.
>> +
>> +* #size-cells: should be 0.
>> +
>> +# Slots: The slot specific information are contained within child-nodes with
>> +  each child-node representing a supported slot. There should be atleast one
>> +  child node representing a card slot. The name of the child node 
>> representing
>> +  the slot is recommended to be slot@n where n is the unique number of the 
>> slot
>> +  connnected to the controller. The following are optional properties which
>> +  can be included in the slot child node.
>> +
>> +   * reg: specifies the physical slot number. The valid values of this
>> + property is 0 to (num-slots -1), where num-slots is the value
>> + specified by the num-slots property.
>> +
>> +   * bus-width: specifies the width of the data bus connected from the
>> + controller to the card slot. The value should be 1, 4 or 8. In case
>> + this property is not specified, a default value of 1 is assumed for
>> + this property.
>> +
>> +   * cd-gpios: specifies the card detect gpio line. The format of the
>> + gpio specifier depends on the gpio controller.
>> +
>> +   * wp-gpios: specifies the write protect gpio line. The format of the
>> + gpio specifier depends on the gpio controller.
>> +
>> +   * gpios: specifies a list of gpios used for command, clock and data
>> + bus. The first gpio is the command line and the second gpio is the
>> + clock line. The rest of the gpios (depending on the bus-width
>> + property) are the data lines in no particular order. The format of
>> + the gpio specifier depends on the gpio controller.
>> +
>> +Optional properties:
>> +
>> +* num-slots: specifies the number of slots supported by the controller.
>> +  The number of physical slots actually used could be equal or less than the
>> +  value specified by num-slots. If this property is not specified, the value
>> +  of num-slot property is assumed to be 1.
>> +
>> +* fifo-depth: The maximum size of the tx/rx fifo's. If this property is not
>> +  specified, the default value of the fifo size is determined from the
>> +  controller registers.
>> +
>> +* card-detect-delay: Delay in milli-seconds before detecting card after card
>> +  insert event. The default value is 0.
>> +
>> +* supports-highspeed: Enables support for high speed cards (upto 50MHz)
>> +
>> +* card-detection-broken: The card detection functionality is not available 
>> on
>> +  any of the slots.
>> +
>> +* no-write-protect: The write protect pad of the controller is not connected
>> +  to the write protect pin on the slot.
>> +
>> +Aliases:
>> +
>> +- All the MSHC controller nodes should be represented in the aliases node 
>> using
>> +  the following format 'mshc{n}' where n is a unique number for the alias.
>> +
>> +
>> +Example:
>> +
>> +  The MSHC controller node can be split into two portions, SoC specific and
>> +  board specific portions as listed below.
>> +
>> +   dwmmc0@1220 {
>> +   compatible = "snps,dw-mshc";
>> +   reg = <0x1220 0x1000>;
>> +   interrupts = <0 75 0>;
>> +   #address-cells = <1>;
>> +   #size-cells = <0>;
>> +   };
>> +
>> +   dwmmc0@1220 {
>> +   num-slots = <1>;
>> +   supports-highspeed;
>>

Re: [PATCH v3 5/6] mmc: dw_mmc: add device tree support

[Chris Ball]

Hi,

On Thu, Jul 12 2012, Thomas Abraham wrote:
> diff --git a/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt 
> b/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
> new file mode 100644
> index 000..3acd6c9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
> @@ -0,0 +1,108 @@
> +* Synopsis Designware Mobile Storage Host Controller
> +
> +The Synopsis designware mobile storage host controller is used to interface
> +a SoC with storage medium such as eMMC or SD/MMC cards.
> +
> +Required Properties:
> +
> +* compatible: should be one of the following
> + - snps,dw-mshc: for controllers compliant with synopsis dw-mshc.
> +
> +* reg: physical base address of the dw-mshc controller and size of its memory
> +  region.
> +
> +* interrupts: interrupt specifier for the controller. The format and value of
> +  the interrupt specifier depends on the interrupt parent for the controller.

Please instead add:

This file documents differences between the core properties described
by mmc.txt and the properties used by the dw_mmc driver.

mmc.txt already describes compatible, reg, interrupts, bus-width,
cd-gpios, and wp-gpios, so you don't need to describe those again.

> + cnt = sizeof(of_quriks) / sizeof(struct dw_mci_of_quirks);
> + for (idx = 0; idx < cnt; idx++)
> + if (of_get_property(np, of_quriks[idx].quirk, NULL))
> + pdata->quirks |= of_quriks[idx].id;

of_quirks, not of_quriks.

Thanks,

- Chris.
-- 
Chris Ball  
One Laptop Per Child
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Re: [PATCH v3 5/6] mmc: dw_mmc: add device tree support

[Girish K S]

On 12 July 2012 18:24, Thomas Abraham  wrote:
> Add device tree based discovery support.
>
> Signed-off-by: Thomas Abraham 
> ---
>  .../devicetree/bindings/mmc/synposis-dw-mshc.txt   |  108 +++
>  drivers/mmc/host/dw_mmc-pltfm.c|   24 +++
>  drivers/mmc/host/dw_mmc.c  |  201 
> +++-
>  drivers/mmc/host/dw_mmc.h  |9 +
>  include/linux/mmc/dw_mmc.h |2 +
>  5 files changed, 338 insertions(+), 6 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
>
> diff --git a/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt 
> b/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
> new file mode 100644
> index 000..3acd6c9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
> @@ -0,0 +1,108 @@
> +* Synopsis Designware Mobile Storage Host Controller
> +
> +The Synopsis designware mobile storage host controller is used to interface
> +a SoC with storage medium such as eMMC or SD/MMC cards.
> +
> +Required Properties:
> +
> +* compatible: should be one of the following
> +   - snps,dw-mshc: for controllers compliant with synopsis dw-mshc.
> +
> +* reg: physical base address of the dw-mshc controller and size of its memory
> +  region.
> +
> +* interrupts: interrupt specifier for the controller. The format and value of
> +  the interrupt specifier depends on the interrupt parent for the controller.
> +
> +* #address-cells: should be 1.
> +
> +* #size-cells: should be 0.
> +
> +# Slots: The slot specific information are contained within child-nodes with
> +  each child-node representing a supported slot. There should be atleast one
> +  child node representing a card slot. The name of the child node 
> representing
> +  the slot is recommended to be slot@n where n is the unique number of the 
> slot
> +  connnected to the controller. The following are optional properties which
> +  can be included in the slot child node.
> +
> +   * reg: specifies the physical slot number. The valid values of this
> + property is 0 to (num-slots -1), where num-slots is the value
> + specified by the num-slots property.
> +
> +   * bus-width: specifies the width of the data bus connected from the
> + controller to the card slot. The value should be 1, 4 or 8. In case
> + this property is not specified, a default value of 1 is assumed for
> + this property.
> +
> +   * cd-gpios: specifies the card detect gpio line. The format of the
> + gpio specifier depends on the gpio controller.
> +
> +   * wp-gpios: specifies the write protect gpio line. The format of the
> + gpio specifier depends on the gpio controller.
> +
> +   * gpios: specifies a list of gpios used for command, clock and data
> + bus. The first gpio is the command line and the second gpio is the
> + clock line. The rest of the gpios (depending on the bus-width
> + property) are the data lines in no particular order. The format of
> + the gpio specifier depends on the gpio controller.
> +
> +Optional properties:
> +
> +* num-slots: specifies the number of slots supported by the controller.
> +  The number of physical slots actually used could be equal or less than the
> +  value specified by num-slots. If this property is not specified, the value
> +  of num-slot property is assumed to be 1.
> +
> +* fifo-depth: The maximum size of the tx/rx fifo's. If this property is not
> +  specified, the default value of the fifo size is determined from the
> +  controller registers.
> +
> +* card-detect-delay: Delay in milli-seconds before detecting card after card
> +  insert event. The default value is 0.
> +
> +* supports-highspeed: Enables support for high speed cards (upto 50MHz)
> +
> +* card-detection-broken: The card detection functionality is not available on
> +  any of the slots.
> +
> +* no-write-protect: The write protect pad of the controller is not connected
> +  to the write protect pin on the slot.
> +
> +Aliases:
> +
> +- All the MSHC controller nodes should be represented in the aliases node 
> using
> +  the following format 'mshc{n}' where n is a unique number for the alias.
> +
> +
> +Example:
> +
> +  The MSHC controller node can be split into two portions, SoC specific and
> +  board specific portions as listed below.
> +
> +   dwmmc0@1220 {
> +   compatible = "snps,dw-mshc";
> +   reg = <0x1220 0x1000>;
> +   interrupts = <0 75 0>;
> +   #address-cells = <1>;
> +   #size-cells = <0>;
> +   };
> +
> +   dwmmc0@1220 {
> +   num-slots = <1>;
> +   supports-highspeed;
> +   card-detection-broken;
> +   no-write-protect;
> +   fifo-depth = <0x80>;
> +   card-detect-delay = <200>;
> +
> + 

RE: [PATCH v5 6/6] spi: s3c64xx: add device tree support

[Kukjin Kim]

Thomas Abraham wrote:
> 
> On 13 July 2012 19:12, Kukjin Kim  wrote:
> > Thomas Abraham wrote:
> >>
> >> On 13 July 2012 16:58, Kukjin Kim  wrote:
> >> > Thomas Abraham wrote:
> >> >>
> >> >> On 13 July 2012 04:08, Kukjin Kim  wrote:
> >> >> > Thomas, the DMACH_DT_PROP is available only on pl330 now. So seems
> >> occur
> >> >> > following build error with s3c6400_defconfig.
> >> >> >
> >> >> > drivers/spi/spi-s3c64xx.c: In function 's3c64xx_spi_get_dmares':
> >> >> > drivers/spi/spi-s3c64xx.c:1098: error: 'DMACH_DT_PROP' undeclared
> >> (first
> >> >> use
> >> >> > in this function)
> >> >> > drivers/spi/spi-s3c64xx.c:1098: error: (Each undeclared identifier
> is
> >> >> > reported only once
> >> >> > drivers/spi/spi-s3c64xx.c:1098: error: for each function it
> appears
> >> in.)
> >> >> > make[3]: *** [drivers/spi/spi-s3c64xx.o] Error 1
> >> >> > make[2]: *** [drivers/spi] Error 2
> >> >> >
> >> >>
> >> >> Dear Mr. Kim,
> >> >>
> >> >> Thanks for considering these patches to be merged via your tree. For
> >> >> the build break you mentioned above, there was a patch submitted
> some
> >> >> time back to handle this. The link to that patch is:
> >> >> http://lists.infradead.org/pipermail/linux-arm-kernel/2012-
> >> >> June/102627.html.
> >> >> Could you please apply this patch also to your tree.
> >> >>
> >> > Sure, it looks good to me, will apply that then this series will be
> >> rebased
> >> > on top of that.
> >>
> >> There are six more patches that enable spi device tree support for
> >> Exynos4 and Exynos5 platforms. Could you consider to apply those
> >> patches as well. The link to those patches is:
> >> http://www.mail-archive.com/linux-samsung-
> >> s...@vger.kernel.org/msg10851.html.
> >>
> > Yeah, I remember, but I think some patches is needed to re-work as per
> > comments...?
> 
> I checked again for any pending comments on v2 version. There are no
> pending comments for the v2 version of this patch series. Thanks.

OK, I checked v2 series you mentioned. Looks OK to me and applied into
next/dt-samsung because it is related in supporting dt.

Note, I applied all of them into same dt branch, the fist one 'fix the
incorrect hierarchy of spi controller bus clock for exynos4' can be sent to
upstream via fixes now though. And I changed the clock name for
exynos4_clk_mdout_spix to 'mdout_spi' for consensus when I applied.

If any problems, please let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim , Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

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