Re: [PATCH 1/2] ARM: Exynos5250: Enabling ehci-s5p driver

Hi all, On Tue, Oct 9, 2012 at 1:57 PM, Jingoo Han wrote: > On Friday, October 05, 2012 7:10 PM Vivek Gautam wrote >> >> Adding EHCI device tree node for Exynos5250 along with >> the device base adress and gpio line for vbus. >> >> Signed-off-by: Vivek Gautam > > It looks good. Also I have test

Re: [PATCH 2/2] ARM: Exynos5250: Enabling ohci-exynos driver

Hi all, On Tue, Oct 9, 2012 at 1:59 PM, Jingoo Han wrote: > On Friday, October 05, 2012 7:10 PM Vivek Gautam wrote >> >> Adding OHCI device tree node for Exynos5250 along with >> the device base address. >> >> Signed-off-by: Vivek Gautam > > It looks good. Also I have tested this patch with Exyn

Re: [PATCH] ARM: EXYNOS5: Remove wrongly placed usb2.0 PHY_CFG definition from PMU_REG

Hi all, On Tue, Oct 9, 2012 at 2:04 PM, Jingoo Han wrote: > On Friday, October 05, 2012 10:27 PM Vivek Gautam wrote >> >> EXYNOS5_USB_CFG macro should actually point to USB20PHY_CFG >> system register (base addr + 0x230). It's wrongly placed in regs-pmu. >> Actual register at offset 0x230 in PMU

Re: [PATCH v2 1/5] clk: samsung: add common clock framework support for Samsung platforms

Hi Thomas, Sylwester, On Wednesday 31 of October 2012 00:10:24 Sylwester Nawrocki wrote: > >>> +/* register a samsung pll type clock */ > >>> +void __init samsung_clk_register_pll(const char *name, const char > >>> **pnames, + struct device_node *np, > >>> +

Re: [PATCH v2 1/5] clk: samsung: add common clock framework support for Samsung platforms

Hi Thomas, On 10/29/2012 11:09 AM, Thomas Abraham wrote: > Hi Sylwester, > > Thanks for your comments. As usual, your comments are very helpful. Thanks. > On 22 October 2012 21:25, Sylwester Nawrocki wrote: >> Hi Thomas, >> >> On 10/07/2012 07:10 PM, Thomas Abraham wrote: >>> All Samsung platfo

Re: [PATCH v2 1/5] clk: samsung: add common clock framework support for Samsung platforms

Hi Thomas, Quoting Thomas Abraham (2012-10-07 10:10:51) > +/* determine the output clock speed of the pll */ > +static unsigned long samsung_pll_clock_recalc_rate(struct clk_hw *hw, > + unsigned long parent_rate) > +{ > + struct samsung_pll_clock *clk_pll = to_c

[PATCH v2 6/6] DRIVERS: ATA: SATA PHY controller driver

This patch adds a platform driver and I2C client driver for SATA PHY controller Signed-off-by: Vasanth Ananthan --- arch/arm/mach-exynos/include/mach/regs-sata.h | 29 +++ drivers/ata/Makefile |2 +- drivers/ata/sata_exynos_phy.c | 300

[PATCH v2 5/6] DRIVERS: ATA: SATA controller driver

This patch adds a platform driver for SATA controller. Signed-off-by: Vasanth Ananthan --- arch/arm/mach-exynos/include/mach/regs-pmu.h |3 + drivers/ata/Kconfig | 12 ++ drivers/ata/Makefile |1 + drivers/ata/sata_exynos.c

[PATCH v2 4/6] DRIVERS:I2C: I2C driver polling mode support

This patch adds polling mode support for i2c s3c-2410 driver. The I2C_SATAPHY controller lacks an interrupt line but the s3c-2410 driver is interrupt driven. Hence this support is required for functioning of the I2C_SATAPHY controller. Signed-off-by: Vasanth Ananthan --- drivers/i2c/busses/i2c-s

[PATCH v2 3/6] DRIVERS: ATA: SATA PHY utility framework

This patch adds SATA PHY utility framework APIs. The framework acts as an interface between the SATA device and the PHY device. The SATA PHY device registers itself with the framework through the APIs provided and the SATA device finds and requests for an appropriate PHY device. Signed-off-by: Vas

[PATCH v2 2/6] ARM: EXYNOS5: DT Support for SATA and SATA PHY

This patch adds Device Nodes for SATA and SATA PHY device. Signed-off-by: Vasanth Ananthan --- .../devicetree/bindings/ata/exynos-sata-phy.txt| 14 ++ .../devicetree/bindings/ata/exynos-sata.txt| 17 + arch/arm/boot/dts/exynos5250-smdk5250.dts

[PATCH v2 1/6] ARM: EXYNOS5: Clock settings for SATA and SATA PHY

This patch adds neccessary clock entries for SATA, SATA PHY and I2C_SATAPHY Signed-off-by: Vasanth Ananthan --- arch/arm/mach-exynos/clock-exynos5.c | 21 ++--- 1 files changed, 18 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach

[PATCH v2 0/6] Adding support for SATA in EXYNO5

The following set of patches provides drivers for SATA and SATA PHY controller and also an interface for the two entity to interact. Vasanth Ananthan (6): ARM: EXYNOS5: Clock settings for SATA and SATA PHY ARM: EXYNOS5: DT Support for SATA and SATA PHY DRIVERS: ATA: SATA PHY utility framewor

Re: [PATCH 4/4] DMA: PL330: add device tree property for DMA_MEMCPY capability

Hi, On Monday 29 October 2012 22:45:48 Jassi Brar wrote: > On Mon, Oct 29, 2012 at 10:59 AM, Bartlomiej Zolnierkiewicz > wrote: > > * Add device tree (DT) property ("pl330,dma-memcpy") for DMA_MEMCPY > > capability and instead of setting this capability unconditionally > > in pl330_probe() d

Re: [PATCH 3/4] pinctrl: samsung: Add support for Exynos4x12

On Mon, Oct 29, 2012 at 12:27 PM, Kukjin Kim wrote: > On 10/29/12 19:28, Tomasz Figa wrote: >> On Monday 29 of October 2012 09:30:26 Kyungmin Park wrote: >> Since this depends on the patch adding Exynos4x12 dts files >> ([PATCH] ARM: dts: exynos4: Add support for Exynos4x12 SoCs), >> which will

Re: [PATCH 2/4] ARM: EXYNOS: PL330 MDMA1 fix for revision 0 of Exynos4210 SOC

Hi, On Monday 29 October 2012 18:24:06 Kukjin Kim wrote: > On 10/29/12 10:59, Bartlomiej Zolnierkiewicz wrote: > > Commit 8214513 ("ARM: EXYNOS: fix address for EXYNOS4 MDMA1") > > changed EXYNOS specific setup of PL330 DMA engine to use 'non-secure' > > mdma1 address instead of 'secure' one (fro

[PATCH] ARM: Exynos: move interrupt combiner controller driver to drivers/irqchip

The irqchip support for interrupt combiner controller is moved into drivers/irqchip directory from arch/arm/mach-exynos/common.c file. While at it, the use of soc_is_exynos4/5() macro in the combiner controller driver (used to determine the number of combiners) is removed. Instead, a new parameter