Re: [PATCH-Resend] thermal: Exynos: Add missing dependency
On 15 November 2012 12:34, Zhang Rui wrote: > On Thu, 2012-11-15 at 12:31 +0530, Amit Kachhap wrote: >> On 15 November 2012 12:09, Sachin Kamat wrote: >> > CPU_FREQ_TABLE depends on CPU_FREQ. Selecting CPU_FREQ_TABLE without >> > checking >> > for dependencies gives the following compilation warnings: >> > warning: (ARCH_TEGRA_2x_SOC && ARCH_TEGRA_3x_SOC && UX500_SOC_DB8500 && >> > CPU_THERMAL && EXYNOS_THERMAL) selects CPU_FREQ_TABLE which has unmet >> > direct dependencies (ARCH_HAS_CPUFREQ && CPU_FREQ) >> > >> > Cc: Amit Daniel Kachhap >> > Signed-off-by: Sachin Kamat >> > --- >> > drivers/thermal/Kconfig |3 +-- >> > 1 files changed, 1 insertions(+), 2 deletions(-) >> > >> > diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig >> > index 266c15e..6124c4b 100644 >> > --- a/drivers/thermal/Kconfig >> > +++ b/drivers/thermal/Kconfig >> > @@ -50,8 +50,7 @@ config RCAR_THERMAL >> > >> > config EXYNOS_THERMAL >> > tristate "Temperature sensor on Samsung EXYNOS" >> > - depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && THERMAL >> > - select CPU_FREQ_TABLE >> Hi Sachin/Rui, >> >> "select CPU_FREQ_TABLE" should be there even if CONFIG_CPU_FREQ is >> enabled. Only some governors enable it. > > But CPU_THERMAL will select it, right? Ohh yes correct. Thanks > >> See drivers/cpufreq/Kconfig >> Also "depends THERMAL" should be there otherwise menuconfig >> parent/child relationship is broken. >> > this should be solved by my patch 1/2. :) > > thanks, > rui > >> Thanks, >> Amit Daniel >> >> > + depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && CPU_THERMAL >> > help >> > If you say yes here you get support for TMU (Thermal Managment >> > Unit) on SAMSUNG EXYNOS series of SoC. >> > -- >> > 1.7.4.1 >> > > > -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH-Resend] thermal: Exynos: Add missing dependency
On Thu, 2012-11-15 at 12:31 +0530, Amit Kachhap wrote: > On 15 November 2012 12:09, Sachin Kamat wrote: > > CPU_FREQ_TABLE depends on CPU_FREQ. Selecting CPU_FREQ_TABLE without > > checking > > for dependencies gives the following compilation warnings: > > warning: (ARCH_TEGRA_2x_SOC && ARCH_TEGRA_3x_SOC && UX500_SOC_DB8500 && > > CPU_THERMAL && EXYNOS_THERMAL) selects CPU_FREQ_TABLE which has unmet > > direct dependencies (ARCH_HAS_CPUFREQ && CPU_FREQ) > > > > Cc: Amit Daniel Kachhap > > Signed-off-by: Sachin Kamat > > --- > > drivers/thermal/Kconfig |3 +-- > > 1 files changed, 1 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig > > index 266c15e..6124c4b 100644 > > --- a/drivers/thermal/Kconfig > > +++ b/drivers/thermal/Kconfig > > @@ -50,8 +50,7 @@ config RCAR_THERMAL > > > > config EXYNOS_THERMAL > > tristate "Temperature sensor on Samsung EXYNOS" > > - depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && THERMAL > > - select CPU_FREQ_TABLE > Hi Sachin/Rui, > > "select CPU_FREQ_TABLE" should be there even if CONFIG_CPU_FREQ is > enabled. Only some governors enable it. But CPU_THERMAL will select it, right? > See drivers/cpufreq/Kconfig > Also "depends THERMAL" should be there otherwise menuconfig > parent/child relationship is broken. > this should be solved by my patch 1/2. :) thanks, rui > Thanks, > Amit Daniel > > > + depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && CPU_THERMAL > > help > > If you say yes here you get support for TMU (Thermal Managment > > Unit) on SAMSUNG EXYNOS series of SoC. > > -- > > 1.7.4.1 > > -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH-Resend] thermal: Exynos: Add missing dependency
On 15 November 2012 12:09, Sachin Kamat wrote: > CPU_FREQ_TABLE depends on CPU_FREQ. Selecting CPU_FREQ_TABLE without checking > for dependencies gives the following compilation warnings: > warning: (ARCH_TEGRA_2x_SOC && ARCH_TEGRA_3x_SOC && UX500_SOC_DB8500 && > CPU_THERMAL && EXYNOS_THERMAL) selects CPU_FREQ_TABLE which has unmet > direct dependencies (ARCH_HAS_CPUFREQ && CPU_FREQ) > > Cc: Amit Daniel Kachhap > Signed-off-by: Sachin Kamat > --- > drivers/thermal/Kconfig |3 +-- > 1 files changed, 1 insertions(+), 2 deletions(-) > > diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig > index 266c15e..6124c4b 100644 > --- a/drivers/thermal/Kconfig > +++ b/drivers/thermal/Kconfig > @@ -50,8 +50,7 @@ config RCAR_THERMAL > > config EXYNOS_THERMAL > tristate "Temperature sensor on Samsung EXYNOS" > - depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && THERMAL > - select CPU_FREQ_TABLE Hi Sachin/Rui, "select CPU_FREQ_TABLE" should be there even if CONFIG_CPU_FREQ is enabled. Only some governors enable it. See drivers/cpufreq/Kconfig Also "depends THERMAL" should be there otherwise menuconfig parent/child relationship is broken. Thanks, Amit Daniel > + depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && CPU_THERMAL > help > If you say yes here you get support for TMU (Thermal Managment > Unit) on SAMSUNG EXYNOS series of SoC. > -- > 1.7.4.1 > -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 07/11] ARM: Exynos4: allow legacy board support to specify xxti and xusbxti clock speed
On Thursday 15 of November 2012 03:37:29 Thomas Abraham wrote:
> The clock speed of xxti and xusbxti clocks depends on the oscillator
> used on the board to generate these clocks. For non-dt platforms, allow
> the board support for those platforms to set the clock frequency of
> xxti and xusbxti clocks.
>
> Cc: Kukjin Kim
> Signed-off-by: Thomas Abraham
> ---
> arch/arm/mach-exynos/common.c |2 ++
> arch/arm/mach-exynos/common.h |1 +
> arch/arm/mach-exynos/mach-nuri.c |2 ++
> arch/arm/mach-exynos/mach-origen.c |2 ++
> arch/arm/mach-exynos/mach-smdkv310.c |2 ++
> arch/arm/mach-exynos/mach-universal_c210.c |2 ++
> arch/arm/mach-exynos/mct.c |1 +
> 7 files changed, 12 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/common.c
> b/arch/arm/mach-exynos/common.c index 138a41d..64c0012 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -65,6 +65,8 @@ static void exynos5_init_clocks(int xtal);
> static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
> static int exynos_init(void);
>
> +unsigned long xxti_f = 0, xusbxti_f = 0;
> +
> static struct cpu_table cpu_ids[] __initdata = {
> {
> .idcode = EXYNOS4210_CPU_ID,
> diff --git a/arch/arm/mach-exynos/common.h
> b/arch/arm/mach-exynos/common.h index 2cacd48..f947789 100644
> --- a/arch/arm/mach-exynos/common.h
> +++ b/arch/arm/mach-exynos/common.h
> @@ -22,6 +22,7 @@ void exynos4_restart(char mode, const char *cmd);
> void exynos5_restart(char mode, const char *cmd);
> void exynos_init_late(void);
>
> +extern unsigned long xxti_f, xusbxti_f;
> void exynos4_clk_init(void);
> void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
>
> diff --git a/arch/arm/mach-exynos/mach-nuri.c
> b/arch/arm/mach-exynos/mach-nuri.c index 5b5c941..e14332c 100644
> --- a/arch/arm/mach-exynos/mach-nuri.c
> +++ b/arch/arm/mach-exynos/mach-nuri.c
> @@ -1332,6 +1332,8 @@ static void __init nuri_map_io(void)
> {
> exynos_init_io(NULL, 0);
> s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
> + xxti_f = 0;
> + xusbxti_f = 2400;
I don't like setting these variables directly from board code.
If you didn't remove clock initialization call from board code, you could
extend that function to take these two frequencies as arguments?
> }
>
> static void __init nuri_reserve(void)
[snip]
> diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
> index c2e806c..cd061b2 100644
> --- a/arch/arm/mach-exynos/mct.c
> +++ b/arch/arm/mach-exynos/mct.c
> @@ -532,6 +532,7 @@ static void __init exynos4_timer_init(void)
> if (soc_is_exynos4210() || soc_is_exynos4212() ||
> soc_is_exynos4412()) {
> exynos4_clk_init();
> + exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
I don't like registering clocks from unrelated code. IMHO any clock
registration should be done from code in drivers/clk/samsung.
Best regards,
Tomasz Figa
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Re: [PATCH v3 04/11] ARM: Exynos4: Migrate clock support to common clock framework
On Thursday 15 of November 2012 03:37:26 Thomas Abraham wrote:
> Remove Samsung specific clock support in Exynos4 and migrate to use
> common clock framework.
>
> Cc: Kukjin Kim
> Signed-off-by: Thomas Abraham
> ---
> arch/arm/mach-exynos/Kconfig |1 +
> arch/arm/mach-exynos/Makefile |3 -
> arch/arm/mach-exynos/clock-exynos4.c | 1602
> arch/arm/mach-exynos/clock-exynos4.h
> | 35 -
> arch/arm/mach-exynos/clock-exynos4210.c| 188
> arch/arm/mach-exynos/clock-exynos4212.c| 192
> arch/arm/mach-exynos/common.c | 22 +-
> arch/arm/mach-exynos/common.h |3 +
> arch/arm/mach-exynos/mach-armlex4210.c |1 -
> arch/arm/mach-exynos/mach-exynos4-dt.c |1 -
> arch/arm/mach-exynos/mach-nuri.c |1 -
> arch/arm/mach-exynos/mach-origen.c |1 -
> arch/arm/mach-exynos/mach-smdk4x12.c |1 -
> arch/arm/mach-exynos/mach-smdkv310.c |1 -
> arch/arm/mach-exynos/mach-universal_c210.c |1 -
> arch/arm/mach-exynos/mct.c | 19 +
> arch/arm/plat-samsung/Kconfig |4 +-
> 17 files changed, 27 insertions(+), 2049 deletions(-)
> delete mode 100644 arch/arm/mach-exynos/clock-exynos4.c
> delete mode 100644 arch/arm/mach-exynos/clock-exynos4.h
> delete mode 100644 arch/arm/mach-exynos/clock-exynos4210.c
> delete mode 100644 arch/arm/mach-exynos/clock-exynos4212.c
>
[snip]
> diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
> index f7792b8..c2e806c 100644
> --- a/arch/arm/mach-exynos/mct.c
> +++ b/arch/arm/mach-exynos/mct.c
> @@ -31,6 +31,7 @@
> #include
> #include
> #include
> +#include "common.h"
>
> #define EXYNOS4_MCTREG(x)(x)
> #define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
> @@ -517,6 +518,24 @@ static void __init exynos4_timer_init(void)
> struct device_node *np;
> u32 nr_irqs, i;
>
> +#ifdef CONFIG_COMMON_CLK
> + /*
> + * Clock lookup should be functional now since the MCT controller
> driver + * looks up clocks. So the clock initialization is initiated
> here. +*/
> + if (of_have_populated_dt()) {
> + if (of_machine_is_compatible("samsung,exynos4210") ||
> + of_machine_is_compatible("samsung,exynos4212") ||
> + of_machine_is_compatible("samsung,exynos4412"))
> + exynos4_clk_init();
> + } else {
> + if (soc_is_exynos4210() || soc_is_exynos4212() ||
> + soc_is_exynos4412()) {
> + exynos4_clk_init();
> + }
> + }
> +#endif
> +
I don't like the idea of initializing the clocks from timer
initialization. What about some platforms where MCT isn't used? It is also
far from being elegant.
Best regards,
Tomasz Figa
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Re: [PATCH v3 05/11] ARM: dts: add exynos4 clock controller nodes
On Thursday 15 of November 2012 03:37:27 Thomas Abraham wrote:
> Add clock controller nodes for Exynos4210 and Exynos4x12 SoC's.
>
> Cc: Kukjin Kim
> Signed-off-by: Thomas Abraham
> ---
> arch/arm/boot/dts/exynos4210.dtsi |6 ++
> arch/arm/boot/dts/exynos4x12.dtsi |6 ++
> 2 files changed, 12 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos4210.dtsi
> b/arch/arm/boot/dts/exynos4210.dtsi index d6fc306..f7daa09 100644
> --- a/arch/arm/boot/dts/exynos4210.dtsi
> +++ b/arch/arm/boot/dts/exynos4210.dtsi
> @@ -50,6 +50,12 @@
> samsung,mct-nr-local-irqs = <4>;
> };
>
> + clock: clock-controller@0x1003 {
> + compatible = "samsung,exynos4210-clock";
> + reg = <0x1003 0x2>;
> + #clock-cells = <1>;
> + };
> +
> pinctrl_0: pinctrl@1140 {
> compatible = "samsung,pinctrl-exynos4210";
> reg = <0x1140 0x1000>;
> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
> b/arch/arm/boot/dts/exynos4x12.dtsi index 7cbbd19..bcfdaac 100644
> --- a/arch/arm/boot/dts/exynos4x12.dtsi
> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
> @@ -35,6 +35,12 @@
><0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
> };
>
> + clock: clock-controller@0x1003 {
> + compatible = "samsung,exynos4412-clock";
nitpick: I forgot to mention about it in my comments for patch 3, but
wouldn't it be better to call it "samsung,exynos4x12-clock"?
> + reg = <0x1003 0x2>;
> + #clock-cells = <1>;
> + };
> +
> pinctrl_0: pinctrl@1140 {
> compatible = "samsung,pinctrl-exynos4x12";
> reg = <0x1140 0x1000>;
Otherwise looks fine.
Best regards,
Tomasz Figa
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Re: [PATCH v3 03/11] clk: exynos4: register clocks using common clock framework
Hi Thomas, Looks mostly good, but I have some minor comments inline. On Thursday 15 of November 2012 03:37:25 Thomas Abraham wrote: > The Exynos4 clocks are statically listed and registered using the > Samsung specific common clock helper functions. Both device tree based > clock lookup and clkdev based clock lookups are supported. > > Cc: Mike Turquette > Cc: Kukjin Kim > Signed-off-by: Thomas Abraham > --- > .../devicetree/bindings/clock/exynos4-clock.txt| 215 +++ > drivers/clk/samsung/Makefile |1 + > drivers/clk/samsung/clk-exynos4.c | 641 > 3 files changed, 857 insertions(+), 0 deletions(-) > create mode 100644 > Documentation/devicetree/bindings/clock/exynos4-clock.txt create mode > 100644 drivers/clk/samsung/clk-exynos4.c > > diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt > b/Documentation/devicetree/bindings/clock/exynos4-clock.txt new file > mode 100644 > index 000..e874add > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt > @@ -0,0 +1,215 @@ > +* Samsung Exynos4 Clock Controller > + > +The Exynos4 clock controller generates and supplies clock to various > controllers +within the Exynos4 SoC. The clock binding described here > is applicable to all +SoC's in the Exynos4 family. > + > +Required Properties: > + > +- comptible: should be one of the following. > + - "samsung,exynos4210-clock" - controller compatible with Exynos4210 > SoC. + - "samsung,exynos4412-clock" - controller compatible with > Exynos4412 SoC. + > +- reg: physical base address of the controller and length of memory > mapped + region. > + > +- #clock-cells: should be 1. > + > +The following is the list of clocks generated by the controller. Each > clock is +assigned an identifier and client nodes use this identifier > to specify the +clock which they consume. Some of the clocks are > available only on a particular +Exynos4 SoC and this is specified where > applicable. > + > + > + [Core Clocks] > + > + Clock ID SoC (if specific) > + --- > + > + xxti1 > + xusbxti 2 > + fin_pll 3 > + fout_apll 4 > + fout_mpll 5 > + fout_epll 6 > + fout_vpll 7 > + sclk_apll 8 > + sclk_mpll 9 > + sclk_epll 10 > + sclk_vpll 11 > + arm_clk 12 > + aclk200 13 > + aclk100 14 > + aclk160 15 > + aclk133 16 > + > + > +[Clock Gate for Special Clocks] > + > + Clock ID SoC (if specific) > + --- > + > + sclk_fimc0 128 > + sclk_fimc1 129 > + sclk_fimc2 130 > + sclk_fimc3 131 > + sclk_cam0 132 > + sclk_cam1 133 > + sclk_csis0 134 > + sclk_csis1 135 > + sclk_hdmi 136 > + sclk_mixer 137 > + sclk_dac138 > + sclk_pixel 139 > + sclk_fimd0 140 > + sclk_mdnie0 141 Exynos4412 > + sclk_mdnie_pwm0 12 142 Exynos4412 > + sclk_mipi0 143 > + sclk_audio0 144 > + sclk_mmc0 145 > + sclk_mmc1 146 > + sclk_mmc2 147 > + sclk_mmc3 148 > + sclk_mmc4 149 > + sclk_sata 150 Exynos4210 > + sclk_uart0 151 > + sclk_uart1 152 > + sclk_uart2 153 > + sclk_uart3 154 > + sclk_uart4 155 > + sclk_audio1 156 > + sclk_audio2 157 > + sclk_spdif 158 > + sclk_spi0 159 > + sclk_spi1 160 > + sclk_spi2 161 > + sclk_slimbus162 > + sclk_fimd1 163 Exynos4210 > + sclk_mipi1 164 Exynos4210 > + sclk_pcm1 165 > + sclk_pcm2 166 > + sclk_i2s1 167 > + sclk_i2s2 168 > + sclk_mipihsi169 Exynos4412 > + > + > + [Peripheral Clock Gates] > + > + Clock ID SoC (if specific) > + --- > + > + fimc0 256 > + fimc1 257 > + fimc2 258 > + fimc3 259 > + csis0 260 > + csis1 261 > + jpeg262 > + smmu_fimc0 263 > + smmu_fimc1 264 > + smmu_fimc2 265 > + smmu_fimc3 266 > + smmu_jpeg 267 > + vp 268 > + mixer 269 > + tvenc 270 Exynos4210 > + hdmi271 > + smmu_tv 272 > + mfc 273 > + smmu_mfcl 274 > + smmu_mfcr 275 > + g3d 276 > + g2d 277 Exynos4210 > + rotator 278 Exynos4210 > + mdma279 Exynos42
Re: [PATCH v3 01/11] clk: samsung: add common clock framework helper functions for Samsung platforms
Hi Thomas,
Looks mostly good, but I have some minor comments inline.
On Thursday 15 of November 2012 03:37:23 Thomas Abraham wrote:
> All Samsung platforms include different types of clock including
> fixed-rate, mux, divider and gate clock types. There are typically
> hundreds of such clocks on each of the Samsung platforms. To enable
> Samsung platforms to register these clocks using the common clock
> framework, a bunch of utility functions are introduced here which
> simplify the clock registration process. The clocks are usually
> statically instantiated and registered with common clock framework.
>
> Cc: Mike Turquette
> Cc: Kukjin Kim
> Signed-off-by: Thomas Abraham
> ---
> drivers/clk/Makefile |1 +
> drivers/clk/samsung/Makefile |5 +
> drivers/clk/samsung/clk.c| 176 ++
> drivers/clk/samsung/clk.h| 218
> ++ 4 files changed, 400
> insertions(+), 0 deletions(-)
> create mode 100644 drivers/clk/samsung/Makefile
> create mode 100644 drivers/clk/samsung/clk.c
> create mode 100644 drivers/clk/samsung/clk.h
>
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index 2701235..808f8e1 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -19,6 +19,7 @@ endif
> obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
> obj-$(CONFIG_ARCH_U8500) += ux500/
> obj-$(CONFIG_ARCH_VT8500)+= clk-vt8500.o
> +obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
>
> # Chip specific
> obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
> new file mode 100644
> index 000..3f926b0
> --- /dev/null
> +++ b/drivers/clk/samsung/Makefile
> @@ -0,0 +1,5 @@
> +#
> +# Samsung Clock specific Makefile
> +#
> +
> +obj-$(CONFIG_PLAT_SAMSUNG) += clk.o
> diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
> new file mode 100644
> index 000..ebc6fb6
> --- /dev/null
> +++ b/drivers/clk/samsung/clk.c
> @@ -0,0 +1,176 @@
> +/*
> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
> + * Copyright (c) 2012 Linaro Ltd.
> + * Author: Thomas Abraham
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as +
> * published by the Free Software Foundation.
> + *
> + * This file includes utility functions to register clocks to common
> + * clock framework for Samsung platforms.
> +*/
> +
> +#include "clk.h"
> +
> +static DEFINE_SPINLOCK(lock);
> +static struct clk **clk_table;
> +static struct clk_onecell_data clk_data;
> +void __iomem *reg_base;
Shouldn't it be static?
> +
> +/* setup the essentials required to support clock lookup using ccf */
> +void __init samsung_clk_init(struct device_node *np, void __iomem
> *base, + unsigned long nr_clks)
> +{
> + reg_base = base;
> + if (!np)
> + return;
> +
> + clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
> + if (!clk_table)
> + panic("could not allocate clock lookup table\n");
> +
> + clk_data.clks = clk_table;
> + clk_data.clk_num = nr_clks;
> + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
> +}
> +
> +/* add a clock instance to the clock lookup table used for dt based
> lookup */ +void samsung_clk_add_lookup(struct clk *clk, unsigned int
> id) +{
> + if (clk_table && id)
I'm not sure if we really need this kind of checks, but if we do, then
shouldn't we also check id against clk_data.clk_num to prevent out of
bound index?
> + clk_table[id] = clk;
> +}
> +
> +/* register a list of fixed clocks */
> +void __init samsung_clk_register_fixed_rate(
> + struct samsung_fixed_rate_clock *list, unsigned int nr_clk)
> +{
> + struct clk *clk;
> + unsigned int idx, ret;
> +
> + for (idx = 0; idx < nr_clk; idx++, list++) {
> + clk = clk_register_fixed_rate(NULL, list->name,
> + list->parent_name, list->flags, list->fixed_rate);
> + if (IS_ERR(clk)) {
> + pr_err("%s: failed to register clock %s\n", __func__,
> + list->name);
> + continue;
> + }
> +
> + samsung_clk_add_lookup(clk, list->id);
> +
> + /*
> + * Unconditionally add a clock lookup for the fixed rate
clocks.
> + * There are not many of these on any of Samsung platforms.
> + */
> + ret = clk_register_clkdev(clk, list->name, NULL);
> + if (ret)
> + pr_err("%s: failed to register clock lookup for %s",
> + __func__, list->name);
> + }
> +}
> +
> +/* register a list of mux clocks */
> +void __init samsung_clk_register_mux(struct samsung_mux_clock *list,
> + unsigned int nr_clk)
> +{
> + struct c
[PATCH v3 11/11] ARM: Exynos: add support for mct clock setup
Add support for mct clock lookup and setup to ensure that the mct clock
is has been turned on.
Cc: Kukjin Kim
Signed-off-by: Thomas Abraham
---
arch/arm/mach-exynos/mct.c |7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index 47bc6b35..09815a9 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -489,7 +489,12 @@ static struct local_timer_ops exynos4_mct_tick_ops
__cpuinitdata = {
static void __init exynos4_timer_resources(struct device_node *np)
{
- struct clk *tick_clk;
+ struct clk *mct_clk, *tick_clk;
+
+ mct_clk = clk_get(NULL, "mct");
+ if (IS_ERR(mct_clk))
+ panic("%s: unable to retrieve mct clock instance\n", __func__);
+ clk_prepare_enable(mct_clk);
tick_clk = clk_get(NULL, "fin_pll");
if (IS_ERR(tick_clk))
--
1.7.4.4
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[PATCH v3 10/11] ARM: Exynos: use fin_pll clock as the tick clock source for mct
With the migration of Exynos4 clocks to use common clock framework, the old
styled 'xtal' clock is not used anymore. Instead, the clock 'fin_pll' is used
as the tick clock for mct controller.
Cc: Kukjin Kim
Signed-off-by: Thomas Abraham
---
arch/arm/mach-exynos/mct.c |8 +---
1 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index cd061b2..47bc6b35 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -489,10 +489,12 @@ static struct local_timer_ops exynos4_mct_tick_ops
__cpuinitdata = {
static void __init exynos4_timer_resources(struct device_node *np)
{
- struct clk *mct_clk;
- mct_clk = clk_get(NULL, "xtal");
+ struct clk *tick_clk;
- clk_rate = clk_get_rate(mct_clk);
+ tick_clk = clk_get(NULL, "fin_pll");
+ if (IS_ERR(tick_clk))
+ panic("%s: unable to determine tick clock rate\n", __func__);
+ clk_rate = clk_get_rate(tick_clk);
reg_base = (np) ? of_iomap(np, 0) : S5P_VA_SYSTIMER;
if (!reg_base)
--
1.7.4.4
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[PATCH v3 09/11] ARM: Exynos4: remove auxdata table from machine file
With support for device tree based clock lookup now available, remove the
auxdata table from exynos4 dt-enabled machine file.
Cc: Kukjin Kim
Signed-off-by: Thomas Abraham
---
arch/arm/mach-exynos/mach-exynos4-dt.c | 68 +---
1 files changed, 2 insertions(+), 66 deletions(-)
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c
b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 059332e..8e72ab7 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -11,77 +11,14 @@
* published by the Free Software Foundation.
*/
+#include
#include
-#include
#include
#include
-#include
-
-#include
-#include
#include "common.h"
-/*
- * The following lookup table is used to override device names when devices
- * are registered from device tree. This is temporarily added to enable
- * device tree support addition for the Exynos4 architecture.
- *
- * For drivers that require platform data to be provided from the machine
- * file, a platform data pointer can also be supplied along with the
- * devices names. Usually, the platform data elements that cannot be parsed
- * from the device tree by the drivers (example: function pointers) are
- * supplied. But it should be noted that this is a temporary mechanism and
- * at some point, the drivers should be capable of parsing all the platform
- * data from the device tree.
- */
-static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
- OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0,
- "exynos4210-uart.0", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1,
- "exynos4210-uart.1", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART2,
- "exynos4210-uart.2", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART3,
- "exynos4210-uart.3", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
- "exynos4-sdhci.0", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(1),
- "exynos4-sdhci.1", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(2),
- "exynos4-sdhci.2", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(3),
- "exynos4-sdhci.3", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
- "s3c2440-i2c.0", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(1),
- "s3c2440-i2c.1", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(2),
- "s3c2440-i2c.2", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(3),
- "s3c2440-i2c.3", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(4),
- "s3c2440-i2c.4", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(5),
- "s3c2440-i2c.5", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(6),
- "s3c2440-i2c.6", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(7),
- "s3c2440-i2c.7", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0,
- "exynos4210-spi.0", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1,
- "exynos4210-spi.1", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2,
- "exynos4210-spi.2", NULL),
- OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
- OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU,
- "exynos-tmu", NULL),
- {},
-};
-
static void __init exynos4_dt_map_io(void)
{
exynos_init_io(NULL, 0);
@@ -89,8 +26,7 @@ static void __init exynos4_dt_map_io(void)
static void __init exynos4_dt_machine_init(void)
{
- of_platform_populate(NULL, of_default_bus_match_table,
- exynos4_auxdata_lookup, NULL);
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static char const *exynos4_dt_compat[] __initdata = {
--
1.7.4.4
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[PATCH v3 08/11] ARM: dts: add clock provider information for all controllers in Exynos4 SoC
For all supported peripheral controllers on Exynos4, add clock lookup information. Cc: Kukjin Kim Signed-off-by: Thomas Abraham --- arch/arm/boot/dts/exynos4.dtsi | 48 1 files changed, 48 insertions(+), 0 deletions(-) diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index db2d4aa..cc73bc2 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -53,6 +53,8 @@ compatible = "samsung,s3c2410-wdt"; reg = <0x1006 0x100>; interrupts = <0 43 0>; + clocks = <&clock 345>; + clock-names = "watchdog"; status = "disabled"; }; @@ -60,6 +62,8 @@ compatible = "samsung,s3c6410-rtc"; reg = <0x1007 0x100>; interrupts = <0 44 0>, <0 45 0>; + clocks = <&clock 346>; + clock-names = "rtc"; status = "disabled"; }; @@ -67,6 +71,8 @@ compatible = "samsung,s5pv210-keypad"; reg = <0x100A 0x100>; interrupts = <0 109 0>; + clocks = <&clock 347>; + clock-names = "keypad"; status = "disabled"; }; @@ -74,6 +80,8 @@ compatible = "samsung,exynos4210-sdhci"; reg = <0x1251 0x100>; interrupts = <0 73 0>; + clocks = <&clock 297>, <&clock 145>; + clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; }; @@ -81,6 +89,8 @@ compatible = "samsung,exynos4210-sdhci"; reg = <0x1252 0x100>; interrupts = <0 74 0>; + clocks = <&clock 298>, <&clock 146>; + clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; }; @@ -88,6 +98,8 @@ compatible = "samsung,exynos4210-sdhci"; reg = <0x1253 0x100>; interrupts = <0 75 0>; + clocks = <&clock 299>, <&clock 147>; + clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; }; @@ -95,6 +107,8 @@ compatible = "samsung,exynos4210-sdhci"; reg = <0x1254 0x100>; interrupts = <0 76 0>; + clocks = <&clock 300>, <&clock 148>; + clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; }; @@ -102,6 +116,8 @@ compatible = "samsung,exynos4210-uart"; reg = <0x1380 0x100>; interrupts = <0 52 0>; + clocks = <&clock 312>, <&clock 151>; + clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; @@ -109,6 +125,8 @@ compatible = "samsung,exynos4210-uart"; reg = <0x1381 0x100>; interrupts = <0 53 0>; + clocks = <&clock 313>, <&clock 152>; + clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; @@ -116,6 +134,8 @@ compatible = "samsung,exynos4210-uart"; reg = <0x1382 0x100>; interrupts = <0 54 0>; + clocks = <&clock 314>, <&clock 153>; + clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; @@ -123,6 +143,8 @@ compatible = "samsung,exynos4210-uart"; reg = <0x1383 0x100>; interrupts = <0 55 0>; + clocks = <&clock 315>, <&clock 154>; + clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; @@ -132,6 +154,8 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x1386 0x100>; interrupts = <0 58 0>; + clocks = <&clock 317>; + clock-names = "i2c"; status = "disabled"; }; @@ -141,6 +165,8 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x1387 0x100>; interrupts = <0 59 0>; + clocks = <&clock 318>; + clock-names = "i2c"; status = "disabled"; }; @@ -150,6 +176,8 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x1388 0x100>; interrupts = <0 60 0>; + clocks = <&clock 319>; + clock-names = "i2c"; status = "disabled"; }; @@ -159,6 +187,8 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x1389 0x100>; interrupts = <0 61 0>; + clocks = <&clock 320>; + clock-names = "i2c"; status = "disabled"; }; @@ -168,6 +198,8 @@ compatible = "samsung,s3c
[PATCH v3 07/11] ARM: Exynos4: allow legacy board support to specify xxti and xusbxti clock speed
The clock speed of xxti and xusbxti clocks depends on the oscillator used on the
board to generate these clocks. For non-dt platforms, allow the board support
for those platforms to set the clock frequency of xxti and xusbxti clocks.
Cc: Kukjin Kim
Signed-off-by: Thomas Abraham
---
arch/arm/mach-exynos/common.c |2 ++
arch/arm/mach-exynos/common.h |1 +
arch/arm/mach-exynos/mach-nuri.c |2 ++
arch/arm/mach-exynos/mach-origen.c |2 ++
arch/arm/mach-exynos/mach-smdkv310.c |2 ++
arch/arm/mach-exynos/mach-universal_c210.c |2 ++
arch/arm/mach-exynos/mct.c |1 +
7 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 138a41d..64c0012 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -65,6 +65,8 @@ static void exynos5_init_clocks(int xtal);
static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
static int exynos_init(void);
+unsigned long xxti_f = 0, xusbxti_f = 0;
+
static struct cpu_table cpu_ids[] __initdata = {
{
.idcode = EXYNOS4210_CPU_ID,
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 2cacd48..f947789 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -22,6 +22,7 @@ void exynos4_restart(char mode, const char *cmd);
void exynos5_restart(char mode, const char *cmd);
void exynos_init_late(void);
+extern unsigned long xxti_f, xusbxti_f;
void exynos4_clk_init(void);
void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 5b5c941..e14332c 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -1332,6 +1332,8 @@ static void __init nuri_map_io(void)
{
exynos_init_io(NULL, 0);
s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
+ xxti_f = 0;
+ xusbxti_f = 2400;
}
static void __init nuri_reserve(void)
diff --git a/arch/arm/mach-exynos/mach-origen.c
b/arch/arm/mach-exynos/mach-origen.c
index d4a0ef1..1196a78 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -754,6 +754,8 @@ static void __init origen_map_io(void)
{
exynos_init_io(NULL, 0);
s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
+ xxti_f = 0;
+ xusbxti_f = 2400;
}
static void __init origen_power_init(void)
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c
b/arch/arm/mach-exynos/mach-smdkv310.c
index ce32dd1..cea4803 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -374,6 +374,8 @@ static void __init smdkv310_map_io(void)
{
exynos_init_io(NULL, 0);
s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
+ xxti_f = 1200;
+ xusbxti_f = 2400;
}
static void __init smdkv310_reserve(void)
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c
b/arch/arm/mach-exynos/mach-universal_c210.c
index 3999c16..3de63cb 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -1095,6 +1095,8 @@ static void __init universal_map_io(void)
exynos_init_io(NULL, 0);
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
+ xxti_f = 0;
+ xusbxti_f = 2400;
}
static void s5p_tv_setup(void)
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index c2e806c..cd061b2 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -532,6 +532,7 @@ static void __init exynos4_timer_init(void)
if (soc_is_exynos4210() || soc_is_exynos4212() ||
soc_is_exynos4412()) {
exynos4_clk_init();
+ exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
}
}
#endif
--
1.7.4.4
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[PATCH v3 06/11] ARM: dts: add xxti and xusbxti fixed rate clock nodes for exynos4 based platforms
The clock frequency of xxti and xusbxti clocks is dependent on the frequency of
the
on-board oscillator that is used to generate these clocks. So allow the
frequency
of these clocks to be specfied from device tree.
Cc: Kukjin Kim
Signed-off-by: Thomas Abraham
---
arch/arm/boot/dts/exynos4210-origen.dts | 12
arch/arm/boot/dts/exynos4210-smdkv310.dts | 12
arch/arm/boot/dts/exynos4412-smdk4412.dts | 12
3 files changed, 36 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index f16c99f..de59733 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -121,4 +121,16 @@
linux,default-trigger = "heartbeat";
};
};
+
+ fixed-rate-clocks {
+ xxti {
+ compatible = "samsung,clock-xxti", "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ xusbxti {
+ compatible = "samsung,clock-xusbxti", "fixed-clock";
+ clock-frequency = <2400>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts
b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 9b23a82..9a379eb 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -189,4 +189,16 @@
};
};
};
+
+ fixed-rate-clocks {
+ xxti {
+ compatible = "samsung,clock-xxti", "fixed-clock";
+ clock-frequency = <1200>;
+ };
+
+ xusbxti {
+ compatible = "samsung,clock-xusbxti", "fixed-clock";
+ clock-frequency = <2400>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts
b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index f05bf57..8f422fc 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -42,4 +42,16 @@
serial@1383 {
status = "okay";
};
+
+ fixed-rate-clocks {
+ xxti {
+ compatible = "samsung,clock-xxti", "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ xusbxti {
+ compatible = "samsung,clock-xusbxti", "fixed-clock";
+ clock-frequency = <2400>;
+ };
+ };
};
--
1.7.4.4
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[PATCH v3 05/11] ARM: dts: add exynos4 clock controller nodes
Add clock controller nodes for Exynos4210 and Exynos4x12 SoC's.
Cc: Kukjin Kim
Signed-off-by: Thomas Abraham
---
arch/arm/boot/dts/exynos4210.dtsi |6 ++
arch/arm/boot/dts/exynos4x12.dtsi |6 ++
2 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index d6fc306..f7daa09 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -50,6 +50,12 @@
samsung,mct-nr-local-irqs = <4>;
};
+ clock: clock-controller@0x1003 {
+ compatible = "samsung,exynos4210-clock";
+ reg = <0x1003 0x2>;
+ #clock-cells = <1>;
+ };
+
pinctrl_0: pinctrl@1140 {
compatible = "samsung,pinctrl-exynos4210";
reg = <0x1140 0x1000>;
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
b/arch/arm/boot/dts/exynos4x12.dtsi
index 7cbbd19..bcfdaac 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -35,6 +35,12 @@
<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
};
+ clock: clock-controller@0x1003 {
+ compatible = "samsung,exynos4412-clock";
+ reg = <0x1003 0x2>;
+ #clock-cells = <1>;
+ };
+
pinctrl_0: pinctrl@1140 {
compatible = "samsung,pinctrl-exynos4x12";
reg = <0x1140 0x1000>;
--
1.7.4.4
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[PATCH v3 03/11] clk: exynos4: register clocks using common clock framework
The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Cc: Mike Turquette Cc: Kukjin Kim Signed-off-by: Thomas Abraham --- .../devicetree/bindings/clock/exynos4-clock.txt| 215 +++ drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos4.c | 641 3 files changed, 857 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos4-clock.txt create mode 100644 drivers/clk/samsung/clk-exynos4.c diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt new file mode 100644 index 000..e874add --- /dev/null +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt @@ -0,0 +1,215 @@ +* Samsung Exynos4 Clock Controller + +The Exynos4 clock controller generates and supplies clock to various controllers +within the Exynos4 SoC. The clock binding described here is applicable to all +SoC's in the Exynos4 family. + +Required Properties: + +- comptible: should be one of the following. + - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC. + - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC. + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +The following is the list of clocks generated by the controller. Each clock is +assigned an identifier and client nodes use this identifier to specify the +clock which they consume. Some of the clocks are available only on a particular +Exynos4 SoC and this is specified where applicable. + + +[Core Clocks] + + Clock ID SoC (if specific) + --- + + xxti1 + xusbxti 2 + fin_pll 3 + fout_apll 4 + fout_mpll 5 + fout_epll 6 + fout_vpll 7 + sclk_apll 8 + sclk_mpll 9 + sclk_epll 10 + sclk_vpll 11 + arm_clk 12 + aclk200 13 + aclk100 14 + aclk160 15 + aclk133 16 + + +[Clock Gate for Special Clocks] + + Clock ID SoC (if specific) + --- + + sclk_fimc0 128 + sclk_fimc1 129 + sclk_fimc2 130 + sclk_fimc3 131 + sclk_cam0 132 + sclk_cam1 133 + sclk_csis0 134 + sclk_csis1 135 + sclk_hdmi 136 + sclk_mixer 137 + sclk_dac138 + sclk_pixel 139 + sclk_fimd0 140 + sclk_mdnie0 141 Exynos4412 + sclk_mdnie_pwm0 12 142 Exynos4412 + sclk_mipi0 143 + sclk_audio0 144 + sclk_mmc0 145 + sclk_mmc1 146 + sclk_mmc2 147 + sclk_mmc3 148 + sclk_mmc4 149 + sclk_sata 150 Exynos4210 + sclk_uart0 151 + sclk_uart1 152 + sclk_uart2 153 + sclk_uart3 154 + sclk_uart4 155 + sclk_audio1 156 + sclk_audio2 157 + sclk_spdif 158 + sclk_spi0 159 + sclk_spi1 160 + sclk_spi2 161 + sclk_slimbus162 + sclk_fimd1 163 Exynos4210 + sclk_mipi1 164 Exynos4210 + sclk_pcm1 165 + sclk_pcm2 166 + sclk_i2s1 167 + sclk_i2s2 168 + sclk_mipihsi169 Exynos4412 + + + [Peripheral Clock Gates] + + Clock ID SoC (if specific) + --- + + fimc0 256 + fimc1 257 + fimc2 258 + fimc3 259 + csis0 260 + csis1 261 + jpeg262 + smmu_fimc0 263 + smmu_fimc1 264 + smmu_fimc2 265 + smmu_fimc3 266 + smmu_jpeg 267 + vp 268 + mixer 269 + tvenc 270 Exynos4210 + hdmi271 + smmu_tv 272 + mfc 273 + smmu_mfcl 274 + smmu_mfcr 275 + g3d 276 + g2d 277 Exynos4210 + rotator 278 Exynos4210 + mdma279 Exynos4210 + smmu_g2d280 Exynos4210 + smmu_rotator281 Exynos4210 + smmu_mdma 282 Exynos4210 + fimd0 283 + mie0284 + mdnie0 285 Exynos4412 + dsim0 286 + smmu_fimd0 287 + fimd1 288 Exynos4210 + mie1289 Exynos4210 + dsim1 290 Exynos4210 + smmu_fimd1
[PATCH v3 02/11] clk: samsung: add pll clock registration helper functions
There are several types of pll clocks used in Samsung SoC's and these pll
clocks can be represented as Samsung specific pll clock types and registered
with the common clock framework. Add support for pll35xx, pll36xx, pll45xx and
pll46xx clock types and helper functions to register them.
Cc: Mike Turquette
Cc: Kukjin Kim
Signed-off-by: Thomas Abraham
---
drivers/clk/samsung/Makefile |2 +-
drivers/clk/samsung/clk-pll.c | 400 +
drivers/clk/samsung/clk-pll.h | 38
3 files changed, 439 insertions(+), 1 deletions(-)
create mode 100644 drivers/clk/samsung/clk-pll.c
create mode 100644 drivers/clk/samsung/clk-pll.h
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 3f926b0..a5bf189 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -2,4 +2,4 @@
# Samsung Clock specific Makefile
#
-obj-$(CONFIG_PLAT_SAMSUNG) += clk.o
+obj-$(CONFIG_PLAT_SAMSUNG) += clk.o clk-pll.o
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
new file mode 100644
index 000..9073cd6
--- /dev/null
+++ b/drivers/clk/samsung/clk-pll.c
@@ -0,0 +1,400 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2012 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the utility functions to register the pll clocks.
+*/
+
+#include
+#include "clk.h"
+#include "clk-pll.h"
+
+/*
+ * PLL35xx Clock Type
+ */
+
+#define PLL35XX_MDIV_MASK (0x3FF)
+#define PLL35XX_PDIV_MASK (0x3F)
+#define PLL35XX_SDIV_MASK (0x7)
+#define PLL35XX_MDIV_SHIFT (16)
+#define PLL35XX_PDIV_SHIFT (8)
+#define PLL35XX_SDIV_SHIFT (0)
+
+struct samsung_clk_pll35xx {
+ struct clk_hw hw;
+ const void __iomem *con_reg;
+};
+
+#define to_clk_pll35xx(_hw) container_of(_hw, struct samsung_clk_pll35xx, hw)
+
+static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll35xx *pll = to_clk_pll35xx(hw);
+ u32 mdiv, pdiv, sdiv, pll_con;
+ u64 fvco = parent_rate;
+
+ pll_con = __raw_readl(pll->con_reg);
+ mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
+ pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
+ sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
+
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+
+ return (unsigned long)fvco;
+}
+
+/* todo: implement pl35xx clock round rate operation */
+static long samsung_pll35xx_round_rate(struct clk_hw *hw,
+ unsigned long drate, unsigned long *prate)
+{
+ return -ENOTSUPP;
+}
+
+/* todo: implement pl35xx clock set rate */
+static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ return -ENOTSUPP;
+}
+
+static const struct clk_ops samsung_pll35xx_clk_ops = {
+ .recalc_rate = samsung_pll35xx_recalc_rate,
+ .round_rate = samsung_pll35xx_round_rate,
+ .set_rate = samsung_pll35xx_set_rate,
+};
+
+struct clk * __init samsung_clk_register_pll35xx(const char *name,
+ const char *pname, const void __iomem *con_reg)
+{
+ struct samsung_clk_pll35xx *pll;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll) {
+ pr_err("%s: could not allocate pll clk %s\n", __func__, name);
+ return NULL;
+ }
+
+ init.name = name;
+ init.ops = &samsung_pll35xx_clk_ops;
+ init.flags = CLK_GET_RATE_NOCACHE;
+ init.parent_names = &pname;
+ init.num_parents = 1;
+
+ pll->hw.init = &init;
+ pll->con_reg = con_reg;
+
+ clk = clk_register(NULL, &pll->hw);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register pll clock %s\n", __func__,
+ name);
+ kfree(pll);
+ }
+
+ if (clk_register_clkdev(clk, name, NULL))
+ pr_err("%s: failed to register lookup for %s", __func__, name);
+
+ return clk;
+}
+
+/*
+ * PLL36xx Clock Type
+ */
+
+#define PLL36XX_KDIV_MASK (0x)
+#define PLL36XX_MDIV_MASK (0x1FF)
+#define PLL36XX_PDIV_MASK (0x3F)
+#define PLL36XX_SDIV_MASK (0x7)
+#define PLL36XX_MDIV_SHIFT (16)
+#define PLL36XX_PDIV_SHIFT (8)
+#define PLL36XX_SDIV_SHIFT (0)
+
+struct samsung_clk_pll36xx {
+ struct clk_hw hw;
+ const void __iomem *con_reg;
+};
+
+#define to_clk_pll36xx(_hw) container_of(_hw, struct samsung_clk_pll36xx, hw)
+
+static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
+ un
[PATCH v3 01/11] clk: samsung: add common clock framework helper functions for Samsung platforms
All Samsung platforms include different types of clock including fixed-rate,
mux, divider and gate clock types. There are typically hundreds of such clocks
on each of the Samsung platforms. To enable Samsung platforms to register these
clocks using the common clock framework, a bunch of utility functions are
introduced here which simplify the clock registration process. The clocks are
usually statically instantiated and registered with common clock framework.
Cc: Mike Turquette
Cc: Kukjin Kim
Signed-off-by: Thomas Abraham
---
drivers/clk/Makefile |1 +
drivers/clk/samsung/Makefile |5 +
drivers/clk/samsung/clk.c| 176 ++
drivers/clk/samsung/clk.h| 218 ++
4 files changed, 400 insertions(+), 0 deletions(-)
create mode 100644 drivers/clk/samsung/Makefile
create mode 100644 drivers/clk/samsung/clk.c
create mode 100644 drivers/clk/samsung/clk.h
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 2701235..808f8e1 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -19,6 +19,7 @@ endif
obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
obj-$(CONFIG_ARCH_U8500) += ux500/
obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
+obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
# Chip specific
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
new file mode 100644
index 000..3f926b0
--- /dev/null
+++ b/drivers/clk/samsung/Makefile
@@ -0,0 +1,5 @@
+#
+# Samsung Clock specific Makefile
+#
+
+obj-$(CONFIG_PLAT_SAMSUNG) += clk.o
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
new file mode 100644
index 000..ebc6fb6
--- /dev/null
+++ b/drivers/clk/samsung/clk.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2012 Linaro Ltd.
+ * Author: Thomas Abraham
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file includes utility functions to register clocks to common
+ * clock framework for Samsung platforms.
+*/
+
+#include "clk.h"
+
+static DEFINE_SPINLOCK(lock);
+static struct clk **clk_table;
+static struct clk_onecell_data clk_data;
+void __iomem *reg_base;
+
+/* setup the essentials required to support clock lookup using ccf */
+void __init samsung_clk_init(struct device_node *np, void __iomem *base,
+ unsigned long nr_clks)
+{
+ reg_base = base;
+ if (!np)
+ return;
+
+ clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
+ if (!clk_table)
+ panic("could not allocate clock lookup table\n");
+
+ clk_data.clks = clk_table;
+ clk_data.clk_num = nr_clks;
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+
+/* add a clock instance to the clock lookup table used for dt based lookup */
+void samsung_clk_add_lookup(struct clk *clk, unsigned int id)
+{
+ if (clk_table && id)
+ clk_table[id] = clk;
+}
+
+/* register a list of fixed clocks */
+void __init samsung_clk_register_fixed_rate(
+ struct samsung_fixed_rate_clock *list, unsigned int nr_clk)
+{
+ struct clk *clk;
+ unsigned int idx, ret;
+
+ for (idx = 0; idx < nr_clk; idx++, list++) {
+ clk = clk_register_fixed_rate(NULL, list->name,
+ list->parent_name, list->flags, list->fixed_rate);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n", __func__,
+ list->name);
+ continue;
+ }
+
+ samsung_clk_add_lookup(clk, list->id);
+
+ /*
+* Unconditionally add a clock lookup for the fixed rate clocks.
+* There are not many of these on any of Samsung platforms.
+*/
+ ret = clk_register_clkdev(clk, list->name, NULL);
+ if (ret)
+ pr_err("%s: failed to register clock lookup for %s",
+ __func__, list->name);
+ }
+}
+
+/* register a list of mux clocks */
+void __init samsung_clk_register_mux(struct samsung_mux_clock *list,
+ unsigned int nr_clk)
+{
+ struct clk *clk;
+ unsigned int idx, ret;
+
+ for (idx = 0; idx < nr_clk; idx++, list++) {
+ clk = clk_register_mux(NULL, list->name, list->parent_names,
+ list->num_parents, list->flags, reg_base + list->offset,
+ list->shift, list->width, list->mux_flags, &lock);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n", __func__,
+ list->name);
+
[PATCH v3 00/11] clk: exynos4: migrate to common clock framework
This patch series migrates the Samsung Exynos4 SoC clock code to adopt the common clock framework. The use of Samsung specific clock structures has been removed and all board support code has been updated. imx-style of clock registration and lookup has been adopted for device tree based exynos4 platforms. This patch series is based on the for-next branch of Samsung maintainer's tree with all patches merged from clk-next branch of Mike's tree. This series has been tested on Exynos4210 based Origen board and Exynos4412 based smdk board. Thomas Abraham (11): clk: samsung: add common clock framework helper functions for Samsung platforms clk: samsung: add pll clock registration helper functions clk: exynos4: register clocks using common clock framework ARM: Exynos4: Migrate clock support to common clock framework ARM: dts: add exynos4 clock controller nodes ARM: dts: add xxti and xusbxti fixed rate clock nodes for exynos4 based platforms ARM: Exynos4: allow legacy board support to specify xxti and xusbxti clock speed ARM: dts: add clock provider information for all controllers in Exynos4 SoC ARM: Exynos4: remove auxdata table from machine file ARM: Exynos: use fin_pll clock as the tick clock source for mct ARM: Exynos: add support for mct clock setup .../devicetree/bindings/clock/exynos4-clock.txt| 215 +++ arch/arm/boot/dts/exynos4.dtsi | 48 + arch/arm/boot/dts/exynos4210-origen.dts| 12 + arch/arm/boot/dts/exynos4210-smdkv310.dts | 12 + arch/arm/boot/dts/exynos4210.dtsi |6 + arch/arm/boot/dts/exynos4412-smdk4412.dts | 12 + arch/arm/boot/dts/exynos4x12.dtsi |6 + arch/arm/mach-exynos/Kconfig |1 + arch/arm/mach-exynos/Makefile |3 - arch/arm/mach-exynos/clock-exynos4.c | 1602 arch/arm/mach-exynos/clock-exynos4.h | 35 - arch/arm/mach-exynos/clock-exynos4210.c| 188 --- arch/arm/mach-exynos/clock-exynos4212.c| 192 --- arch/arm/mach-exynos/common.c | 24 +- arch/arm/mach-exynos/common.h |4 + arch/arm/mach-exynos/mach-armlex4210.c |1 - arch/arm/mach-exynos/mach-exynos4-dt.c | 69 +- arch/arm/mach-exynos/mach-nuri.c |3 +- arch/arm/mach-exynos/mach-origen.c |3 +- arch/arm/mach-exynos/mach-smdk4x12.c |1 - arch/arm/mach-exynos/mach-smdkv310.c |3 +- arch/arm/mach-exynos/mach-universal_c210.c |3 +- arch/arm/mach-exynos/mct.c | 33 +- arch/arm/plat-samsung/Kconfig |4 +- drivers/clk/Makefile |1 + drivers/clk/samsung/Makefile |6 + drivers/clk/samsung/clk-exynos4.c | 641 drivers/clk/samsung/clk-pll.c | 400 + drivers/clk/samsung/clk-pll.h | 38 + drivers/clk/samsung/clk.c | 176 +++ drivers/clk/samsung/clk.h | 218 +++ 31 files changed, 1842 insertions(+), 2118 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos4-clock.txt delete mode 100644 arch/arm/mach-exynos/clock-exynos4.c delete mode 100644 arch/arm/mach-exynos/clock-exynos4.h delete mode 100644 arch/arm/mach-exynos/clock-exynos4210.c delete mode 100644 arch/arm/mach-exynos/clock-exynos4212.c create mode 100644 drivers/clk/samsung/Makefile create mode 100644 drivers/clk/samsung/clk-exynos4.c create mode 100644 drivers/clk/samsung/clk-pll.c create mode 100644 drivers/clk/samsung/clk-pll.h create mode 100644 drivers/clk/samsung/clk.c create mode 100644 drivers/clk/samsung/clk.h -- 1.7.4.4 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH] ASoC: Samsung: Register the audio platform device
Audio platform device is not a hardware peripherial.
So this device can't be added in the dt devices list.
So expanded the module_platform_driver and registered
this device using "platform_device_register_simple".
Also added the soc-core pm ops structure in the audio
platform driver.
Signed-off-by: Padmavathi Venna
---
sound/soc/samsung/smdk_wm8994.c | 31 ++-
1 files changed, 30 insertions(+), 1 deletions(-)
diff --git a/sound/soc/samsung/smdk_wm8994.c b/sound/soc/samsung/smdk_wm8994.c
index 48dd4dd..7f97969 100644
--- a/sound/soc/samsung/smdk_wm8994.c
+++ b/sound/soc/samsung/smdk_wm8994.c
@@ -173,16 +173,45 @@ static int __devexit smdk_audio_remove(struct
platform_device *pdev)
return 0;
}
+static struct platform_device *smdk_audio_device;
+
static struct platform_driver smdk_audio_driver = {
.driver = {
.name = "smdk-audio",
.owner = THIS_MODULE,
+ .pm = &snd_soc_pm_ops,
},
.probe = smdk_audio_probe,
.remove = __devexit_p(smdk_audio_remove),
};
-module_platform_driver(smdk_audio_driver);
+static int __init smdk_audio_init(void)
+{
+ int ret;
+
+ ret = platform_driver_register(&smdk_audio_driver);
+ if (ret) {
+ pr_err("unable to register driver\n");
+ return ret;
+ }
+
+ smdk_audio_device = platform_device_register_simple("smdk-audio", -1,
NULL, 0);
+ if (IS_ERR(smdk_audio_device)) {
+ platform_driver_unregister(&smdk_audio_driver);
+ return PTR_ERR(smdk_audio_device);
+ }
+
+ return 0;
+}
+
+static void __exit smdk_audio_exit(void)
+{
+ platform_device_unregister(smdk_audio_device);
+ platform_driver_unregister(&smdk_audio_driver);
+}
+
+module_init(smdk_audio_init);
+module_exit(smdk_audio_exit);
MODULE_DESCRIPTION("ALSA SoC SMDK WM8994");
MODULE_LICENSE("GPL");
--
1.7.4.4
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[RFC PATCH] ASoC: Samsung: Register the audio dma platform device
Audio dma device is not a hardware peripherial.
So this device can't be added in the dt devices list.
So expanded the module_platform_driver and registered
this device using "platform_device_register_simple".
Signed-off-by: Padmavathi Venna
---
sound/soc/samsung/dma.c | 30 +-
1 files changed, 29 insertions(+), 1 deletions(-)
diff --git a/sound/soc/samsung/dma.c b/sound/soc/samsung/dma.c
index 359708c..17ae9c0 100644
--- a/sound/soc/samsung/dma.c
+++ b/sound/soc/samsung/dma.c
@@ -444,6 +444,8 @@ static int __devexit samsung_asoc_platform_remove(struct
platform_device *pdev)
return 0;
}
+static struct platform_device *asoc_dma_device;
+
static struct platform_driver asoc_dma_driver = {
.driver = {
.name = "samsung-audio",
@@ -454,7 +456,33 @@ static struct platform_driver asoc_dma_driver = {
.remove = __devexit_p(samsung_asoc_platform_remove),
};
-module_platform_driver(asoc_dma_driver);
+static int __init asoc_dma_init(void)
+{
+ int ret;
+
+ ret = platform_driver_register(&asoc_dma_driver);
+ if (ret) {
+ pr_err("unable to register driver\n");
+ return ret;
+ }
+
+ asoc_dma_device = platform_device_register_simple("samsung-audio", -1,
NULL, 0);
+ if (IS_ERR(asoc_dma_device)) {
+ platform_driver_unregister(&asoc_dma_driver);
+ return PTR_ERR(asoc_dma_device);
+ }
+
+ return 0;
+}
+
+static void __exit asoc_dma_exit(void)
+{
+ platform_device_unregister(asoc_dma_device);
+ platform_driver_unregister(&asoc_dma_driver);
+}
+
+module_init(asoc_dma_init);
+module_exit(asoc_dma_exit);
MODULE_AUTHOR("Ben Dooks, ");
MODULE_DESCRIPTION("Samsung ASoC DMA Driver");
--
1.7.4.4
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[PATCH v8 3/3] ARM: EXYNOS: Enabling samsung-usbphy driver for EXYNOS4210
Adding usbphy node for Exynos4210 along with the platform data.
Signed-off-by: Praveen Paneri
---
arch/arm/boot/dts/exynos4210-smdkv310.dts |5 +
arch/arm/mach-exynos/Kconfig |1 +
arch/arm/mach-exynos/include/mach/map.h |1 +
arch/arm/mach-exynos/mach-exynos4-dt.c|8
arch/arm/mach-exynos/setup-usb-phy.c | 13 +
5 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts
b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 9b23a82..550903a 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -59,6 +59,11 @@
status = "okay";
};
+ usbphy@125B {
+ compatible = "samsung,exynos4210-usbphy";
+ reg = <0x125B 0x100>;
+ };
+
keypad@100A {
samsung,keypad-num-rows = <2>;
samsung,keypad-num-columns = <8>;
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index bb3b09a..315308c 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -410,6 +410,7 @@ config MACH_EXYNOS4_DT
select PINCTRL
select PINCTRL_EXYNOS4
select USE_OF
+ select EXYNOS4_SETUP_USB_PHY
help
Machine support for Samsung Exynos4 machine with device tree enabled.
Select this if a fdt blob is available for the Exynos4 SoC based
board.
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index ef4958b..e64fe1c 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -244,6 +244,7 @@
#define S3C_PA_SPI1EXYNOS4_PA_SPI1
#define S3C_PA_SPI2EXYNOS4_PA_SPI2
#define S3C_PA_USB_HSOTG EXYNOS4_PA_HSOTG
+#define S3C_PA_USB_PHY EXYNOS4_PA_HSPHY
#define S5P_PA_EHCIEXYNOS4_PA_EHCI
#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c
b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 8858068..f7887e5 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -13,6 +13,7 @@
#include
#include
+#include
#include
#include
@@ -20,9 +21,14 @@
#include
#include
+#include
#include "common.h"
+static struct samsung_usbphy_data exynos4_usbphy_pdata = {
+ .pmu_isolation = s5p_usb_phy_pmu_isolation,
+};
+
/*
* The following lookup table is used to override device names when devices
* are registered from device tree. This is temporarily added to enable
@@ -79,6 +85,8 @@ static const struct of_dev_auxdata exynos4_auxdata_lookup[]
__initconst = {
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU,
"exynos-tmu", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-usbphy", EXYNOS4_PA_HSPHY,
+ "s3c-usbphy", &exynos4_usbphy_pdata),
{},
};
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c
b/arch/arm/mach-exynos/setup-usb-phy.c
index b81cc56..1c62d20 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -221,3 +221,16 @@ int s5p_usb_phy_exit(struct platform_device *pdev, int
type)
return -EINVAL;
}
+
+void s5p_usb_phy_pmu_isolation(int on)
+{
+ if (on) {
+ writel(readl(S5P_USBDEVICE_PHY_CONTROL)
+ & ~S5P_USBDEVICE_PHY_ENABLE,
+ S5P_USBDEVICE_PHY_CONTROL);
+ } else {
+ writel(readl(S5P_USBDEVICE_PHY_CONTROL)
+ | S5P_USBDEVICE_PHY_ENABLE,
+ S5P_USBDEVICE_PHY_CONTROL);
+ }
+}
--
1.7.1
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[PATCH v8 2/3] ARM: S3C64XX: Enabling samsung-usbphy driver
Adding platform device for samsung-usbphy driver. Enabling it for
s3c64xx based machines using s3c-hsotg.
Signed-off-by: Praveen Paneri
---
arch/arm/mach-s3c64xx/include/mach/map.h |2 +
arch/arm/mach-s3c64xx/mach-crag6410.c|7 ++
arch/arm/mach-s3c64xx/mach-smartq.c |8 +++
arch/arm/mach-s3c64xx/mach-smdk6410.c|7 ++
arch/arm/mach-s3c64xx/setup-usb-phy.c| 14 +
arch/arm/plat-samsung/devs.c | 28 ++
arch/arm/plat-samsung/include/plat/devs.h|1 +
arch/arm/plat-samsung/include/plat/usb-phy.h |1 +
8 files changed, 68 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h
b/arch/arm/mach-s3c64xx/include/mach/map.h
index 8e2097b..dc482bb 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -65,6 +65,7 @@
#define S3C64XX_PA_NAND(0x7020)
#define S3C64XX_PA_FB (0x7710)
+#define S3C64XX_PA_USB_HSPHY (0x7C10)
#define S3C64XX_PA_USB_HSOTG (0x7C00)
#define S3C64XX_PA_WATCHDOG(0x7E004000)
#define S3C64XX_PA_RTC (0x7E005000)
@@ -113,6 +114,7 @@
#define S3C_PA_FB S3C64XX_PA_FB
#define S3C_PA_USBHOST S3C64XX_PA_USBHOST
#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG
+#define S3C_PA_USB_PHY S3C64XX_PA_USB_HSPHY
#define S3C_PA_RTC S3C64XX_PA_RTC
#define S3C_PA_WDT S3C64XX_PA_WATCHDOG
#define S3C_PA_SPI0S3C64XX_PA_SPI0
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c
b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 48f4a2d..c602379 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -31,6 +31,7 @@
#include
#include
+#include
#include
@@ -69,6 +70,7 @@
#include
#include
#include
+#include
#include "common.h"
@@ -353,6 +355,7 @@ static struct platform_device wallvdd_device = {
};
static struct platform_device *crag6410_devices[] __initdata = {
+ &samsung_device_usbphy,
&s3c_device_hsmmc0,
&s3c_device_hsmmc2,
&s3c_device_i2c0,
@@ -804,6 +807,9 @@ static const struct gpio_led_platform_data gpio_leds_pdata
= {
.num_leds = ARRAY_SIZE(gpio_leds),
};
+static struct samsung_usbphy_data crag6410_usbphy_pdata __initdata = {
+ .pmu_isolation = s5p_usb_phy_pmu_isolation,
+};
static void __init crag6410_machine_init(void)
{
@@ -829,6 +835,7 @@ static void __init crag6410_machine_init(void)
s3c_i2c0_set_platdata(&i2c0_pdata);
s3c_i2c1_set_platdata(&i2c1_pdata);
s3c_fb_set_platdata(&crag6410_lcd_pdata);
+ samsung_usbphy_set_pdata(&crag6410_usbphy_pdata);
i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c
b/arch/arm/mach-s3c64xx/mach-smartq.c
index 59bb34c..f18a0ab 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
@@ -36,6 +37,7 @@
#include
#include
#include
+#include
#include
@@ -234,6 +236,7 @@ static struct i2c_board_info smartq_i2c_devs[] __initdata =
{
};
static struct platform_device *smartq_devices[] __initdata = {
+ &samsung_device_usbphy,
&s3c_device_hsmmc1, /* Init iNAND first, ... */
&s3c_device_hsmmc0, /* ... then the external SD card */
&s3c_device_hsmmc2,
@@ -380,9 +383,14 @@ void __init smartq_map_io(void)
smartq_lcd_mode_set();
}
+static struct samsung_usbphy_data smartq_usbphy_pdata __initdata = {
+ .pmu_isolation = s5p_usb_phy_pmu_isolation,
+};
+
void __init smartq_machine_init(void)
{
s3c_i2c0_set_platdata(NULL);
+ samsung_usbphy_set_pdata(&smartq_usbphy_pdata);
s3c_hwmon_set_platdata(&smartq_hwmon_pdata);
s3c_sdhci1_set_platdata(&smartq_internal_hsmmc_pdata);
s3c_sdhci2_set_platdata(&smartq_internal_hsmmc_pdata);
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c
b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 123f452..00e46a6 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -30,6 +30,7 @@
#include
#include
#include
+#include
#ifdef CONFIG_SMDK6410_WM1190_EV1
#include
@@ -72,6 +73,7 @@
#include
#include
#include
+#include
#include "common.h"
@@ -263,6 +265,7 @@ static struct samsung_keypad_platdata smdk6410_keypad_data
__initdata = {
static struct map_desc smdk6410_iodesc[] = {};
static struct platform_device *smdk6410_devices[] __initdata = {
+ &samsung_device_usbphy,
#ifdef CONFIG_SMDK6410_SD_CH0
&s3c_device_hsmmc0,
#endif
@@ -626,6 +629,9 @@ static struct platform_pwm_backlight_data smdk6410_bl_data
= {
.pwm_id = 1,
};
+static struct sam
[PATCH v8 1/3] ARM: S3C64XX: Removing old phy setup code
This patch removes old phy code from platform side. 'setup-usb-phy.c'
will be used for providing transceiver platform data in next
patch. Not all of the platform data code is removed as there are others
making use of platform_data defined for hsotg. That can be removed once
all the SoCs start using the new transceiver for usb phy setup.
Signed-off-by: Praveen Paneri
---
arch/arm/mach-s3c64xx/mach-crag6410.c |3 -
arch/arm/mach-s3c64xx/mach-smartq.c |3 -
arch/arm/mach-s3c64xx/mach-smdk6410.c |3 -
arch/arm/mach-s3c64xx/setup-usb-phy.c | 79 -
4 files changed, 0 insertions(+), 88 deletions(-)
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c
b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 2abe95d..48f4a2d 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -31,7 +31,6 @@
#include
#include
-#include
#include
@@ -805,7 +804,6 @@ static const struct gpio_led_platform_data gpio_leds_pdata
= {
.num_leds = ARRAY_SIZE(gpio_leds),
};
-static struct s3c_hsotg_plat crag6410_hsotg_pdata;
static void __init crag6410_machine_init(void)
{
@@ -831,7 +829,6 @@ static void __init crag6410_machine_init(void)
s3c_i2c0_set_platdata(&i2c0_pdata);
s3c_i2c1_set_platdata(&i2c1_pdata);
s3c_fb_set_platdata(&crag6410_lcd_pdata);
- s3c_hsotg_set_platdata(&crag6410_hsotg_pdata);
i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c
b/arch/arm/mach-s3c64xx/mach-smartq.c
index c6d7390..59bb34c 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -18,7 +18,6 @@
#include
#include
#include
-#include
#include
#include
@@ -187,7 +186,6 @@ static struct s3c_hwmon_pdata smartq_hwmon_pdata __initdata
= {
},
};
-static struct s3c_hsotg_plat smartq_hsotg_pdata;
static int __init smartq_lcd_setup_gpio(void)
{
@@ -385,7 +383,6 @@ void __init smartq_map_io(void)
void __init smartq_machine_init(void)
{
s3c_i2c0_set_platdata(NULL);
- s3c_hsotg_set_platdata(&smartq_hsotg_pdata);
s3c_hwmon_set_platdata(&smartq_hwmon_pdata);
s3c_sdhci1_set_platdata(&smartq_internal_hsmmc_pdata);
s3c_sdhci2_set_platdata(&smartq_internal_hsmmc_pdata);
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c
b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index da1a771..123f452 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -30,7 +30,6 @@
#include
#include
#include
-#include
#ifdef CONFIG_SMDK6410_WM1190_EV1
#include
@@ -627,7 +626,6 @@ static struct platform_pwm_backlight_data smdk6410_bl_data
= {
.pwm_id = 1,
};
-static struct s3c_hsotg_plat smdk6410_hsotg_pdata;
static void __init smdk6410_map_io(void)
{
@@ -657,7 +655,6 @@ static void __init smdk6410_machine_init(void)
s3c_i2c0_set_platdata(NULL);
s3c_i2c1_set_platdata(NULL);
s3c_fb_set_platdata(&smdk6410_lcd_pdata);
- s3c_hsotg_set_platdata(&smdk6410_hsotg_pdata);
samsung_keypad_set_platdata(&smdk6410_keypad_data);
diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c
b/arch/arm/mach-s3c64xx/setup-usb-phy.c
index f6757e0..7a09553 100644
--- a/arch/arm/mach-s3c64xx/setup-usb-phy.c
+++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c
@@ -9,82 +9,3 @@
*
*/
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-static int s3c_usb_otgphy_init(struct platform_device *pdev)
-{
- struct clk *xusbxti;
- u32 phyclk;
-
- writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
-
- /* set clock frequency for PLL */
- phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK;
-
- xusbxti = clk_get(&pdev->dev, "xusbxti");
- if (xusbxti && !IS_ERR(xusbxti)) {
- switch (clk_get_rate(xusbxti)) {
- case 12 * MHZ:
- phyclk |= S3C_PHYCLK_CLKSEL_12M;
- break;
- case 24 * MHZ:
- phyclk |= S3C_PHYCLK_CLKSEL_24M;
- break;
- default:
- case 48 * MHZ:
- /* default reference clock */
- break;
- }
- clk_put(xusbxti);
- }
-
- /* TODO: select external clock/oscillator */
- writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK);
-
- /* set to normal OTG PHY */
- writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR);
- mdelay(1);
-
- /* reset OTG PHY and Link */
- writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK,
- S3C_RSTCON);
- udelay(20); /* at-least 10uS */
- writel(0, S3C_RSTCON);
-
- return 0;
-}
-
-static
[PATCH v8 0/3] ARM: Exynos/S3C64XX: usb phy driver support for S3C64XX and EXYNOS4210
This patch series enables usb phy driver for S3C64XX and EXYNOS4210. The phy driver patches are already sent to linux-usb. Changes From v7: Resolved build errors with s3c6400_defconfig, s5pv210_defconfig and exynos_defconfig. Tested with all other samsung configs as well. Reformed PATCH 3 (PATCH 5 of last series) with proper subject. Separated these arch patches from the driver patches. Changes from v4: Changed the platform data code to use __initdata Changes from v2: Changed 's3c' to 'samsung' for platform device as well as platform data Moved platform data structure to a separate file Praveen Paneri (3): ARM: S3C64XX: Removing old phy setup code ARM: S3C64XX: Enabling samsung-usbphy driver ARM: EXYNOS: Enabling samsung-usbphy driver for EXYNOS4210 arch/arm/boot/dts/exynos4210-smdkv310.dts|5 ++ arch/arm/mach-exynos/Kconfig |1 + arch/arm/mach-exynos/include/mach/map.h |1 + arch/arm/mach-exynos/mach-exynos4-dt.c |8 +++ arch/arm/mach-exynos/setup-usb-phy.c | 13 arch/arm/mach-s3c64xx/include/mach/map.h |2 + arch/arm/mach-s3c64xx/mach-crag6410.c| 10 ++- arch/arm/mach-s3c64xx/mach-smartq.c | 11 +++- arch/arm/mach-s3c64xx/mach-smdk6410.c| 10 ++- arch/arm/mach-s3c64xx/setup-usb-phy.c| 79 ++--- arch/arm/plat-samsung/devs.c | 28 + arch/arm/plat-samsung/include/plat/devs.h|1 + arch/arm/plat-samsung/include/plat/usb-phy.h |1 + 13 files changed, 89 insertions(+), 81 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v8 2/2] usb: s3c-hsotg: Adding phy driver support
Adding the transceiver to hsotg driver. Keeping the platform data
for continuing the smooth operation for boards which still uses it
Signed-off-by: Praveen Paneri
Acked-by: Kyungmin Park
---
drivers/usb/gadget/s3c-hsotg.c | 37 +++--
1 files changed, 27 insertions(+), 10 deletions(-)
diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index 6f696ee..bc30a2d 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -32,6 +32,7 @@
#include
#include
+#include
#include
#include
@@ -133,7 +134,9 @@ struct s3c_hsotg_ep {
* struct s3c_hsotg - driver state.
* @dev: The parent device supplied to the probe function
* @driver: USB gadget driver
- * @plat: The platform specific configuration data.
+ * @phy: The otg phy transceiver structure for phy control.
+ * @plat: The platform specific configuration data. This can be removed once
+ * all SoCs support usb transceiver.
* @regs: The memory area mapped for accessing registers.
* @irq: The IRQ number we are using
* @supplies: Definition of USB power supplies
@@ -153,6 +156,7 @@ struct s3c_hsotg_ep {
struct s3c_hsotg {
struct device*dev;
struct usb_gadget_driver *driver;
+ struct usb_phy *phy;
struct s3c_hsotg_plat*plat;
spinlock_t lock;
@@ -2854,7 +2858,10 @@ static void s3c_hsotg_phy_enable(struct s3c_hsotg *hsotg)
struct platform_device *pdev = to_platform_device(hsotg->dev);
dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
- if (hsotg->plat->phy_init)
+
+ if (hsotg->phy)
+ usb_phy_init(hsotg->phy);
+ else if (hsotg->plat->phy_init)
hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
}
@@ -2869,7 +2876,9 @@ static void s3c_hsotg_phy_disable(struct s3c_hsotg *hsotg)
{
struct platform_device *pdev = to_platform_device(hsotg->dev);
- if (hsotg->plat->phy_exit)
+ if (hsotg->phy)
+ usb_phy_shutdown(hsotg->phy);
+ else if (hsotg->plat->phy_exit)
hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
}
@@ -3493,6 +3502,7 @@ static void s3c_hsotg_release(struct device *dev)
static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
{
struct s3c_hsotg_plat *plat = pdev->dev.platform_data;
+ struct usb_phy *phy;
struct device *dev = &pdev->dev;
struct s3c_hsotg_ep *eps;
struct s3c_hsotg *hsotg;
@@ -3501,20 +3511,27 @@ static int __devinit s3c_hsotg_probe(struct
platform_device *pdev)
int ret;
int i;
- plat = pdev->dev.platform_data;
- if (!plat) {
- dev_err(&pdev->dev, "no platform data defined\n");
- return -EINVAL;
- }
-
hsotg = devm_kzalloc(&pdev->dev, sizeof(struct s3c_hsotg), GFP_KERNEL);
if (!hsotg) {
dev_err(dev, "cannot get memory\n");
return -ENOMEM;
}
+ phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
+ if (IS_ERR_OR_NULL(phy)) {
+ /* Fallback for pdata */
+ plat = pdev->dev.platform_data;
+ if (!plat) {
+ dev_err(&pdev->dev, "no platform data or transceiver
defined\n");
+ return -EPROBE_DEFER;
+ } else {
+ hsotg->plat = plat;
+ }
+ } else {
+ hsotg->phy = phy;
+ }
+
hsotg->dev = dev;
- hsotg->plat = plat;
hsotg->clk = devm_clk_get(&pdev->dev, "otg");
if (IS_ERR(hsotg->clk)) {
--
1.7.1
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[PATCH v8 1/2] usb: phy: samsung: Introducing usb phy driver for hsotg
This driver uses usb_phy interface to interact with s3c-hsotg. Supports
phy_init and phy_shutdown functions to enable/disable usb phy. Support
will be extended to host controllers and more Samsung SoCs.
Signed-off-by: Praveen Paneri
Acked-by: Heiko Stuebner
Acked-by: Kyungmin Park
---
.../devicetree/bindings/usb/samsung-usbphy.txt | 11 +
drivers/usb/phy/Kconfig|8 +
drivers/usb/phy/Makefile |1 +
drivers/usb/phy/samsung-usbphy.c | 360
include/linux/platform_data/samsung-usbphy.h | 27 ++
5 files changed, 407 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/usb/samsung-usbphy.txt
create mode 100644 drivers/usb/phy/samsung-usbphy.c
create mode 100644 include/linux/platform_data/samsung-usbphy.h
diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
new file mode 100644
index 000..7b26e2d
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
@@ -0,0 +1,11 @@
+* Samsung's usb phy transceiver
+
+The Samsung's phy transceiver is used for controlling usb otg phy for
+s3c-hsotg usb device controller.
+TODO: Adding the PHY binding with controller(s) according to the under
+developement generic PHY driver.
+
+Required properties:
+- compatible : should be "samsung,exynos4210-usbphy"
+- reg : base physical address of the phy registers and length of memory mapped
+ region.
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 7eb73c5..17ad743 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -44,3 +44,11 @@ config USB_RCAR_PHY
To compile this driver as a module, choose M here: the
module will be called rcar-phy.
+
+config SAMSUNG_USBPHY
+ bool "Samsung USB PHY controller Driver"
+ depends on USB_S3C_HSOTG
+ select USB_OTG_UTILS
+ help
+ Enable this to support Samsung USB phy controller for samsung
+ SoCs.
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 1a579a8..ec304f6 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_USB_ISP1301) += isp1301.o
obj-$(CONFIG_MV_U3D_PHY) += mv_u3d_phy.o
obj-$(CONFIG_USB_EHCI_TEGRA) += tegra_usb_phy.o
obj-$(CONFIG_USB_RCAR_PHY) += rcar-phy.o
+obj-$(CONFIG_SAMSUNG_USBPHY) += samsung-usbphy.o
diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c
new file mode 100644
index 000..3c84aab
--- /dev/null
+++ b/drivers/usb/phy/samsung-usbphy.c
@@ -0,0 +1,360 @@
+/* linux/drivers/usb/phy/samsung-usbphy.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Author: Praveen Paneri
+ *
+ * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Register definitions */
+
+#define SAMSUNG_PHYPWR (0x00)
+
+#define PHYPWR_NORMAL_MASK (0x19 << 0)
+#define PHYPWR_OTG_DISABLE (0x1 << 4)
+#define PHYPWR_ANALOG_POWERDOWN(0x1 << 3)
+#define PHYPWR_FORCE_SUSPEND (0x1 << 1)
+/* For Exynos4 */
+#define PHYPWR_NORMAL_MASK_PHY0(0x39 << 0)
+#define PHYPWR_SLEEP_PHY0 (0x1 << 5)
+
+#define SAMSUNG_PHYCLK (0x04)
+
+#define PHYCLK_MODE_USB11 (0x1 << 6)
+#define PHYCLK_EXT_OSC (0x1 << 5)
+#define PHYCLK_COMMON_ON_N (0x1 << 4)
+#define PHYCLK_ID_PULL (0x1 << 2)
+#define PHYCLK_CLKSEL_MASK (0x3 << 0)
+#define PHYCLK_CLKSEL_48M (0x0 << 0)
+#define PHYCLK_CLKSEL_12M (0x2 << 0)
+#define PHYCLK_CLKSEL_24M (0x3 << 0)
+
+#define SAMSUNG_RSTCON (0x08)
+
+#define RSTCON_PHYLINK_SWRST (0x1 << 2)
+#define RSTCON_HLINK_SWRST (0x1 << 1)
+#define RSTCON_SWRST (0x1 << 0)
+
+#ifndef MHZ
+#define MHZ (1000*1000)
+#endif
+
+enum samsung_cpu_type {
+ TYPE_S3C64XX,
+ TYPE_EXYNOS4210,
+};
+
+/*
+ * struct samsung_usbphy - transceiver driver state
+ * @phy: transceiver struc
[PATCH v8 0/2] usb: phy: samsung: Introducing usb phy driver for samsung SoCs
Changes from v7: Rebased to the latest usb-next branch. Separating arch patches from these driver patches. Changes from v6: Modified register definitions according to the existing ones. Changed default PHY clk selection for SoCs. Improved binding text and rebased to the latest usb-next. Changes from v5: Moved clk_get() to driver's probe function. Now reference clock frequency selection value is stored in samsung_usbphy structure for later use. Used IS_ENABLED() instead of #ifdef in samsung_usbphy_get_driver_data(). Changes from v4: Moved header file contents to driver's source file Removed unnecessary print message from driver's probe function Dropped the Free Software Foundation address from the header Changes from v3: Replaced susbsys_initcall()/module_exit() by module_platform_driver(). Accordingly in the hsotg driver returned -EPROBE_DEFER until phy driver is registered Removed unnecessary devm_usb_put_phy() call from the hsotg driver remove. Changes from v2: Changed the driver filenames to samsung-usbphy Rectified coding style related errors Changes from v1: Rebased patches to latest usb-next branch Changed the name 'sec_usbphy' to 'samsung_usbphy' This patch set introduces a phy driver for samsung SoCs. It uses the existing transceiver infrastructure to provide phy control functions. Use of this driver can be extended for usb host phy as well. Over the period of time all the phy related code for most of the samsung SoCs can be integrated here. Removing the existing phy code from mach-s3c64xx. Same can be done for other SoCs when they start supporting this phy driver. This driver is tested with smdk6410 and Exynos4210(with DT). Praveen Paneri (2): usb: phy: samsung: Introducing usb phy driver for hsotg usb: s3c-hsotg: Adding phy driver support .../devicetree/bindings/usb/samsung-usbphy.txt | 11 + drivers/usb/gadget/s3c-hsotg.c | 37 ++- drivers/usb/phy/Kconfig|8 + drivers/usb/phy/Makefile |1 + drivers/usb/phy/samsung-usbphy.c | 360 include/linux/platform_data/samsung-usbphy.h | 27 ++ 6 files changed, 434 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/usb/samsung-usbphy.txt create mode 100644 drivers/usb/phy/samsung-usbphy.c create mode 100644 include/linux/platform_data/samsung-usbphy.h -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] sound: use PTR_ERR to fix the value of the return
On 11/14/2012 12:26 PM, Wang Jing wrote:
> On 2012年11月14日 12:58, Tushar Behera wrote:
>> On 11/13/2012 05:49 PM, Wang Jing wrote:
>>> From: wangjing
>>>
>>> This patch use the macro PTR_ERR to modify the value of the return
>>>
>>> Signed-off-by: wangjing
Also please sign off with a valid e-mail address.
>>> ---
>>> sound/soc/samsung/smdk_spdif.c | 30 +++---
>>> 1 file changed, 15 insertions(+), 15 deletions(-)
>>>
>>> diff --git a/sound/soc/samsung/smdk_spdif.c
>>> b/sound/soc/samsung/smdk_spdif.c
>>> index beaa9c1..8f78482 100644
>>> --- a/sound/soc/samsung/smdk_spdif.c
>>> +++ b/sound/soc/samsung/smdk_spdif.c
>>> @@ -28,32 +28,29 @@ static int set_audio_clock_heirachy(struct
>>> platform_device *pdev)
>>> fout_epll = clk_get(NULL, "fout_epll");
>>> if (IS_ERR(fout_epll)) {
>>> -printk(KERN_WARNING "%s: Cannot find fout_epll.\n",
>>> -__func__);
>>> -return -EINVAL;
>>> +printk(KERN_ERR "%s: Cannot find fout_epll.\n", __func__);
>>> +ret = PTR_ERR(fout_epll);
>>> +return ret;
>> We can have a single statement for the above two statements.
>>
>> return PTR_ERR(fout_epll);
>>
>>> }
>>> mout_epll = clk_get(NULL, "mout_epll");
>>> if (IS_ERR(mout_epll)) {
>>> -printk(KERN_WARNING "%s: Cannot find mout_epll.\n",
>>> -__func__);
>>> -ret = -EINVAL;
>>> +printk(KERN_ERR "%s: Cannot find mout_epll.\n", __func__);
>>> +ret = PTR_ERR(mout_epll);
>>> goto out1;
>>> }
>>> sclk_audio0 = clk_get(&pdev->dev, "sclk_audio");
>>> if (IS_ERR(sclk_audio0)) {
>>> -printk(KERN_WARNING "%s: Cannot find sclk_audio.\n",
>>> -__func__);
>>> -ret = -EINVAL;
>>> +printk(KERN_ERR "%s: Cannot find sclk_audio.\n", __func__);
>>> +ret = PTR_ERR(sclk_audio0);
>>> goto out2;
>>> }
>>> sclk_spdif = clk_get(NULL, "sclk_spdif");
>>> if (IS_ERR(sclk_spdif)) {
>>> -printk(KERN_WARNING "%s: Cannot find sclk_spdif.\n",
>>> -__func__);
>>> -ret = -EINVAL;
>>> +printk(KERN_ERR "%s: Cannot find sclk_spdif.\n", __func__);
>>> +ret = PTR_ERR(sclk_spdif);
>>> goto out3;
>>> }
>>> @@ -81,11 +78,13 @@ static int set_audio_clock_rate(unsigned long
>>> epll_rate,
>>> unsigned long audio_rate)
>>> {
>>> struct clk *fout_epll, *sclk_spdif;
>>> +int ret = 0;
>>> fout_epll = clk_get(NULL, "fout_epll");
>>> if (IS_ERR(fout_epll)) {
>>> printk(KERN_ERR "%s: failed to get fout_epll\n", __func__);
>>> -return -ENOENT;
>>> +ret = PTR_ERR(fout_epll);
>>> +return ret;
>> Same as above.
>>
>>> }
>>> clk_set_rate(fout_epll, epll_rate);
>>> @@ -94,13 +93,14 @@ static int set_audio_clock_rate(unsigned long
>>> epll_rate,
>>> sclk_spdif = clk_get(NULL, "sclk_spdif");
>>> if (IS_ERR(sclk_spdif)) {
>>> printk(KERN_ERR "%s: failed to get sclk_spdif\n", __func__);
>>> -return -ENOENT;
>>> +ret = PTR_ERR(sclk_spdif);
>>> +return ret;
>> Same as above.
>>
>>> }
>>> clk_set_rate(sclk_spdif, audio_rate);
>>> clk_put(sclk_spdif);
>>> -return 0;
>>> +return ret;
>>> }
>>> static int smdk_hw_params(struct snd_pcm_substream *substream,
>>>
>>
> Thanks ,I'll submit it again.
--
Tushar Behera
--
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[PATCH 1/4] ARM: EXYNOS: remove system mmu initialization from arch/arm/ tree
This removes System MMU initialization from arch/arm/mach-exynos/
to move them to DT and the exynos-iommu driver except gating clock
definitions.
Signed-off-by: KyongHo Cho
---
arch/arm/mach-exynos/Kconfig | 5 -
arch/arm/mach-exynos/Makefile | 1 -
arch/arm/mach-exynos/clock-exynos4.c | 41 +++--
arch/arm/mach-exynos/clock-exynos4210.c| 9 +-
arch/arm/mach-exynos/clock-exynos4212.c| 23 ++-
arch/arm/mach-exynos/clock-exynos5.c | 62 ---
arch/arm/mach-exynos/dev-sysmmu.c | 274 -
arch/arm/mach-exynos/include/mach/sysmmu.h | 66 ---
arch/arm/mach-exynos/mach-exynos4-dt.c | 34
arch/arm/mach-exynos/mach-exynos5-dt.c | 30
10 files changed, 137 insertions(+), 408 deletions(-)
delete mode 100644 arch/arm/mach-exynos/dev-sysmmu.c
delete mode 100644 arch/arm/mach-exynos/include/mach/sysmmu.h
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index bb3b09a..d5157d7 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -94,11 +94,6 @@ config EXYNOS4_SETUP_FIMD0
help
Common setup code for FIMD0.
-config EXYNOS_DEV_SYSMMU
- bool
- help
- Common setup code for SYSTEM MMU in EXYNOS platforms
-
config EXYNOS4_DEV_DWMCI
bool
help
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 1797dee..7460ba2 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -53,7 +53,6 @@ obj-$(CONFIG_EXYNOS4_DEV_AHCI)+= dev-ahci.o
obj-$(CONFIG_EXYNOS4_DEV_DWMCI)+= dev-dwmci.o
obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o
obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
-obj-$(CONFIG_EXYNOS_DEV_SYSMMU)+= dev-sysmmu.o
obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
diff --git a/arch/arm/mach-exynos/clock-exynos4.c
b/arch/arm/mach-exynos/clock-exynos4.c
index efead60..c81a0ca 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -24,7 +24,6 @@
#include
#include
-#include
#include "common.h"
#include "clock-exynos4.h"
@@ -709,53 +708,53 @@ static struct clk exynos4_init_clocks_off[] = {
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit= (1 << 14),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname= SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
+ .name = "sysmmu",
+ .devname= "exynos-sysmmu.0",
.enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit= (1 << 1),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname= SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
+ .name = "sysmmu",
+ .devname= "exynos-sysmmu.1",
.enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit= (1 << 2),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname= SYSMMU_CLOCK_DEVNAME(tv, 2),
+ .name = "sysmmu",
+ .devname= "exynos-sysmmu.2",
.enable = exynos4_clk_ip_tv_ctrl,
.ctrlbit= (1 << 4),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname= SYSMMU_CLOCK_DEVNAME(jpeg, 3),
+ .name = "sysmmu",
+ .devname= "exynos-sysmmu.3",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit= (1 << 11),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname= SYSMMU_CLOCK_DEVNAME(rot, 4),
+ .name = "sysmmu",
+ .devname= "exynos-sysmmu.4",
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit= (1 << 4),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname= SYSMMU_CLOCK_DEVNAME(fimc0, 5),
+ .name = "sysmmu",
+ .devname= "exynos-sysmmu.5",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit= (1 << 7),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname= SYSMMU_CLOCK_DEVNAME(fimc1, 6),
+ .name = "sysmmu",
+ .devname= "exynos-sysmmu.6",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit= (1 << 8),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname= SYSMMU_CLOCK_DEVNAME(fimc2, 7),
+ .name = "sysmmu",
+ .devname= "exynos-sysmmu.7"
[PATCH 4/4] iommu/exynos: enhancements of System MMU driver with DT
This commit enhances power management of System MMU and its client devices with the following changes: - Each System MMU device becomes the parent device of its client device while probe(). Thus, exynos-iommu driver must be initialized before client devices. - System MMU driver does not pm_runtime_get/put() by itself and runtime power gating is performed by client devices. - System is safe when suspend/resume without any care by client device drivers. In addition, System MMUs can be seperate into several groups that are belongs to a single client device like FIMC-IS block. If such blocks are controlled by a single device descriptor, all System MMUs in the blocks must be enabled/disabled by a single device descriptor. The problem is that clock gating and power gating may be not the same among all System MMUs in the blocks. Thus, System MMUs are grouped by clock gating and power gating and they are chained by parent-child relationships. exynos-iommu driver now also supports debugfs to identify the state of each System MMU. The last big change is to support DT. The desription of the properties of DT nodes are described in the source file. Signed-off-by: KyongHo Cho --- drivers/iommu/Kconfig| 17 +- drivers/iommu/exynos-iommu.c | 1420 +++--- 2 files changed, 1077 insertions(+), 360 deletions(-) diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index e39f9db..548fdf0 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -168,7 +168,7 @@ config TEGRA_IOMMU_SMMU config EXYNOS_IOMMU bool "Exynos IOMMU Support" - depends on ARCH_EXYNOS && EXYNOS_DEV_SYSMMU + depends on ARCH_EXYNOS select IOMMU_API help Support for the IOMMU(System MMU) of Samsung Exynos application @@ -178,6 +178,21 @@ config EXYNOS_IOMMU If unsure, say N here. +config EXYNOS_IOMMU_TLBINV_BY_ENTRY + bool "TLB invalidation in iommu_unmap() call" + depends on EXYNOS_IOMMU + default y + help + TLB must be invalidated whenever a mapping information is removed from + the page table and iommu_ops.unmap() is the proper place to invoke + TLB invalidation. Since iommu_ops.unmap() is called per a page + table entry, TLB invalidation can be invoked hundreds of times for + unmapping just one IO region that consists of hundreds of pages. + It is rather efficient not to invalidate TLB by entry but invalidate + the entire TLB. + Say n if your IO region mapper calls exynos_sysmmu_tlb_invalidate() + directly not to perform TLB invalidation by entry. + config EXYNOS_IOMMU_DEBUG bool "Debugging log for Exynos IOMMU" depends on EXYNOS_IOMMU diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 7fe44f8..acf6486 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -1,6 +1,6 @@ /* linux/drivers/iommu/exynos_iommu.c * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. * http://www.samsung.com * * This program is free software; you can redistribute it and/or modify @@ -12,24 +12,29 @@ #define DEBUG #endif +#include #include #include -#include #include #include #include #include #include -#include #include -#include #include #include +#include +#include +#include +#include +#include +#include +#include +#include #include -#include -#include +#define MODULE_NAME "exynos-sysmmu" /* We does not consider super section mapping (16MB) */ #define SECT_ORDER 20 @@ -80,6 +85,13 @@ #define CTRL_BLOCK 0x7 #define CTRL_DISABLE 0x0 +#define CFG_LRU0x1 +#define CFG_QOS(n) ((n & 0xF) << 7) +#define CFG_MASK 0x0050 /* Selecting bit 0-15, 20, 22 */ +#define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */ +#define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */ +#define CFG_SHAREABLE (1 << 12) /* System MMU 3.x only */ + #define REG_MMU_CTRL 0x000 #define REG_MMU_CFG0x004 #define REG_MMU_STATUS 0x008 @@ -96,10 +108,31 @@ #define REG_MMU_VERSION0x034 -#define REG_PB0_SADDR 0x04C -#define REG_PB0_EADDR 0x050 -#define REG_PB1_SADDR 0x054 -#define REG_PB1_EADDR 0x058 +#define MMU_MAJ_VER(reg) (reg >> 28) +#define MMU_MIN_VER(reg) ((reg >> 21) & 0x7F) + +#define MAX_NUM_PBUF 3 + +#define NUM_MINOR_OF_SYSMMU_V3 4 + +static void *sysmmu_placeholder; /* Inidcate if a device is System MMU */ + +#define is_sysmmu(sysmmu) (sysmmu->archdata.iommu == &sysmmu_placeholder) +#define has_sysmmu(dev) \ + (dev->parent && dev->archdata.iommu && is_sysmmu(dev->parent)) +#define for_each_sysmmu(dev, sysmmu) \ + for (s
[PATCH 0/4] iommu/exynos: Fixes and Enhancements of System MMU driver with DT
The current exynos-iommu(System MMU) driver does not work autonomously since it is lack of support for power management of peripheral blocks. For example, MFC device driver must ensure that its System MMU is disabled before MFC block is power-down not to invalidate IOTLB in the System MMU when I/O memory mapping is changed. Because A System MMU is resides in the same H/W block, access to control registers of System MMU while the H/W block is turned off must be prohibited. This set of changes solves the above problem with setting each System MMUs as the parent of the device which owns the System MMU to recieve the information when the device is turned off or turned on. Another big change to the driver is the support for devicetree. The bindings for System MMU is described in Documentation/devicetree/bindings/arm/samsung/system-mmu.txt In addition, this patchset also includes several bug fixes and enhancements of the current driver. Patch summary: [PATCH 1/4] ARM: EXYNOS: remove system mmu initialization from arch/arm/ tree [PATCH 2/4] ARM: EXYNOS: Add clk_ops for gating clocks of System MMU [PATCH 3/4] ARM: EXYNOS: add System MMU definition to DT [PATCH 4/4] iommu/exynos: enhancements of System MMU driver with DT Diffstats: .../devicetree/bindings/arm/samsung/system-mmu.txt | 42 + arch/arm/boot/dts/exynos4210.dtsi | 96 ++ arch/arm/boot/dts/exynos4x12.dtsi | 124 ++ arch/arm/boot/dts/exynos5250.dtsi | 152 ++- arch/arm/mach-exynos/Kconfig |5 - arch/arm/mach-exynos/Makefile |1 - arch/arm/mach-exynos/clock-exynos4.c | 41 +- arch/arm/mach-exynos/clock-exynos4210.c|9 +- arch/arm/mach-exynos/clock-exynos4212.c| 23 +- arch/arm/mach-exynos/clock-exynos5.c | 87 +- arch/arm/mach-exynos/dev-sysmmu.c | 274 arch/arm/mach-exynos/include/mach/sysmmu.h | 66 - arch/arm/mach-exynos/mach-exynos4-dt.c | 34 + arch/arm/mach-exynos/mach-exynos5-dt.c | 30 + drivers/iommu/Kconfig | 17 +- drivers/iommu/Makefile |2 +- drivers/iommu/exynos-iommu.c | 1420 +++- 17 files changed, 1652 insertions(+), 771 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/4] ARM: EXYNOS: Add clk_ops for gating clocks of System MMU
Touching some System MMU needs its master devices' clock to be enabled
before. This commit adds clk_ops.set_parent of gating clocks of System
MMU to ensure gating clocks of System MMU's mater devices are enabled
when enabling gating clocks of System MMU.
Signed-off-by: KyongHo Cho
---
arch/arm/mach-exynos/clock-exynos5.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c
b/arch/arm/mach-exynos/clock-exynos5.c
index 9e815ae..9dfb845 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -613,6 +613,16 @@ static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
};
+static int exynos5_gate_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ clk->parent = parent;
+ return 0;
+}
+
+static struct clk_ops exynos5_gate_clk_ops = {
+ .set_parent = exynos5_gate_clk_set_parent
+};
+
static struct clk exynos5_init_clocks_off[] = {
{
.name = "timers",
@@ -854,76 +864,91 @@ static struct clk exynos5_init_clocks_off[] = {
.name = "sysmmu",
.devname= "exynos-sysmmu.0",
.enable = &exynos5_clk_ip_mfc_ctrl,
+ .ops= &exynos5_gate_clk_ops,
.ctrlbit= (1 << 1),
}, {
.name = "sysmmu",
.devname= "exynos-sysmmu.1",
.enable = &exynos5_clk_ip_mfc_ctrl,
+ .ops= &exynos5_gate_clk_ops,
.ctrlbit= (1 << 2),
}, {
.name = "sysmmu",
.devname= "exynos-sysmmu.2",
.enable = &exynos5_clk_ip_disp1_ctrl,
+ .ops= &exynos5_gate_clk_ops,
.ctrlbit= (1 << 9)
}, {
.name = "sysmmu",
.devname= "exynos-sysmmu.3",
.enable = &exynos5_clk_ip_gen_ctrl,
+ .ops= &exynos5_gate_clk_ops,
.ctrlbit= (1 << 7),
}, {
.name = "sysmmu",
.devname= "exynos-sysmmu.4",
.enable = &exynos5_clk_ip_gen_ctrl,
+ .ops= &exynos5_gate_clk_ops,
.ctrlbit= (1 << 6)
}, {
.name = "sysmmu",
.devname= "exynos-sysmmu.5",
.enable = &exynos5_clk_ip_gscl_ctrl,
+ .ops= &exynos5_gate_clk_ops,
.ctrlbit= (1 << 7),
}, {
.name = "sysmmu",
.devname= "exynos-sysmmu.6",
.enable = &exynos5_clk_ip_gscl_ctrl,
+ .ops= &exynos5_gate_clk_ops,
.ctrlbit= (1 << 8),
}, {
.name = "sysmmu",
.devname= "exynos-sysmmu.7",
.enable = &exynos5_clk_ip_gscl_ctrl,
+ .ops= &exynos5_gate_clk_ops,
.ctrlbit= (1 << 9),
}, {
.name = "sysmmu",
.devname= "exynos-sysmmu.8",
.enable = &exynos5_clk_ip_gscl_ctrl,
+ .ops= &exynos5_gate_clk_ops,
.ctrlbit= (1 << 10),
}, {
.name = "sysmmu",
.devname= "exynos-sysmmu.9",
.enable = &exynos5_clk_ip_isp0_ctrl,
+ .ops= &exynos5_gate_clk_ops,
.ctrlbit= (0x3F << 8),
}, {
.name = "sysmmu",
.devname= "exynos-sysmmu.10",
.enable = &exynos5_clk_ip_isp1_ctrl,
+ .ops= &exynos5_gate_clk_ops,
.ctrlbit= (0xF << 4),
}, {
.name = "sysmmu",
.devname= "exynos-sysmmu.11",
.enable = &exynos5_clk_ip_disp1_ctrl,
+ .ops= &exynos5_gate_clk_ops,
.ctrlbit= (1 << 8)
}, {
.name = "sysmmu",
.devname= "exynos-sysmmu.12",
.enable = &exynos5_clk_ip_gscl_ctrl,
+ .ops= &exynos5_gate_clk_ops,
.ctrlbit= (1 << 11),
}, {
.name = "sysmmu",
.devname= "exynos-sysmmu.13",
.enable = &exynos5_clk_ip_gscl_ctrl,
+ .ops= &exynos5_gate_clk_ops,
.ctrlbit= (1 << 12),
}, {
.na
[PATCH 3/4] ARM: EXYNOS: add System MMU definition to DT
This commit adds System MMU nodes to DT of Exynos SoCs.
Signed-off-by: KyongHo Cho
---
.../devicetree/bindings/arm/samsung/system-mmu.txt | 42 ++
arch/arm/boot/dts/exynos4210.dtsi | 96 ++
arch/arm/boot/dts/exynos4x12.dtsi | 124 +
arch/arm/boot/dts/exynos5250.dtsi | 147 -
4 files changed, 407 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/samsung/system-mmu.txt
diff --git a/Documentation/devicetree/bindings/arm/samsung/system-mmu.txt
b/Documentation/devicetree/bindings/arm/samsung/system-mmu.txt
new file mode 100644
index 000..5115c39
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung/system-mmu.txt
@@ -0,0 +1,42 @@
+* Samsung Exynos System MMU
+
+Samsung's Exynos architecture includes System MMU that enables scattered
+physical chunks to be visible as a contiguous region to DMA-capabile peripheral
+devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
+
+System MMU is a sort of IOMMU and support identical translation table format to
+ARMv7 translation tables with minimum set of page properties including access
+permissions, shareability and security protection. In addition System MMU has
+another capabilities like L2 TLB or block-fetch buffers to minimize translation
+latency
+
+Each System MMU is included in the H/W block of a peripheral device. Thus, it
is
+important to specify that a System MMU is dedicated to which peripheral device
+before using System MMU. System initialization must specify the relationships
+between a System MMU and a peripheral device that owns the System MMU.
+
+Some device drivers may control several peripheral devices with a single device
+descriptor like MFC. Since handling a System MMU with IOMMU API requires a
+device descriptor that needs the System MMU, it is best to combine the System
+MMUs of the peripheral devices and control them with a single System MMU device
+descriptor. If it is unable to combine them into a single device descriptor,
+they can be linked with each other by the means of device.parent relationship.
+
+Required properties:
+- compatible: Should be "samsung,exynos-sysmmu".
+- reg: Tuples of base address and size of System MMU registers. The number of
+ tuples can be more than one if two or more System MMUs are controlled
+ by a single device descriptor.
+- interrupt-parent: The phandle of the interrupt controller of System MMU
+- interrupts: Tuples of numbers that indicates the interrupt source. The
+ number of elements in the tuple is dependent upon
+ 'interrupt-parent' property. The number of tuples in this property
+ must be the same with 'reg' property.
+
+Optional properties:
+- mmuname: Strings of the name of System MMU for debugging purpose. The number
+ of strings must be the same with the number of tuples in 'reg'
+ property.
+- mmu-master: phandle to the device node that owns System MMU. Only the device
+ that is specified whith this property can control System MMU with
+ IOMMU API.
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index 939f639..d7a7a06 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -71,4 +71,100 @@
reg = <0x100C 0x100>;
interrupts = <2 4>;
};
+
+ sysmmu-mfcL {
+ mmuname = "mfc_l";
+ reg = <0x1362 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <5 5>;
+ };
+
+ sysmmu-mfcR {
+ mmuname = "mfc_r";
+ reg = <0x1363 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <5 6>;
+ };
+
+ sysmmu-tv {
+ mmuname = "tv";
+ reg = <0x13E2 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <5 4>;
+ };
+
+ sysmmu-fimc0 {
+ mmuname = "fimc0";
+ reg = <0x11A2 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <4 2>;
+ };
+
+ sysmmu-fimc1 {
+ mmuname = "fimc1";
+ reg = <0x11A3 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <4 3>;
+ };
+
+ sysmmu-fimc2 {
+ mmuname = "fimc2";
+ reg = <0x11A4 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <4 4>;
+ };
+
+ sysmmu-fimc3 {
+
Re: [oselas] Mini2440 boot failure on kernel 3.7-rc1
On 11/13/2012 01:29 PM, Sylwester Nawrocki wrote:
> On 11/13/2012 08:54 AM, Brian Norris wrote:
>> On Mon, Nov 12, 2012 at 3:18 PM, Sylwester Nawrocki
>> Can you please list a full 8-byte string of id_data[]? This will be
>> very helpful. I know of at least one solution that will fix your
>> problem, but I need to know your full ID to help lay this issue to
>> rest for good.
>
> Indeed, I wish there was good hardware documentation, still it seems
> an exception rather than a rule for some hardware vendors...
>
> Here is my id_data[] dump:
>
> ec, f1, 00, 95, 40, ec, ec, f1
>
> Looks a bit strange, I hope you know how to handle this. :)
Well, sort of. I could add yet another quirk: that some "5-byte" IDs
have the manufacturer ID repeated twice (0xEC 0xEC). In fact, I just got
another report of a similar (stupid) ID.
But I have a more reasonable change. It's disappointing, but I'll have to
do a partial revert of my previous commits, dropping support for some of
the newest SLC in favor of not breaking the old. I'll have to try to get
in contact with Samsung if I'm ever going to support the newest stuff.
Please try my diff (below), on top of the patch from:
http://lists.infradead.org/pipermail/linux-mtd/2012-October/044356.html
> OK. BTW, is this comment in drivers/mtd/nand_base.c
>
> /*
> * nand_id_has_period - Check if an ID string has a given wraparound
> period
> ...
> * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
> * period of 2). This is a helper function for nand_id_len(). Returns
> non-zero
> ...
>
> correct ? Shouldn't it be "has a period of 3" ? Since there are 3 different
> values and then it repeats starting with 0x20 ?
Yes, good eye. I also noticed my typo when re-reviewing this code just now.
I'll fix this for the 3.8 cycle.
Brian
---
drivers/mtd/nand/nand_base.c |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index d5ece6e..1a03b7f 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2990,6 +2990,7 @@ static void nand_decode_ext_id(struct mtd_info *mtd,
struct nand_chip *chip,
* ID to decide what to do.
*/
if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
+ (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
id_data[5] != 0x00) {
/* Calc pagesize */
mtd->writesize = 2048 << (extid & 0x03);
--
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