남영민 wrote:
This patch enables RTC on Exynos5440 by default.
RTC is a basic feature of Exynos5440.
But it was disabled by issue that comes from Exynos5250.
(commit id: 522ccdb6fd0e9689fbdc005ce95a42d70ec81629)
That issue only applies to Exynos5250 not Exynos5440. So, there is
no issue
On 17 May 2013 15:40, Naveen Krishna Chatradhi ch.nav...@samsung.com wrote:
Adds support for High Speed I2C driver found in Exynos5 and
later SoCs from Samsung.
Driver only supports Device Tree method.
Changes since v1:
1. Added FIFO functionality
2. Added High speed mode functionality
Doug Anderson wrote:
Jingoo,
On Sat, May 11, 2013 at 1:09 AM, Jingoo Han jg1@samsung.com wrote:
Add pin state information for DP HPD support that requires
pin configuration support using pinctrl interface.
Signed-off-by: Jingoo Han jg1@samsung.com
---
Tested on Exynos5250
Doug Anderson wrote:
Jingoo,
On Sat, May 11, 2013 at 12:43 AM, Jingoo Han jg1@samsung.com wrote:
The exynos5-dp node needs a clock specified using the common clock
framework.
Signed-off-by: Jingoo Han jg1@samsung.com
---
Tested on Exynos5250
On Saturday, June 08, 2013 2:43 AM, Arnd Bergmann wrote:
On Friday 07 June 2013, Jason Gunthorpe wrote:
Sounds fair to me.
But when we talk about multiple domains we don't mean a disjoint range
bus bus numbers, as your other email shows:
00:00.0 PCI bridge: Samsung Electronics Co Ltd
Kukjin Kim wrote:
Mike Turquette wrote:
Quoting Sachin Kamat (2013-04-18 04:15:15)
Add G2D clocks for Exynos4x12 SoC and sclk_fimg2d required by G2D
IP.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
Cc: Thomas Abraham thomas.abra...@linaro.org
Cc: Mike Turquette
Hi Kukjin,
On 29 April 2013 22:30, Mike Turquette mturque...@linaro.org wrote:
Quoting Sachin Kamat (2013-04-21 20:55:46)
Added clock entries for thermal management unit (TMU) for
Exynos4 SoCs.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
Cc: Thomas Abraham thomas.abra...@linaro.org
Tushar Behera wrote:
On 06/06/2013 04:31 PM, Chander Kashyap wrote:
Extend the soft reset support for Exynos5420 SoC.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
---
arch/arm/mach-exynos/common.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
This patch renames check_timing to check_mode and removes the
unnecessary conversion of drm_display_mode to/from fb_videomode in
the hdmi driver.
v4:
1) Changed the commit message to add information related to renaming
the callbacks to check_mode.
2) Changed debug message to print 1/0 for
Hi,
On 6 June 2013 17:05, Girish KS girishks2...@gmail.com wrote:
On Thu, Jun 6, 2013 at 4:31 PM, Chander Kashyap
chander.kash...@linaro.org wrote:
The serial port used in Exynos5420 is similar to the serial ports used
in the other Exynos SoC. Hence, extend the serial driver support for
Hi Mark,
On 6 June 2013 22:24, Mark Rutland mark.rutl...@arm.com wrote:
On Thu, Jun 06, 2013 at 12:01:18PM +0100, Chander Kashyap wrote:
Instead of having to specify the number for CPUs in Exynos5250 in platsmp.c
file, let the number of CPUs be determined by having this information listed
in
On 8 June 2013 16:46, Tomasz Figa tomasz.f...@gmail.com wrote:
On Thursday 06 of June 2013 16:31:18 Chander Kashyap wrote:
Instead of having to specify the number for CPUs in Exynos5250 in
platsmp.c file, let the number of CPUs be determined by having this
information listed in Exynos5250
Tomasz Figa wrote:
Hi Kukjin,
On Tuesday 04 of June 2013 18:37:54 Kukjin Kim wrote:
Tomasz Figa wrote:
Hi Sylwester, Kukjin,
Hi,
On Saturday 01 of June 2013 10:16:52 Sylwester Nawrocki wrote:
Hi Tomasz,
On 05/19/2013 12:37 AM, Tomasz Figa wrote:
This series is
Add clock changes for hdmi subsystem for exynos5250 SoC. These
include addition of new clocks like mout_hdmi and smmu_tv, associating
ID to clk_hdmiphy and some essential corrections.
This set is based on kukjin's for-next branch at
From: Arun Kumar K arun...@samsung.com
This patch corrects the HDMI clock number given wrongly
in the documentation.
Signed-off-by: Arun Kumar K arun...@samsung.com
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
Documentation/devicetree/bindings/clock/exynos5250-clock.txt |2 +-
1
hdmi driver needs to change the parent of hdmi clock
frequently between pixel clock and hdmiphy clock. hdmiphy is
not stable after power on and for a short interval while changing
the phy configuration. For this duration pixel clock is used to
clock hdmi.
This patch is exposing the mux for
hdmi driver needs hdmiphy clock which is one of the parent
for hdmi mux clock. This is required while changing the parent
of mux clock.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
Documentation/devicetree/bindings/clock/exynos5250-clock.txt |1 +
Adding sysmmu clock for tv for exynos5250 SoC. It also
adds aclk200_disp1 mux which is the actual parent of the
disp1 block (contains hdmi, mixer, sysmmu_tv).
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
Documentation/devicetree/bindings/clock/exynos5250-clock.txt |1 +
This patch is already posted at
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg18331.html
and
Reviewed-by: Doug Anderson diand...@chromium.org
On Mon, Jun 10, 2013 at 4:30 PM, Rahul Sharma rahul.sha...@samsung.com wrote:
From: Arun Kumar K arun...@samsung.com
This patch
Hi Chander,
[snip]
+ sclk_uart3 131
+ sclk_mmc0132
+ sclk_mmc1132
+ sclk_mmc2133
above 2 numbers got repeated. Doug had found this in chromium tree and
fixed it. [ https://gerrit.chromium.org/gerrit/#/c/56626/]
Pls fix the typo in next
Hi Kukjin,
On Thursday 06 of June 2013 12:49:23 Kukjin Kim wrote:
As we discussed in mailing list, non-DT for EXYNOS SoCs will not be
supported from v3.11. This patch removes regarding files for non-DT
including board files and defconfig.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc:
On 06/10/13 21:00, Tomasz Figa wrote:
Hi Kukjin,
On Thursday 06 of June 2013 12:49:23 Kukjin Kim wrote:
As we discussed in mailing list, non-DT for EXYNOS SoCs will not be
supported from v3.11. This patch removes regarding files for non-DT
including board files and defconfig.
Cc: Sylwester
Hi Naveen,
+Optional properties:
+ - samsung,hs-mode: Mode of operation, High speed or Fast speed mode. If not
+specified, default value is 0.
This was probably overlooked from my last review: Why can't you simply
enable hs-mode when clock-frequency is 1MBit?
+Example:
+
Hi,
On Friday 17 of May 2013 18:24:29 Tomasz Figa wrote:
This patch makes legacy code on suspend/resume path being executed
conditionally, on non-DT platforms only, to fix suspend/resume of
DT-enabled systems, for which the code is inappropriate.
Signed-off-by: Tomasz Figa
On Monday 10 June 2013, Jingoo Han wrote:
On Saturday, June 08, 2013 2:43 AM, Arnd Bergmann wrote:
For multiple domains, how can I fix the DT properties?
Domains are a Linux concept, you have to pick a new domain number for each
struct hw_pci you register.
Current DT properties are as below:
On 05/27/2013 04:56 PM, Sylwester Nawrocki wrote:
If the device is already in a runtime PM enabled state
pm_runtime_get_sync() will return 1, so a test for negative
value should be used to check for errors.
Without this patch there are seen errors like:
[8.54] s3c64xx-spi
On Mon, Jun 10, 2013 at 4:45 PM, Tomasz Figa t.f...@samsung.com wrote:
On Friday 17 of May 2013 18:24:29 Tomasz Figa wrote:
This patch makes legacy code on suspend/resume path being executed
conditionally, on non-DT platforms only, to fix suspend/resume of
DT-enabled systems, for which the
If the device is already in a runtime PM enabled state
pm_runtime_get_sync() will return 1, so a test for negative
value should be used to check for errors.
Without this patch there are seen errors like:
[8.54] s3c64xx-spi 1393.spi: Failed to enable device: 1
[8.545000]
On Mon, Jun 10, 2013 at 06:22:26PM +0200, Sylwester Nawrocki wrote:
If the device is already in a runtime PM enabled state
pm_runtime_get_sync() will return 1, so a test for negative
value should be used to check for errors.
Applied, thanks.
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Hi Kukjin,
On Monday 10 of June 2013 21:12:48 Kukjin Kim wrote:
On 06/10/13 21:00, Tomasz Figa wrote:
Hi Kukjin,
On Thursday 06 of June 2013 12:49:23 Kukjin Kim wrote:
As we discussed in mailing list, non-DT for EXYNOS SoCs will not be
supported from v3.11. This patch removes
On Monday 10 of June 2013 09:40:43 Tushar Behera wrote:
On 06/08/2013 04:16 PM, Tomasz Figa wrote:
Hi Tushar, Sachin,
On Friday 07 of June 2013 16:37:13 Tushar Behera wrote:
From: Sachin Kamat sachin.ka...@linaro.org
Adds pinctrl entries required by FIMD.
Signed-off-by: Sachin
On Monday 10 of June 2013 09:44:14 Tushar Behera wrote:
On 06/08/2013 04:19 PM, Tomasz Figa wrote:
On Friday 07 of June 2013 16:37:14 Tushar Behera wrote:
From: Sachin Kamat sachin.ka...@linaro.org
Added FIMD and display timing node to Origen4210 board.
Signed-off-by: Sachin Kamat
On Monday 10 of June 2013 09:13:11 Tushar Behera wrote:
On 06/08/2013 05:20 PM, Tomasz Figa wrote:
On Thursday 06 of June 2013 16:52:28 Tushar Behera wrote:
cpufreq driver for EXYNOS4 based SoCs are not platform drivers, hence
we cannot currently pass the clock names through a device tree
Quoting Kukjin Kim (2013-06-05 04:51:29)
Doug Anderson wrote:
The KDIV value is often listed as unsigned but it needs to be treated
as a 16-bit signed value when using it in calculations. Fix our rate
recalculation to do this correctly.
Before doing this, I tried setting EPLL on
On 5 June 2013 17:44, Kukjin Kim kgene@samsung.com wrote:
Sachin Kamat wrote:
These symbols are used only in this file and hence should be
static.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
drivers/clk/samsung/clk-exynos4.c | 26 ++
1 file
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