[PATCH v7 01/13] [media] exynos5-is: Adding media device driver for exynos5
From: Shaik Ameer Basha shaik.am...@samsung.com
This patch adds support for media device for EXYNOS5 SoCs.
The current media device supports the following ips to connect
through the media controller framework.
* MIPI-CSIS
Support interconnection(subdev interface) between devices
* FIMC-LITE
Support capture interface from device(Sensor, MIPI-CSIS) to memory
Support interconnection(subdev interface) between devices
* FIMC-IS
Camera post-processing IP having multiple sub-nodes.
G-Scaler will be added later to the current media device.
The media device creates two kinds of pipelines for connecting
the above mentioned IPs.
The pipeline0 is uses Sensor, MIPI-CSIS and FIMC-LITE which captures
image data and dumps to memory.
Pipeline1 uses FIMC-IS components for doing post-processing
operations on the captured image and give scaled YUV output.
Pipeline0
++ +---+ +---+ ++
| Sensor | -- | MIPI-CSIS | -- | FIMC-LITE | -- | Memory |
++ +---+ +---+ ++
Pipeline1
++ ++ +---+ +---+
| Memory | -- | ISP | -- |SCC| -- |SCP|
++ ++ +---+ +---+
Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com
Signed-off-by: Arun Kumar K arun...@samsung.com
---
.../bindings/media/exynos5250-camera.txt | 126 ++
drivers/media/platform/exynos5-is/exynos5-mdev.c | 1210
drivers/media/platform/exynos5-is/exynos5-mdev.h | 126 ++
3 files changed, 1462 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/exynos5250-camera.txt
create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.c
create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.h
diff --git a/Documentation/devicetree/bindings/media/exynos5250-camera.txt
b/Documentation/devicetree/bindings/media/exynos5250-camera.txt
new file mode 100644
index 000..09420ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/exynos5250-camera.txt
@@ -0,0 +1,126 @@
+Samsung EXYNOS5 SoC Camera Subsystem
+
+
+The Exynos5 SoC Camera subsystem comprises of multiple sub-devices
+represented by separate device tree nodes. Currently this includes: FIMC-LITE,
+MIPI CSIS and FIMC-IS.
+
+The sub-device nodes are referenced using phandles in the common 'camera' node
+which also includes common properties of the whole subsystem not really
+specific to any single sub-device, like common camera port pins or the common
+camera bus clocks.
+
+Common 'camera' node
+
+
+Required properties:
+
+- compatible : must be samsung,exynos5250-fimc
+- clocks : list of clock specifiers, corresponding to entries in
+ the clock-names property
+- clock-names : must contain sclk_bayer entry
+- samsung,csis : list of phandles to the mipi-csis device nodes
+- samsung,fimc-lite: list of phandles to the fimc-lite device nodes
+- samsung,fimc-is : phandle to the fimc-is device node
+
+The pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt must be used
+to define a required pinctrl state named default.
+
+'parallel-ports' node
+-
+
+This node should contain child 'port' nodes specifying active parallel video
+input ports. It includes camera A, camera B and RGB bay inputs.
+'reg' property in the port nodes specifies the input type:
+ 1 - parallel camport A
+ 2 - parallel camport B
+ 5 - RGB camera bay
+
+3, 4 are for MIPI CSI-2 bus and are already described in samsung-mipi-csis.txt
+
+Image sensor nodes
+--
+
+The sensor device nodes should be added to their control bus controller (e.g.
+I2C0) nodes and linked to a port node in the csis or the parallel-ports node,
+using the common video interfaces bindings, defined in video-interfaces.txt.
+
+Example:
+
+ aliases {
+ fimc-lite0 = fimc_lite_0
+ };
+
+ /* Parallel bus IF sensor */
+ i2c_0: i2c@1386 {
+ s5k6aa: sensor@3c {
+ compatible = samsung,s5k6aafx;
+ reg = 0x3c;
+ vddio-supply = ...;
+
+ clock-frequency = 2400;
+ clocks = ...;
+ clock-names = mclk;
+
+ port {
+ s5k6aa_ep: endpoint {
+ remote-endpoint = fimc0_ep;
+ bus-width = 8;
+ hsync-active = 0;
+ vsync-active = 1;
+ pclk-sample = 1;
+ };
+ };
+ };
+ };
+
+ /* MIPI CSI-2 bus IF sensor */
+ s5c73m3: sensor@1a {
+ compatible =
[PATCH v7 06/13] [media] exynos5-fimc-is: Add isp subdev
fimc-is driver takes video data input from the ISP video node
which is added in this patch. This node accepts Bayer input
buffers which is given from the IS sensors.
Signed-off-by: Arun Kumar K arun...@samsung.com
Signed-off-by: Kilyeon Im kilyeon...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
drivers/media/platform/exynos5-is/fimc-is-isp.c | 534 +++
drivers/media/platform/exynos5-is/fimc-is-isp.h | 90
2 files changed, 624 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-isp.c
b/drivers/media/platform/exynos5-is/fimc-is-isp.c
new file mode 100644
index 000..882c291
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-isp.c
@@ -0,0 +1,534 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K arun...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include media/v4l2-ioctl.h
+#include media/videobuf2-dma-contig.h
+
+#include fimc-is.h
+
+#define ISP_DRV_NAME fimc-is-isp
+
+static const struct fimc_is_fmt formats[] = {
+ {
+ .name = Bayer GR-BG 8bits,
+ .fourcc = V4L2_PIX_FMT_SGRBG8,
+ .depth = { 8 },
+ .num_planes = 1,
+ },
+ {
+ .name = Bayer GR-BG 10bits,
+ .fourcc = V4L2_PIX_FMT_SGRBG10,
+ .depth = { 16 },
+ .num_planes = 1,
+ },
+ {
+ .name = Bayer GR-BG 12bits,
+ .fourcc = V4L2_PIX_FMT_SGRBG12,
+ .depth = { 16 },
+ .num_planes = 1,
+ },
+};
+#define NUM_FORMATS ARRAY_SIZE(formats)
+
+static const struct fimc_is_fmt *find_format(struct v4l2_format *f)
+{
+ unsigned int i;
+
+ for (i = 0; i NUM_FORMATS; i++)
+ if (formats[i].fourcc == f-fmt.pix_mp.pixelformat)
+ return formats[i];
+ return NULL;
+}
+
+static int isp_video_output_start_streaming(struct vb2_queue *vq,
+ unsigned int count)
+{
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+
+ set_bit(STATE_RUNNING, isp-output_state);
+ return 0;
+}
+
+static int isp_video_output_stop_streaming(struct vb2_queue *vq)
+{
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+ struct fimc_is_buf *buf;
+
+ /* Release unused buffers */
+ while (!list_empty(isp-wait_queue)) {
+ buf = fimc_is_isp_wait_queue_get(isp);
+ vb2_buffer_done(buf-vb, VB2_BUF_STATE_ERROR);
+ }
+ while (!list_empty(isp-run_queue)) {
+ buf = fimc_is_isp_run_queue_get(isp);
+ vb2_buffer_done(buf-vb, VB2_BUF_STATE_ERROR);
+ }
+
+ clear_bit(STATE_RUNNING, isp-output_state);
+ return 0;
+}
+
+static int isp_video_output_queue_setup(struct vb2_queue *vq,
+ const struct v4l2_format *pfmt,
+ unsigned int *num_buffers, unsigned int *num_planes,
+ unsigned int sizes[], void *allocators[])
+{
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+ const struct fimc_is_fmt *fmt = isp-fmt;
+ unsigned int wh, i;
+
+ if (!fmt)
+ return -EINVAL;
+
+ *num_planes = fmt-num_planes;
+ wh = isp-width * isp-height;
+
+ for (i = 0; i *num_planes; i++) {
+ allocators[i] = isp-alloc_ctx;
+ sizes[i] = (wh * fmt-depth[i]) / 8;
+ }
+ return 0;
+}
+
+static int isp_video_output_buffer_init(struct vb2_buffer *vb)
+{
+ struct fimc_is_buf *buf = container_of(vb, struct fimc_is_buf, vb);
+
+ buf-paddr[0] = vb2_dma_contig_plane_dma_addr(vb, 0);
+ return 0;
+}
+
+static int isp_video_output_buffer_prepare(struct vb2_buffer *vb)
+{
+ struct vb2_queue *vq = vb-vb2_queue;
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+ unsigned long size;
+
+ size = (isp-width * isp-height * isp-fmt-depth[0]) / 8;
+ if (vb2_plane_size(vb, 0) size) {
+ v4l2_err(isp-subdev, User buffer too small (%ld %ld)\n,
+vb2_plane_size(vb, 0), size);
+ return -EINVAL;
+ }
+ vb2_set_plane_payload(vb, 0, size);
+
+ return 0;
+}
+
+static void isp_video_output_buffer_queue(struct vb2_buffer *vb)
+{
+ struct vb2_queue *vq = vb-vb2_queue;
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+ struct fimc_is_buf *buf = container_of(vb, struct fimc_is_buf, vb);
+
+
[PATCH v7 02/13] [media] exynos5-fimc-is: Add Exynos5 FIMC-IS device tree bindings documentation
The patch adds the DT binding documentation for Samsung Exynos5 SoC series imaging subsystem (FIMC-IS). Signed-off-by: Arun Kumar K arun...@samsung.com Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com --- .../devicetree/bindings/media/exynos5-fimc-is.txt | 46 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/exynos5-fimc-is.txt diff --git a/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt new file mode 100644 index 000..5611401 --- /dev/null +++ b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt @@ -0,0 +1,46 @@ +Samsung EXYNOS5 SoC series Imaging Subsystem (FIMC-IS) +-- + +The camera subsystem on Samsung Exynos5 SoC has some changes relative +to previous SoC versions. Exynos5 has almost similar MIPI-CSIS and +FIMC-LITE IPs but has a much improved version of FIMC-IS which can +handle sensor controls and camera post-processing operations. The +Exynos5 FIMC-IS has a dedicated ARM Cortex A5 processor, many +post-processing blocks (ISP, DRC, FD, ODC, DIS, 3DNR) and two +dedicated scalers (SCC and SCP). + +fimc-is node + + +Required properties: + +- compatible: must be samsung,exynos5250-fimc-is +- reg : physical base address and size of the memory mapped + registers +- interrupt-parent : parent interrupt controller +- interrupts: fimc-is interrupt to the parent interrupt controller +- clocks: list of clock specifiers, corresponding to entries in + clock-names property +- clock-names : must contain isp, mcu_isp, isp_div0, isp_div1, + isp_divmpwm, mcu_isp_div0, mcu_isp_div1 entries, + matching entries in the clocks property +- samsung,pmu : phandle to the Power Management Unit (PMU) node + +i2c-isp (ISP I2C bus controller) nodes +-- + +Required properties: + +- compatible : should be samsung,exynos4212-i2c-isp for Exynos4212, + Exynos4412 and Exynos5250 SoCs +- reg : physical base address and length of the registers set +- clocks : must contain gate clock specifier for this controller +- clock-names : must contain i2c_isp entry + +For the i2c-isp node, it is required to specify a pinctrl state named default, +according to the pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt. + +Device tree nodes of the image sensors controlled directly by the FIMC-IS +firmware must be child nodes of their corresponding ISP I2C bus controller node. +The data link of these image sensors must be specified using the common video +interfaces bindings, defined in video-interfaces.txt. -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 03/13] [media] exynos5-fimc-is: Add driver core files
This driver is for the FIMC-IS IP available in Samsung Exynos5
SoC onwards. This patch adds the core files for the new driver.
Signed-off-by: Arun Kumar K arun...@samsung.com
Signed-off-by: Kilyeon Im kilyeon...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
drivers/media/platform/exynos5-is/fimc-is-core.c | 413 ++
drivers/media/platform/exynos5-is/fimc-is-core.h | 132 +++
2 files changed, 545 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-core.c
b/drivers/media/platform/exynos5-is/fimc-is-core.c
new file mode 100644
index 000..6910581
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-core.c
@@ -0,0 +1,413 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K arun...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/bug.h
+#include linux/ctype.h
+#include linux/device.h
+#include linux/debugfs.h
+#include linux/delay.h
+#include linux/errno.h
+#include linux/err.h
+#include linux/firmware.h
+#include linux/fs.h
+#include linux/gpio.h
+#include linux/interrupt.h
+#include linux/kernel.h
+#include linux/list.h
+#include linux/module.h
+#include linux/of.h
+#include linux/of_gpio.h
+#include linux/of_address.h
+#include linux/of_platform.h
+#include linux/of_irq.h
+#include linux/pinctrl/consumer.h
+#include linux/platform_device.h
+#include linux/pm_runtime.h
+#include linux/slab.h
+#include linux/types.h
+#include linux/videodev2.h
+
+#include media/v4l2-device.h
+#include media/v4l2-ioctl.h
+#include media/v4l2-mem2mem.h
+#include media/v4l2-of.h
+#include media/videobuf2-core.h
+#include media/videobuf2-dma-contig.h
+
+#include fimc-is.h
+#include fimc-is-i2c.h
+
+#define CLK_MCU_ISP_DIV0_FREQ (200 * 100)
+#define CLK_MCU_ISP_DIV1_FREQ (100 * 100)
+#define CLK_ISP_DIV0_FREQ (134 * 100)
+#define CLK_ISP_DIV1_FREQ (68 * 100)
+#define CLK_ISP_DIVMPWM_FREQ (34 * 100)
+
+static const char * const fimc_is_clock_name[] = {
+ [IS_CLK_ISP]= isp,
+ [IS_CLK_MCU_ISP]= mcu_isp,
+ [IS_CLK_ISP_DIV0] = isp_div0,
+ [IS_CLK_ISP_DIV1] = isp_div1,
+ [IS_CLK_ISP_DIVMPWM]= isp_divmpwm,
+ [IS_CLK_MCU_ISP_DIV0] = mcu_isp_div0,
+ [IS_CLK_MCU_ISP_DIV1] = mcu_isp_div1,
+};
+
+static void fimc_is_put_clocks(struct fimc_is *is)
+{
+ int i;
+
+ for (i = 0; i IS_CLK_MAX_NUM; i++) {
+ if (IS_ERR(is-clock[i]))
+ continue;
+ clk_unprepare(is-clock[i]);
+ clk_put(is-clock[i]);
+ is-clock[i] = ERR_PTR(-EINVAL);
+ }
+}
+
+static int fimc_is_get_clocks(struct fimc_is *is)
+{
+ struct device *dev = is-pdev-dev;
+ int i, ret;
+
+ for (i = 0; i IS_CLK_MAX_NUM; i++) {
+ is-clock[i] = clk_get(dev, fimc_is_clock_name[i]);
+ if (IS_ERR(is-clock[i]))
+ goto err;
+ ret = clk_prepare(is-clock[i]);
+ if (ret 0) {
+ clk_put(is-clock[i]);
+ is-clock[i] = ERR_PTR(-EINVAL);
+ goto err;
+ }
+ }
+ return 0;
+err:
+ fimc_is_put_clocks(is);
+ pr_err(Failed to get clock: %s\n, fimc_is_clock_name[i]);
+ return -ENXIO;
+}
+
+static int fimc_is_configure_clocks(struct fimc_is *is)
+{
+ int i, ret;
+
+ for (i = 0; i IS_CLK_MAX_NUM; i++)
+ is-clock[i] = ERR_PTR(-EINVAL);
+
+ ret = fimc_is_get_clocks(is);
+ if (ret)
+ return ret;
+
+ /* Set rates */
+ ret = clk_set_rate(is-clock[IS_CLK_MCU_ISP_DIV0],
+ CLK_MCU_ISP_DIV0_FREQ);
+ if (ret)
+ return ret;
+ ret = clk_set_rate(is-clock[IS_CLK_MCU_ISP_DIV1],
+ CLK_MCU_ISP_DIV1_FREQ);
+ if (ret)
+ return ret;
+ ret = clk_set_rate(is-clock[IS_CLK_ISP_DIV0], CLK_ISP_DIV0_FREQ);
+ if (ret)
+ return ret;
+ ret = clk_set_rate(is-clock[IS_CLK_ISP_DIV1], CLK_ISP_DIV1_FREQ);
+ if (ret)
+ return ret;
+ ret = clk_set_rate(is-clock[IS_CLK_ISP_DIVMPWM],
+ CLK_ISP_DIVMPWM_FREQ);
+ return ret;
+}
+
+static void fimc_is_pipelines_destroy(struct fimc_is *is)
+{
+ int i;
+
+ for (i = 0; i is-drvdata-num_instances; i++)
+ fimc_is_pipeline_destroy(is-pipeline[i]);
+}
+
+static int fimc_is_parse_sensor_config(struct fimc_is *is, unsigned int index,
+
[PATCH v7 05/13] [media] exynos5-fimc-is: Add register definition and context header
This patch adds the register definition file for the fimc-is driver and also the header file containing the main context for the driver. Signed-off-by: Arun Kumar K arun...@samsung.com Signed-off-by: Kilyeon Im kilyeon...@samsung.com Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com --- drivers/media/platform/exynos5-is/fimc-is-regs.h | 105 ++ drivers/media/platform/exynos5-is/fimc-is.h | 160 ++ 2 files changed, 265 insertions(+) create mode 100644 drivers/media/platform/exynos5-is/fimc-is-regs.h create mode 100644 drivers/media/platform/exynos5-is/fimc-is.h diff --git a/drivers/media/platform/exynos5-is/fimc-is-regs.h b/drivers/media/platform/exynos5-is/fimc-is-regs.h new file mode 100644 index 000..06aa466 --- /dev/null +++ b/drivers/media/platform/exynos5-is/fimc-is-regs.h @@ -0,0 +1,105 @@ +/* + * Samsung Exynos5 SoC series FIMC-IS driver + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd + * Arun Kumar K arun...@samsung.com + * Kil-yeon Lim kilyeon...@samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef FIMC_IS_REGS_H +#define FIMC_IS_REGS_H + +/* WDT_ISP register */ +#define WDT0x0017 +/* MCUCTL register */ +#define MCUCTL 0x0018 +/* MCU Controller Register */ +#define MCUCTLR(MCUCTL+0x00) +#define MCUCTLR_AXI_ISPX_AWCACHE(x)((x) 16) +#define MCUCTLR_AXI_ISPX_ARCACHE(x)((x) 12) +#define MCUCTLR_MSWRST (1 0) +/* Boot Base OFfset Address Register */ +#define BBOAR (MCUCTL+0x04) +#define BBOAR_BBOA(x) ((x) 0) + +/* Interrupt Generation Register 0 from Host CPU to VIC */ +#define INTGR0 (MCUCTL+0x08) +#define INTGR0_INTGC(n)(1 ((n) + 16)) +#define INTGR0_INTGD(n)(1 (n)) + +/* Interrupt Clear Register 0 from Host CPU to VIC */ +#define INTCR0 (MCUCTL+0x0c) +#define INTCR0_INTCC(n)(1 ((n) + 16)) +#define INTCR0_INTCD(n)(1 (n)) + +/* Interrupt Mask Register 0 from Host CPU to VIC */ +#define INTMR0 (MCUCTL+0x10) +#define INTMR0_INTMC(n)(1 ((n) + 16)) +#define INTMR0_INTMD(n)(1 (n)) + +/* Interrupt Status Register 0 from Host CPU to VIC */ +#define INTSR0 (MCUCTL+0x14) +#define INTSR0_GET_INTSD(n, x) (((x) (n)) 0x1) +#define INTSR0_GET_INTSC(n, x) (((x) ((n) + 16)) 0x1) + +/* Interrupt Mask Status Register 0 from Host CPU to VIC */ +#define INTMSR0(MCUCTL+0x18) +#define INTMSR0_GET_INTMSD(n, x) (((x) (n)) 0x1) +#define INTMSR0_GET_INTMSC(n, x) (((x) ((n) + 16)) 0x1) + +/* Interrupt Generation Register 1 from ISP CPU to Host IC */ +#define INTGR1 (MCUCTL+0x1c) +#define INTGR1_INTGC(n)(1 (n)) + +/* Interrupt Clear Register 1 from ISP CPU to Host IC */ +#define INTCR1 (MCUCTL+0x20) +#define INTCR1_INTCC(n)(1 (n)) + +/* Interrupt Mask Register 1 from ISP CPU to Host IC */ +#define INTMR1 (MCUCTL+0x24) +#define INTMR1_INTMC(n)(1 (n)) + +/* Interrupt Status Register 1 from ISP CPU to Host IC */ +#define INTSR1 (MCUCTL+0x28) +/* Interrupt Mask Status Register 1 from ISP CPU to Host IC */ +#define INTMSR1(MCUCTL+0x2c) +/* Interrupt Clear Register 2 from ISP BLK's interrupts to Host IC */ +#define INTCR2 (MCUCTL+0x30) +#define INTCR2_INTCC(n)(1 (n)) + +/* Interrupt Mask Register 2 from ISP BLK's interrupts to Host IC */ +#define INTMR2 (MCUCTL+0x34) +#define INTMR2_INTMCIS(n) (1 (n)) + +/* Interrupt Status Register 2 from ISP BLK's interrupts to Host IC */ +#define INTSR2 (MCUCTL+0x38) +/* Interrupt Mask Status Register 2 from ISP BLK's interrupts to Host IC */ +#define INTMSR2(MCUCTL+0x3c) +/* General Purpose Output Control Register (0~17) */ +#define GPOCTLR(MCUCTL+0x40) +#define GPOCTLR_GPOG(n, x) ((x) (n)) + +/* General Purpose Pad Output Enable Register (0~17) */ +#define GPOENCTLR (MCUCTL+0x44) +#define GPOENCTLR_GPOEN0(n, x) ((x) (n)) + +/* General Purpose Input Control Register (0~17) */ +#define GPICTLR(MCUCTL+0x48) + +/* IS Shared Registers between ISP CPU and HOST CPU */ +#define ISSR(n)(MCUCTL + 0x80 + (n)) + +/* PMU for FIMC-IS*/ +#define
[PATCH v7 07/13] [media] exynos5-fimc-is: Add scaler subdev
FIMC-IS has two hardware scalers named as scaler-codec and
scaler-preview. This patch adds the common code handling the
video nodes and subdevs of both the scalers.
Signed-off-by: Arun Kumar K arun...@samsung.com
Signed-off-by: Kilyeon Im kilyeon...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
drivers/media/platform/exynos5-is/fimc-is-scaler.c | 472
drivers/media/platform/exynos5-is/fimc-is-scaler.h | 106 +
2 files changed, 578 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-scaler.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-scaler.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-scaler.c
b/drivers/media/platform/exynos5-is/fimc-is-scaler.c
new file mode 100644
index 000..82ba867
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-scaler.c
@@ -0,0 +1,472 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K arun...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include media/v4l2-ioctl.h
+#include media/videobuf2-dma-contig.h
+
+#include fimc-is.h
+
+#define IS_SCALER_DRV_NAME fimc-is-scaler
+
+static const struct fimc_is_fmt formats[] = {
+ {
+ .name = YUV 4:2:0 3p MultiPlanar,
+ .fourcc = V4L2_PIX_FMT_YUV420M,
+ .depth = {8, 2, 2},
+ .num_planes = 3,
+ },
+ {
+ .name = YUV 4:2:0 2p MultiPlanar,
+ .fourcc = V4L2_PIX_FMT_NV12M,
+ .depth = {8, 4},
+ .num_planes = 2,
+ },
+ {
+ .name = YUV 4:2:2 1p MultiPlanar,
+ .fourcc = V4L2_PIX_FMT_NV16,
+ .depth = {16},
+ .num_planes = 1,
+ },
+};
+#define NUM_FORMATS ARRAY_SIZE(formats)
+
+static const struct fimc_is_fmt *find_format(struct v4l2_format *f)
+{
+ unsigned int i;
+
+ for (i = 0; i NUM_FORMATS; i++) {
+ if (formats[i].fourcc == f-fmt.pix_mp.pixelformat)
+ return formats[i];
+ }
+ return NULL;
+}
+
+static int scaler_video_capture_start_streaming(struct vb2_queue *vq,
+ unsigned int count)
+{
+ struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+ int ret;
+
+ ret = fimc_is_pipeline_scaler_start(ctx-pipeline,
+ ctx-scaler_id,
+ vq-num_buffers,
+ ctx-fmt-num_planes);
+ if (ret) {
+ v4l2_err(ctx-subdev, Scaler start failed.\n);
+ return -EINVAL;
+ }
+
+ set_bit(STATE_RUNNING, ctx-capture_state);
+ return 0;
+}
+
+static int scaler_video_capture_stop_streaming(struct vb2_queue *vq)
+{
+ struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+ struct fimc_is_buf *buf;
+ int ret;
+
+ ret = fimc_is_pipeline_scaler_stop(ctx-pipeline, ctx-scaler_id);
+ if (ret)
+ v4l2_info(ctx-subdev, Scaler already stopped.\n);
+
+ /* Release un-used buffers */
+ while (!list_empty(ctx-wait_queue)) {
+ buf = fimc_is_scaler_wait_queue_get(ctx);
+ vb2_buffer_done(buf-vb, VB2_BUF_STATE_ERROR);
+ }
+ while (!list_empty(ctx-run_queue)) {
+ buf = fimc_is_scaler_run_queue_get(ctx);
+ vb2_buffer_done(buf-vb, VB2_BUF_STATE_ERROR);
+ }
+
+ clear_bit(STATE_RUNNING, ctx-capture_state);
+ return 0;
+}
+
+static int scaler_video_capture_queue_setup(struct vb2_queue *vq,
+ const struct v4l2_format *pfmt,
+ unsigned int *num_buffers, unsigned int *num_planes,
+ unsigned int sizes[], void *allocators[])
+{
+ struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+ const struct fimc_is_fmt *fmt = ctx-fmt;
+ unsigned int wh;
+ int i;
+
+ if (!fmt)
+ return -EINVAL;
+
+ *num_planes = fmt-num_planes;
+ wh = ctx-width * ctx-height;
+
+ for (i = 0; i *num_planes; i++) {
+ allocators[i] = ctx-alloc_ctx;
+ sizes[i] = (wh * fmt-depth[i]) / 8;
+ }
+ return 0;
+}
+
+static int scaler_video_capture_buffer_init(struct vb2_buffer *vb)
+{
+ struct vb2_queue *vq = vb-vb2_queue;
+ struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+ struct fimc_is_buf *buf = container_of(vb, struct fimc_is_buf, vb);
+ const struct fimc_is_fmt *fmt;
+ int i;
+
+ fmt = ctx-fmt;
+ for (i = 0; i fmt-num_planes; i++)
+ buf-paddr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
+
+
[PATCH v7 12/13] V4L: s5k6a3: Change sensor min/max resolutions
s5k6a3 sensor has actual pixel resolution of 1408x1402 against the active resolution 1392x1392. The real resolution is needed when raw sensor SRGB data is dumped to memory by fimc-lite. Signed-off-by: Arun Kumar K arun...@samsung.com Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com --- drivers/media/i2c/s5k6a3.c | 19 +++ 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/media/i2c/s5k6a3.c b/drivers/media/i2c/s5k6a3.c index ccbb4fc..34c3165 100644 --- a/drivers/media/i2c/s5k6a3.c +++ b/drivers/media/i2c/s5k6a3.c @@ -25,10 +25,12 @@ #include media/v4l2-async.h #include media/v4l2-subdev.h -#define S5K6A3_SENSOR_MAX_WIDTH1392 -#define S5K6A3_SENSOR_MAX_HEIGHT 1392 -#define S5K6A3_SENSOR_MIN_WIDTH32 -#define S5K6A3_SENSOR_MIN_HEIGHT 32 +#define S5K6A3_SENSOR_MAX_WIDTH1408 +#define S5K6A3_SENSOR_MAX_HEIGHT 1402 +#define S5K6A3_SENSOR_ACTIVE_WIDTH 1392 +#define S5K6A3_SENSOR_ACTIVE_HEIGHT1392 +#define S5K6A3_SENSOR_MIN_WIDTH(32 + 16) +#define S5K6A3_SENSOR_MIN_HEIGHT (32 + 10) #define S5K6A3_DEF_PIX_WIDTH 1296 #define S5K6A3_DEF_PIX_HEIGHT 732 @@ -107,10 +109,11 @@ static void s5k6a3_try_format(struct v4l2_mbus_framefmt *mf) fmt = find_sensor_format(mf); mf-code = fmt-code; - v4l_bound_align_image(mf-width, S5K6A3_SENSOR_MIN_WIDTH, - S5K6A3_SENSOR_MAX_WIDTH, 0, - mf-height, S5K6A3_SENSOR_MIN_HEIGHT, - S5K6A3_SENSOR_MAX_HEIGHT, 0, 0); + v4l_bound_align_image(mf-width, + S5K6A3_SENSOR_MIN_WIDTH, S5K6A3_SENSOR_MAX_WIDTH, 0, + mf-height, + S5K6A3_SENSOR_MIN_HEIGHT, S5K6A3_SENSOR_MAX_HEIGHT, 0, + 0); } static struct v4l2_mbus_framefmt *__s5k6a3_get_format( -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 08/13] [media] exynos5-fimc-is: Add sensor interface
Some sensors to be used with fimc-is are exclusively controlled
by the fimc-is firmware. This minimal sensor driver provides
the required info for the firmware to configure the sensors
sitting on I2C bus.
Signed-off-by: Arun Kumar K arun...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
drivers/media/platform/exynos5-is/fimc-is-sensor.c | 45 ++
drivers/media/platform/exynos5-is/fimc-is-sensor.h | 65
2 files changed, 110 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-sensor.c
b/drivers/media/platform/exynos5-is/fimc-is-sensor.c
new file mode 100644
index 000..475f1c3
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-sensor.c
@@ -0,0 +1,45 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Arun Kumar K arun...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include fimc-is-sensor.h
+
+static const struct sensor_drv_data s5k6a3_drvdata = {
+ .id = FIMC_IS_SENSOR_ID_S5K6A3,
+ .open_timeout = S5K6A3_OPEN_TIMEOUT,
+ .setfile_name = exynos5_s5k6a3_setfile.bin,
+};
+
+static const struct sensor_drv_data s5k4e5_drvdata = {
+ .id = FIMC_IS_SENSOR_ID_S5K4E5,
+ .open_timeout = S5K4E5_OPEN_TIMEOUT,
+ .setfile_name = exynos5_s5k4e5_setfile.bin,
+};
+
+static const struct of_device_id fimc_is_sensor_of_ids[] = {
+ {
+ .compatible = samsung,s5k6a3,
+ .data = s5k6a3_drvdata,
+ },
+ {
+ .compatible = samsung,s5k4e5,
+ .data = s5k4e5_drvdata,
+ },
+ { }
+};
+
+const struct sensor_drv_data *exynos5_is_sensor_get_drvdata(
+ struct device_node *node)
+{
+ const struct of_device_id *of_id;
+
+ of_id = of_match_node(fimc_is_sensor_of_ids, node);
+ return of_id ? of_id-data : NULL;
+}
diff --git a/drivers/media/platform/exynos5-is/fimc-is-sensor.h
b/drivers/media/platform/exynos5-is/fimc-is-sensor.h
new file mode 100644
index 000..0ba5733
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-sensor.h
@@ -0,0 +1,65 @@
+/*
+ * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Arun Kumar K arun...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef FIMC_IS_SENSOR_H_
+#define FIMC_IS_SENSOR_H_
+
+#include linux/of.h
+#include linux/types.h
+
+#define S5K6A3_OPEN_TIMEOUT2000 /* ms */
+#define S5K6A3_SENSOR_WIDTH1392
+#define S5K6A3_SENSOR_HEIGHT 1392
+
+#define S5K4E5_OPEN_TIMEOUT2000 /* ms */
+#define S5K4E5_SENSOR_WIDTH2560
+#define S5K4E5_SENSOR_HEIGHT 1920
+
+#define SENSOR_WIDTH_PADDING 16
+#define SENSOR_HEIGHT_PADDING 10
+
+enum fimc_is_sensor_id {
+ FIMC_IS_SENSOR_ID_S5K3H2 = 1,
+ FIMC_IS_SENSOR_ID_S5K6A3,
+ FIMC_IS_SENSOR_ID_S5K4E5,
+ FIMC_IS_SENSOR_ID_S5K3H7,
+ FIMC_IS_SENSOR_ID_CUSTOM,
+ FIMC_IS_SENSOR_ID_END
+};
+
+struct sensor_drv_data {
+ enum fimc_is_sensor_id id;
+ /* sensor open timeout in ms */
+ unsigned short open_timeout;
+ char *setfile_name;
+};
+
+/**
+ * struct fimc_is_sensor - fimc-is sensor data structure
+ * @drvdata: a pointer to the sensor's parameters data structure
+ * @i2c_bus: ISP I2C bus index (0...1)
+ * @width: sensor active width
+ * @height: sensor active height
+ * @pixel_width: sensor effective pixel width (width + padding)
+ * @pixel_height: sensor effective pixel height (height + padding)
+ */
+struct fimc_is_sensor {
+ const struct sensor_drv_data *drvdata;
+ unsigned int i2c_bus;
+ unsigned int width;
+ unsigned int height;
+ unsigned int pixel_width;
+ unsigned int pixel_height;
+};
+
+const struct sensor_drv_data *exynos5_is_sensor_get_drvdata(
+ struct device_node *node);
+
+#endif /* FIMC_IS_SENSOR_H_ */
--
1.7.9.5
--
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[PATCH v7 11/13] [media] exynos5-is: Add Kconfig and Makefile
Adds Kconfig and Makefile for exynos5-is driver files. Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com Signed-off-by: Arun Kumar K arun...@samsung.com Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com --- drivers/media/platform/Kconfig |1 + drivers/media/platform/Makefile|1 + drivers/media/platform/exynos5-is/Kconfig | 20 drivers/media/platform/exynos5-is/Makefile |7 +++ 4 files changed, 29 insertions(+) create mode 100644 drivers/media/platform/exynos5-is/Kconfig create mode 100644 drivers/media/platform/exynos5-is/Makefile diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig index 08de865..4b0475e 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig @@ -123,6 +123,7 @@ config VIDEO_S3C_CAMIF source drivers/media/platform/soc_camera/Kconfig source drivers/media/platform/exynos4-is/Kconfig +source drivers/media/platform/exynos5-is/Kconfig source drivers/media/platform/s5p-tv/Kconfig endif # V4L_PLATFORM_DRIVERS diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile index eee28dd..40bf09f 100644 --- a/drivers/media/platform/Makefile +++ b/drivers/media/platform/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_VIDEO_SAMSUNG_S5P_TV)+= s5p-tv/ obj-$(CONFIG_VIDEO_SAMSUNG_S5P_G2D)+= s5p-g2d/ obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC) += exynos-gsc/ +obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_CAMERA) += exynos5-is/ obj-$(CONFIG_BLACKFIN) += blackfin/ diff --git a/drivers/media/platform/exynos5-is/Kconfig b/drivers/media/platform/exynos5-is/Kconfig new file mode 100644 index 000..b67d11a --- /dev/null +++ b/drivers/media/platform/exynos5-is/Kconfig @@ -0,0 +1,20 @@ +config VIDEO_SAMSUNG_EXYNOS5_CAMERA + bool Samsung Exynos5 SoC Camera Media Device driver + depends on VIDEO_V4L2 VIDEO_V4L2_SUBDEV_API PM_RUNTIME + depends on VIDEO_SAMSUNG_EXYNOS4_IS + help + This is a V4L2 media device driver for Exynos5 SoC series + camera subsystem. + +if VIDEO_SAMSUNG_EXYNOS5_CAMERA + +config VIDEO_SAMSUNG_EXYNOS5_FIMC_IS + tristate Samsung Exynos5 SoC FIMC-IS driver + depends on I2C OF + depends on VIDEO_EXYNOS4_FIMC_IS + select VIDEOBUF2_DMA_CONTIG + help + This is a V4L2 driver for Samsung Exynos5 SoC series Imaging + Subsystem known as FIMC-IS. + +endif #VIDEO_SAMSUNG_EXYNOS5_MDEV diff --git a/drivers/media/platform/exynos5-is/Makefile b/drivers/media/platform/exynos5-is/Makefile new file mode 100644 index 000..6cdb037 --- /dev/null +++ b/drivers/media/platform/exynos5-is/Makefile @@ -0,0 +1,7 @@ +ccflags-y += -Idrivers/media/platform/exynos4-is +exynos5-fimc-is-objs := fimc-is-core.o fimc-is-isp.o fimc-is-scaler.o +exynos5-fimc-is-objs += fimc-is-pipeline.o fimc-is-interface.o fimc-is-sensor.o +exynos-mdevice-objs := exynos5-mdev.o + +obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_FIMC_IS) += exynos5-fimc-is.o +obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_CAMERA) += exynos-mdevice.o -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 13/13] V4L: Add driver for s5k4e5 image sensor
This patch adds subdev driver for Samsung S5K4E5 raw image sensor.
Like s5k6a3, it is also another fimc-is firmware controlled
sensor. This minimal sensor driver doesn't do any I2C communications
as its done by ISP firmware. It can be updated if needed to a
regular sensor driver by adding the I2C communication.
Signed-off-by: Arun Kumar K arun...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
.../devicetree/bindings/media/i2c/s5k4e5.txt | 43 +++
drivers/media/i2c/Kconfig |8 +
drivers/media/i2c/Makefile |1 +
drivers/media/i2c/s5k4e5.c | 361
4 files changed, 413 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/i2c/s5k4e5.txt
create mode 100644 drivers/media/i2c/s5k4e5.c
diff --git a/Documentation/devicetree/bindings/media/i2c/s5k4e5.txt
b/Documentation/devicetree/bindings/media/i2c/s5k4e5.txt
new file mode 100644
index 000..5af462c
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/s5k4e5.txt
@@ -0,0 +1,43 @@
+* Samsung S5K4E5 Raw Image Sensor
+
+S5K4E5 is a raw image sensor with maximum resolution of 2560x1920
+pixels. Data transfer is carried out via MIPI CSI-2 port and controls
+via I2C bus.
+
+Required Properties:
+- compatible : must be samsung,s5k4e5
+- reg : I2C device address
+- gpios: reset gpio pin
+- clocks : clock specifier for the clock-names property
+- clock-names : must contain mclk entry
+- svdda-supply : core voltage supply
+- svddio-supply: I/O voltage supply
+
+Optional Properties:
+- clock-frequency : operating frequency for the sensor
+default value will be taken if not provided.
+
+The device node should be added to respective control bus controller
+(e.g. I2C0) nodes and linked to the csis port node, using the common
+video interfaces bindings, defined in video-interfaces.txt.
+
+Example:
+
+ i2c-isp@1313 {
+ s5k4e5@20 {
+ compatible = samsung,s5k4e5;
+ reg = 0x20;
+ gpios = gpx1 2 1;
+ clock-frequency = 2400;
+ clocks = clock 129;
+ clock-names = mclk;
+ svdda-supply = ...;
+ svddio-supply = ...;
+ port {
+ is_s5k4e5_ep: endpoint {
+ data-lanes = 1 2 3 4;
+ remote-endpoint = csis0_ep;
+ };
+ };
+ };
+ };
diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index f7e9147..271028b 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -572,6 +572,14 @@ config VIDEO_S5K6A3
This is a V4L2 sensor-level driver for Samsung S5K6A3 raw
camera sensor.
+config VIDEO_S5K4E5
+ tristate Samsung S5K4E5 sensor support
+ depends on MEDIA_CAMERA_SUPPORT
+ depends on I2C VIDEO_V4L2 VIDEO_V4L2_SUBDEV_API OF
+ ---help---
+ This is a V4L2 sensor-level driver for Samsung S5K4E5 raw
+ camera sensor.
+
config VIDEO_S5K4ECGX
tristate Samsung S5K4ECGX sensor support
depends on I2C VIDEO_V4L2 VIDEO_V4L2_SUBDEV_API
diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
index cf3cf03..0aeed8e 100644
--- a/drivers/media/i2c/Makefile
+++ b/drivers/media/i2c/Makefile
@@ -65,6 +65,7 @@ obj-$(CONFIG_VIDEO_SR030PC30) += sr030pc30.o
obj-$(CONFIG_VIDEO_NOON010PC30)+= noon010pc30.o
obj-$(CONFIG_VIDEO_S5K6AA) += s5k6aa.o
obj-$(CONFIG_VIDEO_S5K6A3) += s5k6a3.o
+obj-$(CONFIG_VIDEO_S5K4E5) += s5k4e5.o
obj-$(CONFIG_VIDEO_S5K4ECGX) += s5k4ecgx.o
obj-$(CONFIG_VIDEO_S5C73M3)+= s5c73m3/
obj-$(CONFIG_VIDEO_ADP1653)+= adp1653.o
diff --git a/drivers/media/i2c/s5k4e5.c b/drivers/media/i2c/s5k4e5.c
new file mode 100644
index 000..0a6ece6
--- /dev/null
+++ b/drivers/media/i2c/s5k4e5.c
@@ -0,0 +1,361 @@
+/*
+ * Samsung S5K4E5 image sensor driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Arun Kumar K arun...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/clk.h
+#include linux/delay.h
+#include linux/device.h
+#include linux/errno.h
+#include linux/gpio.h
+#include linux/i2c.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/of_gpio.h
+#include linux/pm_runtime.h
+#include linux/regulator/consumer.h
+#include linux/slab.h
+#include linux/videodev2.h
+#include media/v4l2-async.h
+#include media/v4l2-subdev.h
+
+#define S5K4E5_SENSOR_MAX_WIDTH2576
+#define S5K4E5_SENSOR_MAX_HEIGHT 1930
+
[PATCH V2] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.
changes since V1:
1.disable node by status = disabled in SOC file
2.enable node by status = okay in board specific file
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
---
.../devicetree/bindings/mmc/exynos-dw-mshc.txt |2 +
arch/arm/boot/dts/exynos5420-smdk5420.dts | 39
arch/arm/boot/dts/exynos5420.dtsi | 36 ++
3 files changed, 77 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 6d1c098..84cd56f 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -16,6 +16,8 @@ Required Properties:
specific extensions.
- samsung,exynos5250-dw-mshc: for controllers with Samsung Exynos5250
specific extensions.
+ - samsung,exynos5420-dw-mshc: for controllers with Samsung Exynos5420
+ specific extensions.
* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 08607df..0b2e464 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -30,4 +30,43 @@
clock-frequency = 2400;
};
};
+
+ dwmmc0@1220 {
+ status = okay;
+ num-slots = 1;
+ broken-cd;
+ bypass-smu;
+ supports-highspeed;
+ fifo-depth = 0x80;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 0 4;
+ samsung,dw-mshc-ddr-timing = 0 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ };
+ };
+
+ dwmmc2@1222 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ fifo-depth = 0x80;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd2_clk sd2_cmd sd2_cd sd2_bus4;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 4;
+ };
+ };
+
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 9e90d1e..d9220c3 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -19,6 +19,9 @@
compatible = samsung,exynos5420;
aliases {
+ mshc0 = dwmmc_0;
+ mshc1 = dwmmc_1;
+ mshc2 = dwmmc_2;
pinctrl0 = pinctrl_0;
pinctrl1 = pinctrl_1;
pinctrl2 = pinctrl_2;
@@ -65,6 +68,39 @@
#clock-cells = 1;
};
+ dwmmc_0: dwmmc0@1220 {
+ compatible = samsung,exynos5420-dw-mshc;
+ interrupts = 0 75 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1220 0x2000;
+ clocks = clock 351, clock 132;
+ clock-names = biu, ciu;
+ status = disabled;
+ };
+
+ dwmmc_1: dwmmc1@1221 {
+ compatible = samsung,exynos5420-dw-mshc;
+ interrupts = 0 76 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1221 0x2000;
+ clocks = clock 352, clock 133;
+ clock-names = biu, ciu;
+ status = disabled;
+ };
+
+ dwmmc_2: dwmmc2@1222 {
+ compatible = samsung,exynos5420-dw-mshc;
+ interrupts = 0 77 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1222 0x2000;
+ clocks = clock 353, clock 134;
+ clock-names = biu, ciu;
+ status = disabled;
+ };
+
mct@101C {
compatible = samsung,exynos4210-mct;
reg = 0x101C 0x800;
--
1.7.9.5
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[PATCH v7 10/13] [media] exynos5-fimc-is: Add the hardware interface module
The hardware interface module finally sends the commands to the
FIMC-IS firmware and runs the interrupt handler for getting the
responses.
Signed-off-by: Arun Kumar K arun...@samsung.com
Signed-off-by: Kilyeon Im kilyeon...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
.../media/platform/exynos5-is/fimc-is-interface.c | 810
.../media/platform/exynos5-is/fimc-is-interface.h | 125 +++
2 files changed, 935 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-interface.c
b/drivers/media/platform/exynos5-is/fimc-is-interface.c
new file mode 100644
index 000..c5da6ff
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-interface.c
@@ -0,0 +1,810 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Kil-yeon Lim kilyeon...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/debugfs.h
+#include linux/seq_file.h
+#include fimc-is.h
+#include fimc-is-cmd.h
+#include fimc-is-regs.h
+
+#define init_request_barrier(itf) mutex_init(itf-request_barrier)
+#define enter_request_barrier(itf) mutex_lock(itf-request_barrier)
+#define exit_request_barrier(itf) mutex_unlock(itf-request_barrier)
+
+static inline void itf_get_cmd(struct fimc_is_interface *itf,
+ struct fimc_is_msg *msg, unsigned int index)
+{
+ struct is_common_reg __iomem *com_regs = itf-com_regs;
+
+ memset(msg, 0, sizeof(*msg));
+
+ switch (index) {
+ case INTR_GENERAL:
+ msg-command = com_regs-ihcmd;
+ msg-instance = com_regs-ihc_sensorid;
+ memcpy(msg-param, com_regs-ihc_param,
+ 4 * sizeof(msg-param[0]));
+ break;
+ case INTR_SCC_FDONE:
+ msg-command = IHC_FRAME_DONE;
+ msg-instance = com_regs-scc_sensor_id;
+ memcpy(msg-param, com_regs-scc_param,
+ 3 * sizeof(msg-param[0]));
+ break;
+ case INTR_SCP_FDONE:
+ msg-command = IHC_FRAME_DONE;
+ msg-instance = com_regs-scp_sensor_id;
+ memcpy(msg-param, com_regs-scp_param,
+ 3 * sizeof(msg-param[0]));
+ break;
+ case INTR_META_DONE:
+ msg-command = IHC_FRAME_DONE;
+ msg-instance = com_regs-meta_sensor_id;
+ msg-param[0] = com_regs-meta_param1;
+ break;
+ case INTR_SHOT_DONE:
+ msg-command = IHC_FRAME_DONE;
+ msg-instance = com_regs-shot_sensor_id;
+ memcpy(msg-param, com_regs-shot_param,
+ 2 * sizeof(msg-param[0]));
+ break;
+ default:
+ dev_err(itf-dev, %s Unknown command\n, __func__);
+ break;
+ }
+}
+
+static inline unsigned int itf_get_intr(struct fimc_is_interface *itf)
+{
+ unsigned int status;
+ struct is_common_reg __iomem *com_regs = itf-com_regs;
+
+ status = readl(itf-regs + INTMSR1) | com_regs-ihcmd_iflag |
+ com_regs-scc_iflag |
+ com_regs-scp_iflag |
+ com_regs-meta_iflag |
+ com_regs-shot_iflag;
+
+ return status;
+}
+
+static void itf_set_state(struct fimc_is_interface *itf,
+ unsigned long state)
+{
+ unsigned long flags;
+ spin_lock_irqsave(itf-slock_state, flags);
+ __set_bit(state, itf-state);
+ spin_unlock_irqrestore(itf-slock_state, flags);
+}
+
+static void itf_clr_state(struct fimc_is_interface *itf,
+ unsigned long state)
+{
+ unsigned long flags;
+ spin_lock_irqsave(itf-slock_state, flags);
+ __clear_bit(state, itf-state);
+ spin_unlock_irqrestore(itf-slock_state, flags);
+}
+
+static int itf_get_state(struct fimc_is_interface *itf,
+ unsigned long state)
+{
+ int ret = 0;
+ unsigned long flags;
+
+ spin_lock_irqsave(itf-slock_state, flags);
+ ret = test_bit(state, itf-state);
+ spin_unlock_irqrestore(itf-slock_state, flags);
+ return ret;
+}
+
+static void itf_init_wakeup(struct fimc_is_interface *itf)
+{
+ itf_set_state(itf, IS_IF_STATE_INIT);
+ wake_up(itf-irq_queue);
+}
+
+void itf_busy_wakeup(struct fimc_is_interface *itf)
+{
+ itf_clr_state(itf, IS_IF_STATE_BUSY);
+ wake_up(itf-irq_queue);
+}
+
+static int itf_wait_hw_ready(struct fimc_is_interface *itf)
+{
+ int t;
+ for (t = TRY_RECV_AWARE_COUNT; t = 0; t--) {
+ unsigned int cfg = readl(itf-regs + INTMSR0);
+
[PATCH v7 09/13] [media] exynos5-fimc-is: Add the hardware pipeline control
This patch adds the crucial hardware pipeline control for the
fimc-is driver. All the subdev nodes will call this pipeline
interfaces to reach the hardware. Responsibilities of this module
involves configuring and maintaining the hardware pipeline involving
multiple sub-ips like ISP, DRC, Scalers, ODC, 3DNR, FD etc.
Signed-off-by: Arun Kumar K arun...@samsung.com
Signed-off-by: Kilyeon Im kilyeon...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
.../media/platform/exynos5-is/fimc-is-pipeline.c | 1692
.../media/platform/exynos5-is/fimc-is-pipeline.h | 128 ++
2 files changed, 1820 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-pipeline.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-pipeline.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-pipeline.c
b/drivers/media/platform/exynos5-is/fimc-is-pipeline.c
new file mode 100644
index 000..7d91469
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-pipeline.c
@@ -0,0 +1,1692 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K arun...@samsung.com
+ * Kil-yeon Lim kilyeon...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include fimc-is.h
+#include fimc-is-pipeline.h
+#include fimc-is-metadata.h
+#include fimc-is-regs.h
+#include fimc-is-cmd.h
+#include media/videobuf2-dma-contig.h
+#include linux/delay.h
+
+/* Default setting values */
+#define DEFAULT_PREVIEW_STILL_WIDTH1280
+#define DEFAULT_PREVIEW_STILL_HEIGHT 720
+#define DEFAULT_CAPTURE_VIDEO_WIDTH1920
+#define DEFAULT_CAPTURE_VIDEO_HEIGHT 1080
+#define DEFAULT_CAPTURE_STILL_WIDTH2560
+#define DEFAULT_CAPTURE_STILL_HEIGHT 1920
+#define DEFAULT_CAPTURE_STILL_CROP_WIDTH 2560
+#define DEFAULT_CAPTURE_STILL_CROP_HEIGHT 1440
+#define DEFAULT_PREVIEW_VIDEO_WIDTH640
+#define DEFAULT_PREVIEW_VIDEO_HEIGHT 480
+
+/* Init params for pipeline devices */
+static const struct sensor_param init_sensor_param = {
+ .frame_rate = {
+ .frame_rate = 30,
+ },
+};
+
+static const struct isp_param init_isp_param = {
+ .control = {
+ .cmd = CONTROL_COMMAND_START,
+ .bypass = CONTROL_BYPASS_DISABLE,
+ },
+ .otf_input = {
+ .cmd = OTF_INPUT_COMMAND_DISABLE,
+ .width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ .format = OTF_INPUT_FORMAT_BAYER,
+ .bitwidth = OTF_INPUT_BIT_WIDTH_10BIT,
+ .order = OTF_INPUT_ORDER_BAYER_GR_BG,
+ .frametime_max = 3,
+ },
+ .dma1_input = {
+ .cmd = DMA_INPUT_COMMAND_DISABLE,
+ },
+ .dma2_input = {
+ .cmd = DMA_INPUT_COMMAND_DISABLE,
+ },
+ .aa = {
+ .cmd = ISP_AA_COMMAND_START,
+ .target = ISP_AA_TARGET_AF | ISP_AA_TARGET_AE |
+ ISP_AA_TARGET_AWB,
+ .mode = ISP_AF_CONTINUOUS,
+ },
+ .flash = {
+ .cmd = ISP_FLASH_COMMAND_DISABLE,
+ .redeye = ISP_FLASH_REDEYE_DISABLE,
+ },
+ .awb = {
+ .cmd = ISP_AWB_COMMAND_AUTO,
+ },
+ .effect = {
+ .cmd = ISP_IMAGE_EFFECT_DISABLE,
+ },
+ .iso = {
+ .cmd = ISP_ISO_COMMAND_AUTO,
+ },
+ .adjust = {
+ .cmd = ISP_ADJUST_COMMAND_AUTO,
+ },
+ .metering = {
+ .cmd = ISP_METERING_COMMAND_CENTER,
+ .win_width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .win_height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ },
+ .afc = {
+ .cmd = ISP_AFC_COMMAND_AUTO,
+ },
+ .otf_output = {
+ .cmd = OTF_OUTPUT_COMMAND_ENABLE,
+ .width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ .format = OTF_OUTPUT_FORMAT_YUV444,
+ .bitwidth = OTF_OUTPUT_BIT_WIDTH_12BIT,
+ .order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+ },
+ .dma1_output = {
+ .cmd = DMA_OUTPUT_COMMAND_DISABLE,
+ .width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ .format = DMA_INPUT_FORMAT_YUV444,
+ .bitwidth = DMA_INPUT_BIT_WIDTH_8BIT,
+ .plane = 1,
+ .order = DMA_INPUT_ORDER_YCBCR,
+ },
+ .dma2_output = {
+ .cmd = DMA_OUTPUT_COMMAND_DISABLE,
+ .width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+
[PATCH 4/8] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
---
.../devicetree/bindings/mmc/exynos-dw-mshc.txt |2 +
arch/arm/boot/dts/exynos5420-smdk5420.dts | 41
arch/arm/boot/dts/exynos5420.dtsi | 33
3 files changed, 76 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 6d1c098..84cd56f 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -16,6 +16,8 @@ Required Properties:
specific extensions.
- samsung,exynos5250-dw-mshc: for controllers with Samsung Exynos5250
specific extensions.
+ - samsung,exynos5420-dw-mshc: for controllers with Samsung Exynos5420
+ specific extensions.
* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 08607df..4530700 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -30,4 +30,45 @@
clock-frequency = 2400;
};
};
+
+ dwmmc0@1220 {
+ num-slots = 1;
+ broken-cd;
+ bypass-smu;
+ supports-highspeed;
+ fifo-depth = 0x80;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 0 4;
+ samsung,dw-mshc-ddr-timing = 0 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ };
+ };
+
+ dwmmc1@1221 {
+ status = disabled;
+ };
+
+ dwmmc2@1222 {
+ num-slots = 1;
+ supports-highspeed;
+ fifo-depth = 0x80;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd2_clk sd2_cmd sd2_cd sd2_bus4;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 4;
+ };
+ };
+
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 9e90d1e..8559aa8 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -19,6 +19,9 @@
compatible = samsung,exynos5420;
aliases {
+ mshc0 = dwmmc_0;
+ mshc1 = dwmmc_1;
+ mshc2 = dwmmc_2;
pinctrl0 = pinctrl_0;
pinctrl1 = pinctrl_1;
pinctrl2 = pinctrl_2;
@@ -65,6 +68,36 @@
#clock-cells = 1;
};
+ dwmmc_0: dwmmc0@1220 {
+ compatible = samsung,exynos5420-dw-mshc;
+ interrupts = 0 75 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1220 0x2000;
+ clocks = clock 351, clock 132;
+ clock-names = biu, ciu;
+ };
+
+ dwmmc_1: dwmmc1@1221 {
+ compatible = samsung,exynos5420-dw-mshc;
+ interrupts = 0 76 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1221 0x2000;
+ clocks = clock 352, clock 133;
+ clock-names = biu, ciu;
+ };
+
+ dwmmc_2: dwmmc2@1222 {
+ compatible = samsung,exynos5420-dw-mshc;
+ interrupts = 0 77 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1222 0x2000;
+ clocks = clock 353, clock 134;
+ clock-names = biu, ciu;
+ };
+
mct@101C {
compatible = samsung,exynos4210-mct;
reg = 0x101C 0x800;
--
1.7.9.5
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[PATCH V2 2/2] ARM: dts: Add dwmmc nodes in SOC specific dts file
From: Yuvaraj Kumar C D yuvaraj...@samsung.com
Exynos5 series SOC's have different versions of DWMMC controller.
So dwmmc device nodes moved from Exynos5 SOC's common dts file to
SOC specific dts file.
changes since V1:
1.disable node by status = disabled in SOC file
2.enable node by status = okay in board specific file
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 10 ++
arch/arm/boot/dts/exynos5250.dtsi | 16
2 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 2538b32..bd19d55d 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -141,6 +141,7 @@
};
dwmmc0@1220 {
+ status = okay;
num-slots = 1;
supports-highspeed;
broken-cd;
@@ -158,11 +159,8 @@
};
};
- dwmmc1@1221 {
- status = disabled;
- };
-
dwmmc2@1222 {
+ status = okay;
num-slots = 1;
supports-highspeed;
fifo-depth = 0x80;
@@ -180,10 +178,6 @@
};
};
- dwmmc3@1223 {
- status = disabled;
- };
-
spi_0: spi@12d2 {
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 1eec646..b1b6f61 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -387,21 +387,36 @@
};
dwmmc_0: dwmmc0@1220 {
+ compatible = samsung,exynos5250-dw-mshc;
+ interrupts = 0 75 0;
+ #address-cells = 1;
+ #size-cells = 0;
reg = 0x1220 0x1000;
clocks = clock 280, clock 139;
clock-names = biu, ciu;
+ status = disabled;
};
dwmmc_1: dwmmc1@1221 {
+ compatible = samsung,exynos5250-dw-mshc;
+ interrupts = 0 76 0;
+ #address-cells = 1;
+ #size-cells = 0;
reg = 0x1221 0x1000;
clocks = clock 281, clock 140;
clock-names = biu, ciu;
+ status = disabled;
};
dwmmc_2: dwmmc2@1222 {
+ compatible = samsung,exynos5250-dw-mshc;
+ interrupts = 0 77 0;
+ #address-cells = 1;
+ #size-cells = 0;
reg = 0x1222 0x1000;
clocks = clock 282, clock 141;
clock-names = biu, ciu;
+ status = disabled;
};
dwmmc_3: dwmmc3@1223 {
@@ -412,6 +427,7 @@
#size-cells = 0;
clocks = clock 283, clock 142;
clock-names = biu, ciu;
+ status = disabled;
};
i2s0: i2s@0383 {
--
1.7.9.5
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[PATCH V2 1/2] ARM: dts: remove dwmmc nodes from exynos5 common dts file.
From: Yuvaraj Kumar C D yuvaraj...@samsung.com
Exynos5 series SOC's 5250 and 5420 have different versions of
DWMMC controller.So there is a new compatible string to distinguish
between them.So these nodes should be moved out of Exynos5 series
common device tree source.
Changes since V1: none
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
---
arch/arm/boot/dts/exynos5.dtsi | 21 -
1 file changed, 21 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 6afa57d..24140f0 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -50,27 +50,6 @@
interrupts = 1 9 0xf04;
};
- dwmmc_0: dwmmc0@1220 {
- compatible = samsung,exynos5250-dw-mshc;
- interrupts = 0 75 0;
- #address-cells = 1;
- #size-cells = 0;
- };
-
- dwmmc_1: dwmmc1@1221 {
- compatible = samsung,exynos5250-dw-mshc;
- interrupts = 0 76 0;
- #address-cells = 1;
- #size-cells = 0;
- };
-
- dwmmc_2: dwmmc2@1222 {
- compatible = samsung,exynos5250-dw-mshc;
- interrupts = 0 77 0;
- #address-cells = 1;
- #size-cells = 0;
- };
-
serial@12C0 {
compatible = samsung,exynos4210-uart;
reg = 0x12C0 0x100;
--
1.7.9.5
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[PATCH V2] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.
changes since V1:
1.disable node by status = disabled in SOC file
2.enable node by status = okay in board specific file
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
---
.../devicetree/bindings/mmc/exynos-dw-mshc.txt |2 ++
arch/arm/boot/dts/exynos5420-smdk5420.dts | 38
arch/arm/boot/dts/exynos5420.dtsi | 36 +++
3 files changed, 76 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 6d1c098..84cd56f 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -16,6 +16,8 @@ Required Properties:
specific extensions.
- samsung,exynos5250-dw-mshc: for controllers with Samsung Exynos5250
specific extensions.
+ - samsung,exynos5420-dw-mshc: for controllers with Samsung Exynos5420
+ specific extensions.
* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index bafba25..6e65278 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -31,6 +31,44 @@
};
};
+ dwmmc0@1220 {
+ status = okay;
+ num-slots = 1;
+ broken-cd;
+ bypass-smu;
+ supports-highspeed;
+ fifo-depth = 0x80;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 0 4;
+ samsung,dw-mshc-ddr-timing = 0 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ };
+ };
+
+ dwmmc2@1222 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ fifo-depth = 0x80;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd2_clk sd2_cmd sd2_cd sd2_bus4;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 4;
+ };
+ };
+
dp-controller@145B {
pinctrl-names = default;
pinctrl-0 = dp_hpd;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 5353e32..694e7f1 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -22,6 +22,9 @@
compatible = samsung,exynos5420;
aliases {
+ mshc0 = dwmmc_0;
+ mshc1 = dwmmc_1;
+ mshc2 = dwmmc_2;
pinctrl0 = pinctrl_0;
pinctrl1 = pinctrl_1;
pinctrl2 = pinctrl_2;
@@ -84,6 +87,39 @@
clock-names = mfc;
};
+ dwmmc_0: dwmmc0@1220 {
+ compatible = samsung,exynos5420-dw-mshc;
+ interrupts = 0 75 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1220 0x2000;
+ clocks = clock 351, clock 132;
+ clock-names = biu, ciu;
+ status = disabled;
+ };
+
+ dwmmc_1: dwmmc1@1221 {
+ compatible = samsung,exynos5420-dw-mshc;
+ interrupts = 0 76 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1221 0x2000;
+ clocks = clock 352, clock 133;
+ clock-names = biu, ciu;
+ status = disabled;
+ };
+
+ dwmmc_2: dwmmc2@1222 {
+ compatible = samsung,exynos5420-dw-mshc;
+ interrupts = 0 77 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1222 0x2000;
+ clocks = clock 353, clock 134;
+ clock-names = biu, ciu;
+ status = disabled;
+ };
+
mct@101C {
compatible = samsung,exynos4210-mct;
reg = 0x101C 0x800;
--
1.7.9.5
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Re: [PATCH v7 13/13] V4L: Add driver for s5k4e5 image sensor
On 08/21/2013 08:34 AM, Arun Kumar K wrote:
This patch adds subdev driver for Samsung S5K4E5 raw image sensor.
Like s5k6a3, it is also another fimc-is firmware controlled
sensor. This minimal sensor driver doesn't do any I2C communications
as its done by ISP firmware. It can be updated if needed to a
regular sensor driver by adding the I2C communication.
Signed-off-by: Arun Kumar K arun...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
.../devicetree/bindings/media/i2c/s5k4e5.txt | 43 +++
drivers/media/i2c/Kconfig |8 +
drivers/media/i2c/Makefile |1 +
drivers/media/i2c/s5k4e5.c | 361
4 files changed, 413 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/i2c/s5k4e5.txt
create mode 100644 drivers/media/i2c/s5k4e5.c
...
diff --git a/drivers/media/i2c/s5k4e5.c b/drivers/media/i2c/s5k4e5.c
new file mode 100644
index 000..0a6ece6
--- /dev/null
+++ b/drivers/media/i2c/s5k4e5.c
@@ -0,0 +1,361 @@
+/*
+ * Samsung S5K4E5 image sensor driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Arun Kumar K arun...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/clk.h
+#include linux/delay.h
+#include linux/device.h
+#include linux/errno.h
+#include linux/gpio.h
+#include linux/i2c.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/of_gpio.h
+#include linux/pm_runtime.h
+#include linux/regulator/consumer.h
+#include linux/slab.h
+#include linux/videodev2.h
+#include media/v4l2-async.h
+#include media/v4l2-subdev.h
+
+#define S5K4E5_SENSOR_MAX_WIDTH 2576
+#define S5K4E5_SENSOR_MAX_HEIGHT 1930
+
+#define S5K4E5_SENSOR_ACTIVE_WIDTH 2560
+#define S5K4E5_SENSOR_ACTIVE_HEIGHT 1920
+
+#define S5K4E5_SENSOR_MIN_WIDTH (32 + 16)
+#define S5K4E5_SENSOR_MIN_HEIGHT (32 + 10)
+
+#define S5K4E5_DEF_WIDTH 1296
+#define S5K4E5_DEF_HEIGHT732
+
+#define S5K4E5_DRV_NAME S5K4E5
+#define S5K4E5_CLK_NAME mclk
+
+#define S5K4E5_NUM_SUPPLIES 2
+
+#define S5K4E5_DEF_CLK_FREQ 2400
+
+/**
+ * struct s5k4e5 - s5k4e5 sensor data structure
+ * @dev: pointer to this I2C client device structure
+ * @subdev: the image sensor's v4l2 subdev
+ * @pad: subdev media source pad
+ * @supplies: image sensor's voltage regulator supplies
+ * @gpio_reset: GPIO connected to the sensor's reset pin
+ * @lock: mutex protecting the structure's members below
+ * @format: media bus format at the sensor's source pad
+ */
+struct s5k4e5 {
+ struct device *dev;
+ struct v4l2_subdev subdev;
+ struct media_pad pad;
+ struct regulator_bulk_data supplies[S5K4E5_NUM_SUPPLIES];
+ int gpio_reset;
+ struct mutex lock;
+ struct v4l2_mbus_framefmt format;
+ struct clk *clock;
+ u32 clock_frequency;
+};
+
+static const char * const s5k4e5_supply_names[] = {
+ svdda,
+ svddio
+};
I'm no regulator expert, but shouldn't this list come from the DT or
platform_data?
Or are these names specific to this sensor?
Regards,
Hans
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Re: [PATCH v7 13/13] V4L: Add driver for s5k4e5 image sensor
Hi Hans,
On Wednesday 21 of August 2013 08:53:55 Hans Verkuil wrote:
On 08/21/2013 08:34 AM, Arun Kumar K wrote:
This patch adds subdev driver for Samsung S5K4E5 raw image sensor.
Like s5k6a3, it is also another fimc-is firmware controlled
sensor. This minimal sensor driver doesn't do any I2C communications
as its done by ISP firmware. It can be updated if needed to a
regular sensor driver by adding the I2C communication.
Signed-off-by: Arun Kumar K arun...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
.../devicetree/bindings/media/i2c/s5k4e5.txt | 43 +++
drivers/media/i2c/Kconfig |8 +
drivers/media/i2c/Makefile |1 +
drivers/media/i2c/s5k4e5.c | 361
4 files changed, 413 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/i2c/s5k4e5.txt create mode
100644 drivers/media/i2c/s5k4e5.c
...
diff --git a/drivers/media/i2c/s5k4e5.c b/drivers/media/i2c/s5k4e5.c
new file mode 100644
index 000..0a6ece6
--- /dev/null
+++ b/drivers/media/i2c/s5k4e5.c
@@ -0,0 +1,361 @@
+/*
+ * Samsung S5K4E5 image sensor driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Arun Kumar K arun...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or
modify + * it under the terms of the GNU General Public License
version 2 as + * published by the Free Software Foundation.
+ */
+
+#include linux/clk.h
+#include linux/delay.h
+#include linux/device.h
+#include linux/errno.h
+#include linux/gpio.h
+#include linux/i2c.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/of_gpio.h
+#include linux/pm_runtime.h
+#include linux/regulator/consumer.h
+#include linux/slab.h
+#include linux/videodev2.h
+#include media/v4l2-async.h
+#include media/v4l2-subdev.h
+
+#define S5K4E5_SENSOR_MAX_WIDTH2576
+#define S5K4E5_SENSOR_MAX_HEIGHT 1930
+
+#define S5K4E5_SENSOR_ACTIVE_WIDTH 2560
+#define S5K4E5_SENSOR_ACTIVE_HEIGHT1920
+
+#define S5K4E5_SENSOR_MIN_WIDTH(32 + 16)
+#define S5K4E5_SENSOR_MIN_HEIGHT (32 + 10)
+
+#define S5K4E5_DEF_WIDTH 1296
+#define S5K4E5_DEF_HEIGHT 732
+
+#define S5K4E5_DRV_NAMES5K4E5
+#define S5K4E5_CLK_NAMEmclk
+
+#define S5K4E5_NUM_SUPPLIES2
+
+#define S5K4E5_DEF_CLK_FREQ2400
+
+/**
+ * struct s5k4e5 - s5k4e5 sensor data structure
+ * @dev: pointer to this I2C client device structure
+ * @subdev: the image sensor's v4l2 subdev
+ * @pad: subdev media source pad
+ * @supplies: image sensor's voltage regulator supplies
+ * @gpio_reset: GPIO connected to the sensor's reset pin
+ * @lock: mutex protecting the structure's members below
+ * @format: media bus format at the sensor's source pad
+ */
+struct s5k4e5 {
+ struct device *dev;
+ struct v4l2_subdev subdev;
+ struct media_pad pad;
+ struct regulator_bulk_data supplies[S5K4E5_NUM_SUPPLIES];
+ int gpio_reset;
+ struct mutex lock;
+ struct v4l2_mbus_framefmt format;
+ struct clk *clock;
+ u32 clock_frequency;
+};
+
+static const char * const s5k4e5_supply_names[] = {
+ svdda,
+ svddio
+};
I'm no regulator expert, but shouldn't this list come from the DT or
platform_data? Or are these names specific to this sensor?
This is a list of regulator input (aka supply) names. In other words those
are usually names of pins of the consumer device (s5k4e5 chip in this
case) to which the regulators are connected. They are used as lookup keys
when looking up regulators, either from device tree or lookup tables.
Best regards,
Tomasz
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Re: [PATCH v7 13/13] V4L: Add driver for s5k4e5 image sensor
On Wed 21 August 2013 09:58:28 Tomasz Figa wrote:
Hi Hans,
On Wednesday 21 of August 2013 08:53:55 Hans Verkuil wrote:
On 08/21/2013 08:34 AM, Arun Kumar K wrote:
This patch adds subdev driver for Samsung S5K4E5 raw image sensor.
Like s5k6a3, it is also another fimc-is firmware controlled
sensor. This minimal sensor driver doesn't do any I2C communications
as its done by ISP firmware. It can be updated if needed to a
regular sensor driver by adding the I2C communication.
Signed-off-by: Arun Kumar K arun...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
.../devicetree/bindings/media/i2c/s5k4e5.txt | 43 +++
drivers/media/i2c/Kconfig |8 +
drivers/media/i2c/Makefile |1 +
drivers/media/i2c/s5k4e5.c | 361
4 files changed, 413 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/i2c/s5k4e5.txt create mode
100644 drivers/media/i2c/s5k4e5.c
...
diff --git a/drivers/media/i2c/s5k4e5.c b/drivers/media/i2c/s5k4e5.c
new file mode 100644
index 000..0a6ece6
--- /dev/null
+++ b/drivers/media/i2c/s5k4e5.c
@@ -0,0 +1,361 @@
+/*
+ * Samsung S5K4E5 image sensor driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Arun Kumar K arun...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or
modify + * it under the terms of the GNU General Public License
version 2 as + * published by the Free Software Foundation.
+ */
+
+#include linux/clk.h
+#include linux/delay.h
+#include linux/device.h
+#include linux/errno.h
+#include linux/gpio.h
+#include linux/i2c.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/of_gpio.h
+#include linux/pm_runtime.h
+#include linux/regulator/consumer.h
+#include linux/slab.h
+#include linux/videodev2.h
+#include media/v4l2-async.h
+#include media/v4l2-subdev.h
+
+#define S5K4E5_SENSOR_MAX_WIDTH 2576
+#define S5K4E5_SENSOR_MAX_HEIGHT 1930
+
+#define S5K4E5_SENSOR_ACTIVE_WIDTH 2560
+#define S5K4E5_SENSOR_ACTIVE_HEIGHT 1920
+
+#define S5K4E5_SENSOR_MIN_WIDTH (32 + 16)
+#define S5K4E5_SENSOR_MIN_HEIGHT (32 + 10)
+
+#define S5K4E5_DEF_WIDTH 1296
+#define S5K4E5_DEF_HEIGHT732
+
+#define S5K4E5_DRV_NAME S5K4E5
+#define S5K4E5_CLK_NAME mclk
+
+#define S5K4E5_NUM_SUPPLIES 2
+
+#define S5K4E5_DEF_CLK_FREQ 2400
+
+/**
+ * struct s5k4e5 - s5k4e5 sensor data structure
+ * @dev: pointer to this I2C client device structure
+ * @subdev: the image sensor's v4l2 subdev
+ * @pad: subdev media source pad
+ * @supplies: image sensor's voltage regulator supplies
+ * @gpio_reset: GPIO connected to the sensor's reset pin
+ * @lock: mutex protecting the structure's members below
+ * @format: media bus format at the sensor's source pad
+ */
+struct s5k4e5 {
+ struct device *dev;
+ struct v4l2_subdev subdev;
+ struct media_pad pad;
+ struct regulator_bulk_data supplies[S5K4E5_NUM_SUPPLIES];
+ int gpio_reset;
+ struct mutex lock;
+ struct v4l2_mbus_framefmt format;
+ struct clk *clock;
+ u32 clock_frequency;
+};
+
+static const char * const s5k4e5_supply_names[] = {
+ svdda,
+ svddio
+};
I'm no regulator expert, but shouldn't this list come from the DT or
platform_data? Or are these names specific to this sensor?
This is a list of regulator input (aka supply) names. In other words those
are usually names of pins of the consumer device (s5k4e5 chip in this
case) to which the regulators are connected. They are used as lookup keys
when looking up regulators, either from device tree or lookup tables.
How does that work if you have two of these sensors? E.g. in a stereo-camera?
Can the regulator subsystem map those pins to the correct regulators?
Again, sorry for my ignorance in this area as I've never used it. I just
want to make sure this information is stored in the right place.
Regards,
Hans
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re: [media] exynos4-is: Add Exynos5250 SoC support to fimc-lite driver
Hello Sylwester Nawrocki,
This is a semi-automatic email about new static checker warnings.
The patch 086eca2905d0: [media] exynos4-is: Add Exynos5250 SoC
support to fimc-lite driver from Jun 14, 2013, leads to the
following Smatch complaint:
drivers/media/platform/exynos4-is/fimc-lite.c:1521 fimc_lite_probe()
error: we previously assumed 'dev-of_node' could be null (see line
1511)
drivers/media/platform/exynos4-is/fimc-lite.c
1510
1511 if (dev-of_node) {
Existing check.
1512 of_id = of_match_node(flite_of_match, dev-of_node);
1513 if (of_id)
1514 drv_data = (struct flite_drvdata *)of_id-data;
1515 fimc-index = of_alias_get_id(dev-of_node,
fimc-lite);
1516 }
1517
1518 if (!drv_data || fimc-index = drv_data-num_instances ||
1519 fimc-index 0) {
1520 dev_err(dev, Wrong %s node alias\n,
1521 dev-of_node-full_name);
^^
Patch adds this dereference.
1522 return -EINVAL;
1523 }
regards,
dan carpenter
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Re: [PATCH V2 2/2] ARM: dts: Add dwmmc nodes in SOC specific dts file
--- Original Message ---
Sender : yuvaraj...@gmail.comyuvaraj...@gmail.com
Date : Aug 21, 2013 12:07 (GMT+05:30)
Title : [PATCH V2 2/2] ARM: dts: Add dwmmc nodes in SOC specific dts file
From: Yuvaraj Kumar C D
Exynos5 series SOC's have different versions of DWMMC controller.
So dwmmc device nodes moved from Exynos5 SOC's common dts file to
SOC specific dts file.
changes since V1:
1.disable node by status = disabled in SOC file
2.enable node by status = okay in board specific file
Signed-off-by: Yuvaraj Kumar C D
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 10 ++
arch/arm/boot/dts/exynos5250.dtsi | 16
2 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 2538b32..bd19d55d 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -141,6 +141,7 @@
};
dwmmc0@1220 {
+ status = okay;
num-slots = 1;
supports-highspeed;
broken-cd;
@@ -158,11 +159,8 @@
};
};
- dwmmc1@1221 {
- status = disabled;
- };
-
dwmmc2@1222 {
+ status = okay;
num-slots = 1;
supports-highspeed;
fifo-depth = 0x80;
@@ -180,10 +178,6 @@
};
};
- dwmmc3@1223 {
- status = disabled;
- };
-
spi_0: spi@12d2 {
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 1eec646..b1b6f61 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -387,21 +387,36 @@
};
dwmmc_0: dwmmc0@1220 {
+ compatible = samsung,exynos5250-dw-mshc;
+ interrupts = 0 75 0;
+ #address-cells = 1;
+ #size-cells = 0;
reg = 0x1220 0x1000;
clocks = clock 280, clock 139;
clock-names = biu, ciu;
+ status = disabled;
};
dwmmc_1: dwmmc1@1221 {
+ compatible = samsung,exynos5250-dw-mshc;
+ interrupts = 0 76 0;
+ #address-cells = 1;
+ #size-cells = 0;
reg = 0x1221 0x1000;
clocks = clock 281, clock 140;
clock-names = biu, ciu;
+ status = disabled;
};
dwmmc_2: dwmmc2@1222 {
+ compatible = samsung,exynos5250-dw-mshc;
+ interrupts = 0 77 0;
+ #address-cells = 1;
+ #size-cells = 0;
reg = 0x1222 0x1000;
clocks = clock 282, clock 141;
clock-names = biu, ciu;
+ status = disabled;
};
dwmmc_3: dwmmc3@1223 {
@@ -412,6 +427,7 @@
#size-cells = 0;
clocks = clock 283, clock 142;
clock-names = biu, ciu;
+ status = disabled;
};
i2s0: i2s@0383 {
Looks Ok to me.
Reviewed By: Girish K S ks.g...@samsung.com
--
1.7.9.5
Re: [PATCH v7 13/13] V4L: Add driver for s5k4e5 image sensor
Hi Hans,
On Wed, Aug 21, 2013 at 1:54 PM, Hans Verkuil hverk...@xs4all.nl wrote:
On Wed 21 August 2013 09:58:28 Tomasz Figa wrote:
Hi Hans,
On Wednesday 21 of August 2013 08:53:55 Hans Verkuil wrote:
On 08/21/2013 08:34 AM, Arun Kumar K wrote:
This patch adds subdev driver for Samsung S5K4E5 raw image sensor.
Like s5k6a3, it is also another fimc-is firmware controlled
sensor. This minimal sensor driver doesn't do any I2C communications
as its done by ISP firmware. It can be updated if needed to a
regular sensor driver by adding the I2C communication.
Signed-off-by: Arun Kumar K arun...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
.../devicetree/bindings/media/i2c/s5k4e5.txt | 43 +++
drivers/media/i2c/Kconfig |8 +
drivers/media/i2c/Makefile |1 +
drivers/media/i2c/s5k4e5.c | 361
4 files changed, 413 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/i2c/s5k4e5.txt create mode
100644 drivers/media/i2c/s5k4e5.c
...
diff --git a/drivers/media/i2c/s5k4e5.c b/drivers/media/i2c/s5k4e5.c
new file mode 100644
index 000..0a6ece6
--- /dev/null
+++ b/drivers/media/i2c/s5k4e5.c
@@ -0,0 +1,361 @@
+/*
+ * Samsung S5K4E5 image sensor driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Arun Kumar K arun...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or
modify + * it under the terms of the GNU General Public License
version 2 as + * published by the Free Software Foundation.
+ */
+
+#include linux/clk.h
+#include linux/delay.h
+#include linux/device.h
+#include linux/errno.h
+#include linux/gpio.h
+#include linux/i2c.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/of_gpio.h
+#include linux/pm_runtime.h
+#include linux/regulator/consumer.h
+#include linux/slab.h
+#include linux/videodev2.h
+#include media/v4l2-async.h
+#include media/v4l2-subdev.h
+
+#define S5K4E5_SENSOR_MAX_WIDTH 2576
+#define S5K4E5_SENSOR_MAX_HEIGHT 1930
+
+#define S5K4E5_SENSOR_ACTIVE_WIDTH 2560
+#define S5K4E5_SENSOR_ACTIVE_HEIGHT 1920
+
+#define S5K4E5_SENSOR_MIN_WIDTH (32 + 16)
+#define S5K4E5_SENSOR_MIN_HEIGHT (32 + 10)
+
+#define S5K4E5_DEF_WIDTH 1296
+#define S5K4E5_DEF_HEIGHT732
+
+#define S5K4E5_DRV_NAME S5K4E5
+#define S5K4E5_CLK_NAME mclk
+
+#define S5K4E5_NUM_SUPPLIES 2
+
+#define S5K4E5_DEF_CLK_FREQ 2400
+
+/**
+ * struct s5k4e5 - s5k4e5 sensor data structure
+ * @dev: pointer to this I2C client device structure
+ * @subdev: the image sensor's v4l2 subdev
+ * @pad: subdev media source pad
+ * @supplies: image sensor's voltage regulator supplies
+ * @gpio_reset: GPIO connected to the sensor's reset pin
+ * @lock: mutex protecting the structure's members below
+ * @format: media bus format at the sensor's source pad
+ */
+struct s5k4e5 {
+ struct device *dev;
+ struct v4l2_subdev subdev;
+ struct media_pad pad;
+ struct regulator_bulk_data supplies[S5K4E5_NUM_SUPPLIES];
+ int gpio_reset;
+ struct mutex lock;
+ struct v4l2_mbus_framefmt format;
+ struct clk *clock;
+ u32 clock_frequency;
+};
+
+static const char * const s5k4e5_supply_names[] = {
+ svdda,
+ svddio
+};
I'm no regulator expert, but shouldn't this list come from the DT or
platform_data? Or are these names specific to this sensor?
This is a list of regulator input (aka supply) names. In other words those
are usually names of pins of the consumer device (s5k4e5 chip in this
case) to which the regulators are connected. They are used as lookup keys
when looking up regulators, either from device tree or lookup tables.
How does that work if you have two of these sensors? E.g. in a stereo-camera?
Can the regulator subsystem map those pins to the correct regulators?
Again, sorry for my ignorance in this area as I've never used it. I just
want to make sure this information is stored in the right place.
There are two regulator supplies needed for this sensor, and these pin names
are just used in the driver to differentiate them.
From the DT, we pass regulator node phandles with these properties
(supply names) which the driver uses.
Regards
Arun
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Re: [PATCH v7 13/13] V4L: Add driver for s5k4e5 image sensor
On 08/21/2013 10:24 AM, Hans Verkuil wrote:
+static const char * const s5k4e5_supply_names[] = {
+ svdda,
+ svddio
+};
I'm no regulator expert, but shouldn't this list come from the DT or
platform_data? Or are these names specific to this sensor?
This is a list of regulator input (aka supply) names. In other words those
are usually names of pins of the consumer device (s5k4e5 chip in this
case) to which the regulators are connected. They are used as lookup keys
when looking up regulators, either from device tree or lookup tables.
How does that work if you have two of these sensors? E.g. in a stereo-camera?
Can the regulator subsystem map those pins to the correct regulators?
Again, sorry for my ignorance in this area as I've never used it. I just
want to make sure this information is stored in the right place.
The _voltage regulator supply names_ are fixed but _voltage regulator_
is matched with a consumer device based on the supply name and name of
the consumer device. See usage of struct regulator_consumer_supply, e.g.
in arch/arm/mach-s5pv210/mach-goni.c board file. This is an example of
non-dt system, and something that would presumably be created by a driver
like em28xx if it wanted to use that sensor. I.e. em28xx would first
need to create a voltage regulator device and then pass in a
struct regulator_init_data the list of voltage supply definitions for
the consumers to be able to use this regulator.
In case of device tree the voltage supplies are specified in
a DT node, which can be referenced by subsystems/drivers through
struct device::of_node.
reg_a: voltage-regulator-a {
compatible = regulator-fixed;
regulator-name = REG_5V_A;
regulator-min-microvolt = 500;
regulator-max-microvolt = 500;
gpio = ...;
...
};
reg_b: voltage-regulator-b {
compatible = regulator-fixed;
regulator-name = REG_3.3V_B;
regulator-min-microvolt = 330;
regulator-max-microvolt = 330;
gpio = ...;
...
};
s5k4e5@20 {
compatible = samsung,s5k4e5;
reg = 0x20;
...
svdda-supply = reg_a;
svddio-supply = reg_b;
...
};
The regulator supply names are part of name of the property defining
a voltage regulator for a device. Properties in form of
[supply_name]-supply are parsed by the regulator core when consumer
device driver calls regulator_get(). This way drivers don't need to
care whether the system is booted from Device Tree or not. They just
keep using the regulator API and the regulator supply lookup is done
the the core based on data in a board file or in device tree blob.
This is similar to the clock API operation, except that clkdev entries
are usually defined per SOC/MCU rather than per board.
I hope it helps. I looked yesterday at the em28xx driver. Do you happen
to know if there is a schematic for one of devices this driver supports ?
Sorry, I didn't dig to hard yet.
At first sight I thought it may look a bit problematic and require
significant amount of code to define regulators for the all supported
sensors by this driver, should it be made to work with sensors that
are currently known to be used only in embedded systems and use the
regulators API. However it should be as simple as defining at least one
regulator device and attaching regulator supply list definition for all
supported sensors. Thus not that scary at all. And the subdev drivers
can continue to use regulator API, without a need for any hacks making
it optional through e.g. platform_data flag. And IMO if the regulator
API is disabled currently by some x86 distros it should be enabled,
as long as some drivers need it.
--
Regards,
Sylwester
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Re: [PATCH v7 13/13] V4L: Add driver for s5k4e5 image sensor
On 08/21/2013 11:13 AM, Sylwester Nawrocki wrote:
On 08/21/2013 10:24 AM, Hans Verkuil wrote:
+static const char * const s5k4e5_supply_names[] = {
+ svdda,
+ svddio
+};
I'm no regulator expert, but shouldn't this list come from the DT or
platform_data? Or are these names specific to this sensor?
This is a list of regulator input (aka supply) names. In other words those
are usually names of pins of the consumer device (s5k4e5 chip in this
case) to which the regulators are connected. They are used as lookup keys
when looking up regulators, either from device tree or lookup tables.
How does that work if you have two of these sensors? E.g. in a stereo-camera?
Can the regulator subsystem map those pins to the correct regulators?
Again, sorry for my ignorance in this area as I've never used it. I just
want to make sure this information is stored in the right place.
The _voltage regulator supply names_ are fixed but _voltage regulator_
is matched with a consumer device based on the supply name and name of
the consumer device. See usage of struct regulator_consumer_supply, e.g.
in arch/arm/mach-s5pv210/mach-goni.c board file. This is an example of
non-dt system, and something that would presumably be created by a driver
like em28xx if it wanted to use that sensor. I.e. em28xx would first
need to create a voltage regulator device and then pass in a
struct regulator_init_data the list of voltage supply definitions for
the consumers to be able to use this regulator.
In case of device tree the voltage supplies are specified in
a DT node, which can be referenced by subsystems/drivers through
struct device::of_node.
reg_a: voltage-regulator-a {
compatible = regulator-fixed;
regulator-name = REG_5V_A;
regulator-min-microvolt = 500;
regulator-max-microvolt = 500;
gpio = ...;
...
};
reg_b: voltage-regulator-b {
compatible = regulator-fixed;
regulator-name = REG_3.3V_B;
regulator-min-microvolt = 330;
regulator-max-microvolt = 330;
gpio = ...;
...
};
s5k4e5@20 {
compatible = samsung,s5k4e5;
reg = 0x20;
...
svdda-supply = reg_a;
svddio-supply = reg_b;
...
};
I forgot to mention that each of the two sensors would of course have
its corresponding DT node, but since they both have same slave address
would likely be attached to separate I2C bus controllers, e.g.
/* I2C bus controller node */
i2c-gpio-0 {
compatible = i2c-gpio;
gpios = ...;
...
s5k4e5@20 {
compatible = samsung,s5k4e5;
reg = 0x20;
...
svdda-supply = reg_a;
svddio-supply = reg_b;
...
};
};
i2c-gpio-1 {
compatible = i2c-gpio;
gpios = ...;
...
s5k4e5@20 {
compatible = samsung,s5k4e5;
reg = 0x20;
...
svdda-supply = reg_a;
svddio-supply = reg_b;
...
};
};
So these sensors have same regulator supply names but different i2c_client
(device) names, since they are children of different I2C bus adapters.
The regulator supply names are part of name of the property defining
a voltage regulator for a device. Properties in form of
[supply_name]-supply are parsed by the regulator core when consumer
device driver calls regulator_get(). This way drivers don't need to
care whether the system is booted from Device Tree or not. They just
keep using the regulator API and the regulator supply lookup is done
the the core based on data in a board file or in device tree blob.
This is similar to the clock API operation, except that clkdev entries
are usually defined per SOC/MCU rather than per board.
I hope it helps. I looked yesterday at the em28xx driver. Do you happen
to know if there is a schematic for one of devices this driver supports ?
Sorry, I didn't dig to hard yet.
At first sight I thought it may look a bit problematic and require
significant amount of code to define regulators for the all supported
sensors by this driver, should it be made to work with sensors that
are currently known to be used only in embedded systems and use the
regulators API. However it should be as simple as defining at least one
regulator device and attaching regulator supply list definition for all
supported sensors. Thus not that scary at all. And the subdev drivers
can continue to use regulator API, without a need for any hacks making
it optional through e.g. platform_data flag. And IMO if the regulator
API is disabled currently by some x86 distros it should be enabled,
as long as some drivers need it.
--
Regards,
[PATCH] i2c: exynos5: add High Speed I2C controller driver
Adds support for High Speed I2C driver found in Exynos5 and
later SoCs from Samsung.
Highspeed mode is a minor change in the i2c protocol.
Starts with
1. start condition,
2. 8-bit master ID code (1xxx)
3. followed by a NACK bit
Once the above conditions are met, the bus is now operates in highspeed mode.
The rest of the I2C protocol applies the same.
Driver only supports Device Tree method.
Changes since v1:
1. Added FIFO functionality
2. Added High speed mode functionality
3. Remove SMBUS_QUICK
4. Remove the debugfs functionality
5. Use devm_* functions where ever possible
6. Driver is free from GPIO configs
7. Use OF data string clock-frequency to get the bus operating frequencies
8. Split the clock divisor calculation function
9. Add resets for the failed transacton cases
10. Removed retries as core does retries if -EAGAIN is returned
11. Removed mode from device tree info (use speed to distinguish
the mode of operation)
12. Use wait_for_completion_timeout as the interruptible case is not tested well
13. few other bug fixes and cosmetic changes
14. Removed the untested runtime_pm code
15. Removed the retries as core does that
16. Use adap.nr instead of alias
17. Added spinlocks around the irq code
18. Use i2c_add_numbered_adapter() instead of using aliases
Signed-off-by: Taekgyun Ko taeggyun...@samsung.com
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Reviewed-by: Simon Glass s...@google.com
Tested-by: Andrew Bresticker abres...@google.com
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
Signed-off-by: Andrew Bresticker abres...@google.com
---
Wolfram and Thomas Figa thanks for reviewing the code.
Changes since v10:
1. Remove the incomplete runtime_pm code
2. Correct the error checks as suggested by Thomas
3. Use i2c_add_numbered_adapter() as suggested
4. Modified the irq routine to handle the specific interrupts
5. Added spinlocks around the irq code
6. Remove the mode of operation field from device tree node and use the
clock-frequency to decide the mode.
.../devicetree/bindings/i2c/i2c-exynos5.txt| 44 ++
drivers/i2c/busses/Kconfig |7 +
drivers/i2c/busses/Makefile|1 +
drivers/i2c/busses/i2c-exynos5.c | 799
4 files changed, 851 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
create mode 100644 drivers/i2c/busses/i2c-exynos5.c
diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
new file mode 100644
index 000..805e018
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
@@ -0,0 +1,44 @@
+* Samsung's High Speed I2C controller
+
+The Samsung's High Speed I2C controller is used to interface with I2C devices
+at various speeds ranging from 100khz to 3.4Mhz.
+
+Required properties:
+ - compatible: value should be.
+ - samsung,exynos5-hsi2c, for i2c compatible with exynos5 hsi2c.
+ - reg: physical base address of the controller and length of memory mapped
+region.
+ - interrupts: interrupt number to the cpu.
+ - #address-cells: always 1 (for i2c addresses)
+ - #size-cells: always 0
+
+ - Pinctrl:
+- pinctrl-0: Pin control group to be used for this controller.
+- pinctrl-names: Should contain only one value - default.
+
+Optional properties:
+ - clock-frequency: Desired operating frequency in Hz of the bus.
+- If not specified, the default value is 100khz in fast-speed mode and
+ 1Mhz in high-speed mode.
+- If specified, The bus operates in high-speed mode only if the
+ clock-frequency is = 1Mhz.
+
+Example:
+
+hsi2c@12ca {
+ compatible = samsung,exynos5-hsi2c;
+ reg = 0x12ca 0x100;
+ interrupts = 56;
+ clock-frequency = 10;
+
+ pinctrl-0 = i2c4_bus;
+ pinctrl-names = default;
+
+ #address-cells = 1;
+ #size-cells = 0;
+
+ s2mps11_pmic@66 {
+ compatible = samsung,s2mps11-pmic;
+ reg = 0x66;
+ };
+};
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index fcdd321..69b1848 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -436,6 +436,13 @@ config I2C_EG20T
ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.
ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.
+config I2C_EXYNOS5
+ tristate Exynos5 high-speed I2C driver
+ depends on ARCH_EXYNOS5 OF
+ help
+ Say Y here to include support for high-speed I2C controller in the
+ Exynos5 based Samsung SoCs.
+
config I2C_GPIO
tristate GPIO-based bitbanging I2C
depends on GPIOLIB
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index d00997f..d1ad371 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -42,6 +42,7 @@ i2c-designware-platform-objs :=
Re: [PATCH 4/8] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
Hi Yuvaraj,
On Wednesday 21 of August 2013 12:05:33 Yuvaraj Kumar C D wrote:
This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.
Is this patch a v3 of [1]?
[1] - http://thread.gmane.org/gmane.linux.kernel.mmc/21981
Why it is named patch 4/8?
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
---
.../devicetree/bindings/mmc/exynos-dw-mshc.txt |2 +
arch/arm/boot/dts/exynos5420-smdk5420.dts | 41
arch/arm/boot/dts/exynos5420.dtsi
| 33 3 files changed, 76 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt index
6d1c098..84cd56f 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -16,6 +16,8 @@ Required Properties:
specific extensions.
- samsung,exynos5250-dw-mshc: for controllers with Samsung Exynos5250
specific extensions.
+ - samsung,exynos5420-dw-mshc: for controllers with Samsung Exynos5420
+ specific extensions.
* samsung,dw-mshc-ciu-div: Specifies the divider value for the card
interface unit (ciu) clock. This property is applicable only for Exynos5
SoC's and diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 08607df..4530700
100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -30,4 +30,45 @@
clock-frequency = 2400;
};
};
+
+ dwmmc0@1220 {
+ num-slots = 1;
+ broken-cd;
+ bypass-smu;
+ supports-highspeed;
+ fifo-depth = 0x80;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 0 4;
+ samsung,dw-mshc-ddr-timing = 0 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8;
See below.
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ };
+ };
+
+ dwmmc1@1221 {
+ status = disabled;
You should rather keep things the other way around. A board dts shouldn't
care about peripherals it doesn't use, so any peripheral requiring board-
specific data in its node should have status set as disabled at top level
and then overridden to okay at level in which it has all the required
properties to operate (in board dts in this case).
+ };
+
+ dwmmc2@1222 {
+ num-slots = 1;
+ supports-highspeed;
+ fifo-depth = 0x80;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd2_clk sd2_cmd sd2_cd sd2_bus4;
Here would go status = okay.
+
+ slot@0 {
+ reg = 0;
+ bus-width = 4;
+ };
+ };
+
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi index 9e90d1e..8559aa8 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -19,6 +19,9 @@
compatible = samsung,exynos5420;
aliases {
+ mshc0 = dwmmc_0;
+ mshc1 = dwmmc_1;
+ mshc2 = dwmmc_2;
pinctrl0 = pinctrl_0;
pinctrl1 = pinctrl_1;
pinctrl2 = pinctrl_2;
@@ -65,6 +68,36 @@
#clock-cells = 1;
};
+ dwmmc_0: dwmmc0@1220 {
+ compatible = samsung,exynos5420-dw-mshc;
+ interrupts = 0 75 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1220 0x2000;
+ clocks = clock 351, clock 132;
+ clock-names = biu, ciu;
Here would go status = disabled in this case.
+ };
+
+ dwmmc_1: dwmmc1@1221 {
+ compatible = samsung,exynos5420-dw-mshc;
+ interrupts = 0 76 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1221 0x2000;
+ clocks = clock 352, clock 133;
+ clock-names = biu, ciu;
...
+ };
+
+ dwmmc_2: dwmmc2@1222 {
+ compatible = samsung,exynos5420-dw-mshc;
+ interrupts = 0 77 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1222 0x2000;
+ clocks = clock 353, clock 134;
+ clock-names = biu, ciu;
...
Best regards,
Tomasz
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Re: [PATCH V2] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
Hi Yuvaraj,
On Wednesday 21 of August 2013 12:13:53 Yuvaraj Kumar C D wrote:
This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.
What are the difference between both versions? Is there a patch adding the
new compatible to the driver somewhere?
changes since V1:
1.disable node by status = disabled in SOC file
2.enable node by status = okay in board specific file
Ahh, so you fixed this already in this version, thanks. Haven't noticed
this patch at first and commented on previous one. Sorry for the noise.
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
---
.../devicetree/bindings/mmc/exynos-dw-mshc.txt |2 ++
arch/arm/boot/dts/exynos5420-smdk5420.dts | 38
arch/arm/boot/dts/exynos5420.dtsi
| 36 +++ 3 files changed, 76 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt index
6d1c098..84cd56f 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -16,6 +16,8 @@ Required Properties:
specific extensions.
- samsung,exynos5250-dw-mshc: for controllers with Samsung Exynos5250
specific extensions.
+ - samsung,exynos5420-dw-mshc: for controllers with Samsung Exynos5420
+ specific extensions.
* samsung,dw-mshc-ciu-div: Specifies the divider value for the card
interface unit (ciu) clock. This property is applicable only for Exynos5
SoC's and diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts index bafba25..6e65278
100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -31,6 +31,44 @@
};
};
+ dwmmc0@1220 {
+ status = okay;
+ num-slots = 1;
You don't have to specify this property if there is only one slot. Also are
you sure that this is a board specific property?
+ broken-cd;
+ bypass-smu;
This property doesn't seem to be documented nor used anywhere.
+ supports-highspeed;
Is it a board specific property?
+ fifo-depth = 0x80;
Ditto.
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 0 4;
+ samsung,dw-mshc-ddr-timing = 0 2;
Are the above three properties really board-specific?
Same for remaining nodes.
Best regards,
Tomasz
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Re: [PATCH V2 1/2] ARM: dts: remove dwmmc nodes from exynos5 common dts file.
Hi Yuvaraj, On Wednesday 21 of August 2013 12:07:38 yuvaraj...@gmail.com wrote: From: Yuvaraj Kumar C D yuvaraj...@samsung.com Exynos5 series SOC's 5250 and 5420 have different versions of DWMMC controller.So there is a new compatible string to distinguish between them.So these nodes should be moved out of Exynos5 series common device tree source. This series should be split in a different way, because patch 1/2 breaks dwmmc on Exynos5250 and only patch 2/2 fixes this, so bisection is broken. Also patch 2/2 contains two logically separate changes - moving dwmmc nodes and making status disabled by default. Those should be in separate patches. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2 1/2] ARM: dts: remove dwmmc nodes from exynos5 common dts file.
On Wed, Aug 21, 2013 at 4:04 PM, Tomasz Figa t.f...@samsung.com wrote: Hi Yuvaraj, On Wednesday 21 of August 2013 12:07:38 yuvaraj...@gmail.com wrote: From: Yuvaraj Kumar C D yuvaraj...@samsung.com Exynos5 series SOC's 5250 and 5420 have different versions of DWMMC controller.So there is a new compatible string to distinguish between them.So these nodes should be moved out of Exynos5 series common device tree source. This series should be split in a different way, because patch 1/2 breaks dwmmc on Exynos5250 and only patch 2/2 fixes this, so bisection is broken. will make a single patch and resend. Also patch 2/2 contains two logically separate changes - moving dwmmc nodes and making status disabled by default. Those should be in separate patches. will separate patch2/2 and resend. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v5 0/4] mmc: dw_mmc: fixes for suspend/resume on exynos
Hi Doug, Do you have any update for this series? Please let me know. Thanks, Seungwon Jeon On Sat, August 10, 2013, Doug Anderson wrote: This series of patches addresses some suspend/resume problems with dw_mmc on exynos platforms, espeically exynos5420. Since suspend/resume is not fully working on ToT Linux (v3.11-rc4) on exynos5250-snow, this series was tested against the current ToT ChromeOS 3.8 tree. I have confirmed basic booting and eMMC / SD card usage (and compiling, honest!) against ToT Linux. I have received confirmation from Samsung that the problem solved is a silicon errata on exynos5420 and that this is a good fix. Changes in v5: - Remove force_clkinit as per Jaehoon. - Update commit message to (hopefully) be clearer. - Cleaned up dw_mci_exynos_resume_noirq() comment as per Seungwon. - Don't memcpy dev_pm_ops structure, define a new one. Changes in v4: - Take Seungwon's suggestion and don't add any dw_mmc-pltfm code. Changes in v3: - Add freeze/thaw and poweroff/restore noirq entries. Changes in v2: - Fix typo (some - come) - Use ~0 instead of 0x; add comment about value - Use suspend_noirq as per James Hogan. Doug Anderson (4): mmc: dw_mmc: Invalidate cache of current_speed after suspend/resume mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT mmc: dw_mmc: Always setup the bus after suspend/resume mmc: dw_mmc: Set timeout to max upon resume drivers/mmc/host/dw_mmc-exynos.c | 56 +++- drivers/mmc/host/dw_mmc.c| 21 ++- 2 files changed, 69 insertions(+), 8 deletions(-) -- 1.8.3 -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 4/8] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
On Wed, Aug 21, 2013 at 3:40 PM, Tomasz Figa t.f...@samsung.com wrote:
Hi Yuvaraj,
On Wednesday 21 of August 2013 12:05:33 Yuvaraj Kumar C D wrote:
This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.
Is this patch a v3 of [1]?
[1] - http://thread.gmane.org/gmane.linux.kernel.mmc/21981
Why it is named patch 4/8?
Please ignore this patch. patch 4/8 was accidental.
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
---
.../devicetree/bindings/mmc/exynos-dw-mshc.txt |2 +
arch/arm/boot/dts/exynos5420-smdk5420.dts | 41
arch/arm/boot/dts/exynos5420.dtsi
| 33 3 files changed, 76 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt index
6d1c098..84cd56f 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -16,6 +16,8 @@ Required Properties:
specific extensions.
- samsung,exynos5250-dw-mshc: for controllers with Samsung Exynos5250
specific extensions.
+ - samsung,exynos5420-dw-mshc: for controllers with Samsung Exynos5420
+ specific extensions.
* samsung,dw-mshc-ciu-div: Specifies the divider value for the card
interface unit (ciu) clock. This property is applicable only for Exynos5
SoC's and diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 08607df..4530700
100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -30,4 +30,45 @@
clock-frequency = 2400;
};
};
+
+ dwmmc0@1220 {
+ num-slots = 1;
+ broken-cd;
+ bypass-smu;
+ supports-highspeed;
+ fifo-depth = 0x80;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 0 4;
+ samsung,dw-mshc-ddr-timing = 0 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8;
See below.
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ };
+ };
+
+ dwmmc1@1221 {
+ status = disabled;
You should rather keep things the other way around. A board dts shouldn't
care about peripherals it doesn't use, so any peripheral requiring board-
specific data in its node should have status set as disabled at top level
and then overridden to okay at level in which it has all the required
properties to operate (in board dts in this case).
+ };
+
+ dwmmc2@1222 {
+ num-slots = 1;
+ supports-highspeed;
+ fifo-depth = 0x80;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd2_clk sd2_cmd sd2_cd sd2_bus4;
Here would go status = okay.
+
+ slot@0 {
+ reg = 0;
+ bus-width = 4;
+ };
+ };
+
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi index 9e90d1e..8559aa8 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -19,6 +19,9 @@
compatible = samsung,exynos5420;
aliases {
+ mshc0 = dwmmc_0;
+ mshc1 = dwmmc_1;
+ mshc2 = dwmmc_2;
pinctrl0 = pinctrl_0;
pinctrl1 = pinctrl_1;
pinctrl2 = pinctrl_2;
@@ -65,6 +68,36 @@
#clock-cells = 1;
};
+ dwmmc_0: dwmmc0@1220 {
+ compatible = samsung,exynos5420-dw-mshc;
+ interrupts = 0 75 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1220 0x2000;
+ clocks = clock 351, clock 132;
+ clock-names = biu, ciu;
Here would go status = disabled in this case.
+ };
+
+ dwmmc_1: dwmmc1@1221 {
+ compatible = samsung,exynos5420-dw-mshc;
+ interrupts = 0 76 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1221 0x2000;
+ clocks = clock 352, clock 133;
+ clock-names = biu, ciu;
...
+ };
+
+ dwmmc_2: dwmmc2@1222 {
+ compatible = samsung,exynos5420-dw-mshc;
+ interrupts = 0 77 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1222 0x2000;
+ clocks = clock
Re: [PATCH 10/16] clk: samsung: pll: Add support for rate configuration of PLL45xx
Hi Tomasz,
On Tue, Aug 20, 2013 at 11:01 PM, Tomasz Figa t.f...@samsung.com wrote:
This patch implements round_rate and set_rate callbacks of PLL45xx
driver to allow reconfiguration of PLL at runtime.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/clk/samsung/clk-pll.c | 109
+-
drivers/clk/samsung/clk-pll.h | 10
2 files changed, 118 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index b0398d2..cb971cb 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -10,9 +10,12 @@
*/
#include linux/errno.h
+#include linux/hrtimer.h
#include clk.h
#include clk-pll.h
+#define PLL_TIMEOUT_MS 10
+
struct samsung_clk_pll {
struct clk_hw hw;
void __iomem*lock_reg;
@@ -272,13 +275,20 @@ static const struct clk_ops samsung_pll36xx_clk_min_ops
= {
/*
* PLL45xx Clock Type
*/
+#define PLL4502_LOCK_FACTOR400
+#define PLL4508_LOCK_FACTOR240
#define PLL45XX_MDIV_MASK (0x3FF)
#define PLL45XX_PDIV_MASK (0x3F)
#define PLL45XX_SDIV_MASK (0x7)
+#define PLL45XX_AFC_MASK (0x1F)
#define PLL45XX_MDIV_SHIFT (16)
#define PLL45XX_PDIV_SHIFT (8)
#define PLL45XX_SDIV_SHIFT (0)
+#define PLL45XX_AFC_SHIFT (0)
+
+#define PLL45XX_ENABLE BIT(31)
+#define PLL45XX_LOCKED BIT(29)
static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
@@ -301,8 +311,100 @@ static unsigned long samsung_pll45xx_recalc_rate(struct
clk_hw *hw,
return (unsigned long)fvco;
}
+static bool samsung_pll45xx_mp_change(u32 pll_con0, u32 pll_con1,
+ const struct samsung_pll_rate_table *rate)
+{
+ u32 old_mdiv, old_pdiv, old_afc;
+
+ old_mdiv = (pll_con0 PLL45XX_MDIV_SHIFT) PLL45XX_MDIV_MASK;
+ old_pdiv = (pll_con0 PLL45XX_PDIV_SHIFT) PLL45XX_PDIV_MASK;
+ old_afc = (pll_con1 PLL45XX_AFC_SHIFT) PLL45XX_AFC_MASK;
old_afc doesn't required in this function.
+
+ return (old_mdiv != rate-mdiv || old_pdiv != rate-pdiv);
+}
+
+static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ const struct samsung_pll_rate_table *rate;
+ u32 con0, con1;
+ ktime_t start;
+
+ /* Get required rate settings from table */
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err(%s: Invalid rate : %lu for pll clk %s\n, __func__,
+ drate, __clk_get_name(hw-clk));
+ return -EINVAL;
+ }
+
+ con0 = __raw_readl(pll-con_reg);
+ con1 = __raw_readl(pll-con_reg + 0x4);
+
+ if (!(samsung_pll45xx_mp_change(con0, con1, rate))) {
+ /* If only s change, change just s value only*/
+ con0 = ~(PLL45XX_SDIV_MASK PLL45XX_SDIV_SHIFT);
+ con0 |= rate-sdiv PLL45XX_SDIV_SHIFT;
+ __raw_writel(con0, pll-con_reg);
+
+ return 0;
+ }
+
+ /* Set PLL PMS values. */
+ con0 = ~((PLL45XX_MDIV_MASK PLL45XX_MDIV_SHIFT) |
+ (PLL45XX_PDIV_MASK PLL45XX_PDIV_SHIFT) |
+ (PLL45XX_SDIV_MASK PLL45XX_SDIV_SHIFT));
+ con0 |= (rate-mdiv PLL45XX_MDIV_SHIFT) |
+ (rate-pdiv PLL45XX_PDIV_SHIFT) |
+ (rate-sdiv PLL45XX_SDIV_SHIFT);
+
+ /* Set PLL AFC value. */
+ con1 = __raw_readl(pll-con_reg + 0x4);
+ con1 = ~(PLL45XX_AFC_MASK PLL45XX_AFC_SHIFT);
+ con1 |= (rate-afc PLL45XX_AFC_SHIFT);
+
Do we need to take care of AFC_ENB also, if we are using AFC ?
Regards,
Yadwinder
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Re: [PATCH] irqchip: gic: Allow setting affinity to offline CPUs
[Copying Daniel] On Tuesday 20 of August 2013 15:39:17 Stephen Boyd wrote: On 08/21, Tomasz Figa wrote: On Tuesday 20 of August 2013 22:14:42 Russell King - ARM Linux wrote: On Tue, Aug 20, 2013 at 06:11:10PM +0200, Tomasz Figa wrote: Sometimes it is necessary to fix interrupt affinity to an offline CPU, for example in initialization of local timers. This patch modifies .set_affinity() operation of irq-gic driver to fall back to any possible CPU if no online CPU can be found in requested CPU mask. Err, this is a bad idea. If a CPU is offline, then it must not respond to interrupts. If you bind an interrupt to an offline CPU, and that device asserts its interrupt, what happens? It doesn't get serviced until that CPU comes back online, which may be a very long time. If, for example, that is your network device, it would mean your network stops operating. Worse, the network layer will time out and reset the ethernet device, trying to get things working (which it won't.) I think how I used to handle this case prior to genirq is that I fell back to any online CPU if the interrupt ended up only routed to offline CPUs, but when an offline CPU comes back, it could then be re-routed back to that CPU. In other words, the mask change was non-destructive. I think with genirq, such mask changes are destructive. Yes, that's correct. Although if you _explicitly_ request the interrupt to be routed to an offline CPU (i.e. only offline CPUs have bits set in passed cpumask), is it an error? There is at least one irqchip that does not check received cpumask for this (metag) and I don't see any documentation saying what should happen in this case in .set_affinity operation. Still, if you have any better solution for the original problem (broken Exynos4210 local timers, due to failing irq_set_affinity()), then I'd appreciate it, as I don't like the one from this patch too much either. One solution might be to change the irq affinity after the CPU is marked online via the hotplug notifier chain. For a short period of time the timer interrupt will go to a different CPU but I don't see how that is a problem. After initial testing, this seems to work, but but it still seems a little hackish. I'd like to make sure that nothing bad happens if the irq somehow fires before setting the affinity. An opinion of someone that is more into kernel timekeeping than me would be nice. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 12/16] clk: samsung: pll: Add support for rate configuration of PLL46xx
+ con0 |= (rate-mdiv PLL46XX_MDIV_SHIFT) |
+ (rate-pdiv PLL46XX_PDIV_SHIFT) |
+ (rate-sdiv PLL46XX_SDIV_SHIFT) |
+ (rate-vsel PLL46XX_VSEL_SHIFT);
+
+ /* Set PLL AFC, MFR and MRR values. */
This comments seems to be miss match with below code.
+ con1 = __raw_readl(pll-con_reg + 0x4);
+ con1 = ~((PLL46XX_KDIV_MASK PLL46XX_KDIV_SHIFT) |
+ (PLL46XX_MFR_MASK PLL46XX_MFR_SHIFT) |
+ (PLL46XX_MRR_MASK PLL46XX_MRR_SHIFT));
+ con1 |= (rate-kdiv PLL46XX_KDIV_SHIFT) |
+ (rate-mfr PLL46XX_MFR_SHIFT) |
+ (rate-mrr PLL46XX_MRR_SHIFT);
+
snip
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -51,6 +51,28 @@ enum samsung_pll_type {
.afc= (_afc), \
}
+#define PLL_4600_RATE(_rate, _m, _p, _s, _k, _vsel)\
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ .vsel = (_vsel),\
+ }
+
+#define PLL_4650_RATE(_rate, _m, _p, _s, _k, _mfr, _mrr, _vsel)\
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ .mfr= (_mfr), \
+ .mrr= (_mrr), \
+ .vsel = (_vsel),\
+ }
+
/* NOTE: Rate table should be kept sorted in descending order. */
struct samsung_pll_rate_table {
@@ -60,6 +82,9 @@ struct samsung_pll_rate_table {
unsigned int sdiv;
unsigned int kdiv;
unsigned int afc;
+ unsigned int mfr;
+ unsigned int mrr;
+ unsigned int vsel;
};
This struct seems to be expanding too much.
Can we re-think on options for using bit map same as register
definition? It can reduce code in set_rate also little bit.
Regards,
Yadwinder
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Re: [PATCH 14/16] clk: samsung: exynos4: Register PLL rate tables for Exynos4210
On Tue, Aug 20, 2013 at 11:01 PM, Tomasz Figa t.f...@samsung.com wrote:
This patch adds rate tables for PLLs that can be reconfigured at runtime
for Exynos4210 SoCs. Provided tables contain PLL coefficients for
input clock of 24 MHz and so are registered only in this case. MPLL does
not need runtime reconfiguration and so table for it is not provided.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c | 45
+++
1 file changed, 45 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 34474ce..e18cfae 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -992,6 +992,40 @@ static struct of_device_id ext_clk_match[] __initdata = {
{},
};
+/* PLLs PMS values */
+static struct samsung_pll_rate_table exynos4210_apll_rates[] = {
+ PLL_45XX_RATE(12, 150, 3, 1, 28),
All these tables in this patch as well as next patch can be __initdata
Regards,
Yadwinder
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Re: [PATCH 12/16] clk: samsung: pll: Add support for rate configuration of PLL46xx
On Wednesday 21 of August 2013 18:02:16 Yadwinder Singh Brar wrote:
+ con0 |= (rate-mdiv PLL46XX_MDIV_SHIFT) |
+ (rate-pdiv PLL46XX_PDIV_SHIFT) |
+ (rate-sdiv PLL46XX_SDIV_SHIFT) |
+ (rate-vsel PLL46XX_VSEL_SHIFT);
+
+ /* Set PLL AFC, MFR and MRR values. */
This comments seems to be miss match with below code.
Hmm, looks like a copy/paste error. Thanks for spotting.
+ con1 = __raw_readl(pll-con_reg + 0x4);
+ con1 = ~((PLL46XX_KDIV_MASK PLL46XX_KDIV_SHIFT) |
+ (PLL46XX_MFR_MASK PLL46XX_MFR_SHIFT) |
+ (PLL46XX_MRR_MASK PLL46XX_MRR_SHIFT));
+ con1 |= (rate-kdiv PLL46XX_KDIV_SHIFT) |
+ (rate-mfr PLL46XX_MFR_SHIFT) |
+ (rate-mrr PLL46XX_MRR_SHIFT);
+
snip
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -51,6 +51,28 @@ enum samsung_pll_type {
.afc= (_afc), \
}
+#define PLL_4600_RATE(_rate, _m, _p, _s, _k, _vsel)\
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ .vsel = (_vsel),\
+ }
+
+#define PLL_4650_RATE(_rate, _m, _p, _s, _k, _mfr, _mrr, _vsel)
\ + { \ +
.rate = (_rate),\ +
.mdiv = (_m), \ +
.pdiv = (_p), \ +
.sdiv = (_s), \ +
.kdiv = (_k), \ + .mfr
= (_mfr), \ + .mrr=
(_mrr), \ + .vsel =
(_vsel),\ + }
+
/* NOTE: Rate table should be kept sorted in descending order. */
struct samsung_pll_rate_table {
@@ -60,6 +82,9 @@ struct samsung_pll_rate_table {
unsigned int sdiv;
unsigned int kdiv;
unsigned int afc;
+ unsigned int mfr;
+ unsigned int mrr;
+ unsigned int vsel;
};
This struct seems to be expanding too much.
I don't think it's a problem. How many bytes such tables can occupy in a
system?
Can we re-think on options for using bit map same as register
definition? It can reduce code in set_rate also little bit.
IMHO it is more clear what the code does when accessing a single
coefficient at once.
In addition you still would need to preserve bitfields that are not changed
by the driver and also unpack some of the coefficients anyway, like pdiv
that is used to calculate lock time.
Best regards,
Tomasz
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Re: [PATCH 14/16] clk: samsung: exynos4: Register PLL rate tables for Exynos4210
On Wednesday 21 of August 2013 18:04:07 Yadwinder Singh Brar wrote:
On Tue, Aug 20, 2013 at 11:01 PM, Tomasz Figa t.f...@samsung.com wrote:
This patch adds rate tables for PLLs that can be reconfigured at
runtime
for Exynos4210 SoCs. Provided tables contain PLL coefficients for
input clock of 24 MHz and so are registered only in this case. MPLL
does
not need runtime reconfiguration and so table for it is not provided.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c | 45
+++ 1 file changed, 45
insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c index 34474ce..e18cfae 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -992,6 +992,40 @@ static struct of_device_id ext_clk_match[]
__initdata = {
{},
};
+/* PLLs PMS values */
+static struct samsung_pll_rate_table exynos4210_apll_rates[] = {
+ PLL_45XX_RATE(12, 150, 3, 1, 28),
All these tables in this patch as well as next patch can be __initdata
Right, I forgot to mark them as such. Thanks for spotting.
Best regards,
Tomasz
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Re: [PATCH 10/16] clk: samsung: pll: Add support for rate configuration of PLL45xx
On Wednesday 21 of August 2013 17:48:44 Yadwinder Singh Brar wrote:
Hi Tomasz,
On Tue, Aug 20, 2013 at 11:01 PM, Tomasz Figa t.f...@samsung.com wrote:
This patch implements round_rate and set_rate callbacks of PLL45xx
driver to allow reconfiguration of PLL at runtime.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/clk/samsung/clk-pll.c | 109
+-
drivers/clk/samsung/clk-pll.h | 10
2 files changed, 118 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-pll.c
b/drivers/clk/samsung/clk-pll.c index b0398d2..cb971cb 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -10,9 +10,12 @@
*/
#include linux/errno.h
+#include linux/hrtimer.h
#include clk.h
#include clk-pll.h
+#define PLL_TIMEOUT_MS 10
+
struct samsung_clk_pll {
struct clk_hw hw;
void __iomem*lock_reg;
@@ -272,13 +275,20 @@ static const struct clk_ops
samsung_pll36xx_clk_min_ops = {
/*
* PLL45xx Clock Type
*/
+#define PLL4502_LOCK_FACTOR400
+#define PLL4508_LOCK_FACTOR240
#define PLL45XX_MDIV_MASK (0x3FF)
#define PLL45XX_PDIV_MASK (0x3F)
#define PLL45XX_SDIV_MASK (0x7)
+#define PLL45XX_AFC_MASK (0x1F)
#define PLL45XX_MDIV_SHIFT (16)
#define PLL45XX_PDIV_SHIFT (8)
#define PLL45XX_SDIV_SHIFT (0)
+#define PLL45XX_AFC_SHIFT (0)
+
+#define PLL45XX_ENABLE BIT(31)
+#define PLL45XX_LOCKED BIT(29)
static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
@@ -301,8 +311,100 @@ static unsigned long
samsung_pll45xx_recalc_rate(struct clk_hw *hw,
return (unsigned long)fvco;
}
+static bool samsung_pll45xx_mp_change(u32 pll_con0, u32 pll_con1,
+ const struct samsung_pll_rate_table
*rate) +{
+ u32 old_mdiv, old_pdiv, old_afc;
+
+ old_mdiv = (pll_con0 PLL45XX_MDIV_SHIFT)
PLL45XX_MDIV_MASK;
+ old_pdiv = (pll_con0 PLL45XX_PDIV_SHIFT)
PLL45XX_PDIV_MASK;
+ old_afc = (pll_con1 PLL45XX_AFC_SHIFT) PLL45XX_AFC_MASK;
old_afc doesn't required in this function.
+
+ return (old_mdiv != rate-mdiv || old_pdiv != rate-pdiv);
Actually it should be included in the comparison above. Thanks for
spotting.
+}
+
+static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long
drate, + unsigned long prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ const struct samsung_pll_rate_table *rate;
+ u32 con0, con1;
+ ktime_t start;
+
+ /* Get required rate settings from table */
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err(%s: Invalid rate : %lu for pll clk %s\n,
__func__, + drate, __clk_get_name(hw-clk));
+ return -EINVAL;
+ }
+
+ con0 = __raw_readl(pll-con_reg);
+ con1 = __raw_readl(pll-con_reg + 0x4);
+
+ if (!(samsung_pll45xx_mp_change(con0, con1, rate))) {
+ /* If only s change, change just s value only*/
+ con0 = ~(PLL45XX_SDIV_MASK PLL45XX_SDIV_SHIFT);
+ con0 |= rate-sdiv PLL45XX_SDIV_SHIFT;
+ __raw_writel(con0, pll-con_reg);
+
+ return 0;
+ }
+
+ /* Set PLL PMS values. */
+ con0 = ~((PLL45XX_MDIV_MASK PLL45XX_MDIV_SHIFT) |
+ (PLL45XX_PDIV_MASK PLL45XX_PDIV_SHIFT) |
+ (PLL45XX_SDIV_MASK PLL45XX_SDIV_SHIFT));
+ con0 |= (rate-mdiv PLL45XX_MDIV_SHIFT) |
+ (rate-pdiv PLL45XX_PDIV_SHIFT) |
+ (rate-sdiv PLL45XX_SDIV_SHIFT);
+
+ /* Set PLL AFC value. */
+ con1 = __raw_readl(pll-con_reg + 0x4);
+ con1 = ~(PLL45XX_AFC_MASK PLL45XX_AFC_SHIFT);
+ con1 |= (rate-afc PLL45XX_AFC_SHIFT);
+
Do we need to take care of AFC_ENB also, if we are using AFC ?
I'm not really sure. The original vendor code seems to not touch this bit
at all, assuming that it has been configured by the bootloader.
We should take care for the AFC coefficient, though, as AFC might have been
enabled at bootup.
I'd like to hear an opinion from someone from SLSI. Kukjin, Jingoo, do you
know anything about this?
Best regards,
Tomasz
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Re: [PATCH 12/16] clk: samsung: pll: Add support for rate configuration of PLL46xx
snip
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -51,6 +51,28 @@ enum samsung_pll_type {
.afc= (_afc), \
}
+#define PLL_4600_RATE(_rate, _m, _p, _s, _k, _vsel)\
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ .vsel = (_vsel),\
+ }
+
+#define PLL_4650_RATE(_rate, _m, _p, _s, _k, _mfr, _mrr, _vsel)
\ + { \ +
.rate = (_rate),\ +
.mdiv = (_m), \ +
.pdiv = (_p), \ +
.sdiv = (_s), \ +
.kdiv = (_k), \ + .mfr
= (_mfr), \ + .mrr=
(_mrr), \ + .vsel =
(_vsel),\ + }
+
/* NOTE: Rate table should be kept sorted in descending order. */
struct samsung_pll_rate_table {
@@ -60,6 +82,9 @@ struct samsung_pll_rate_table {
unsigned int sdiv;
unsigned int kdiv;
unsigned int afc;
+ unsigned int mfr;
+ unsigned int mrr;
+ unsigned int vsel;
};
This struct seems to be expanding too much.
I don't think it's a problem. How many bytes such tables can occupy in a
system?
no doubt comparing with memory size its negligible..
but comparing only struct size and coding lines it seems costlier :) .
Can we re-think on options for using bit map same as register
definition? It can reduce code in set_rate also little bit.
IMHO it is more clear what the code does when accessing a single
coefficient at once.
In addition you still would need to preserve bitfields that are not changed
by the driver
Sorry, I can't see any such problem, it will OR only the required bits.
and also unpack some of the coefficients anyway, like pdiv
that is used to calculate lock time.
Agree, but cases of unpacking will always be less than cases of
shifting and packing.
Anyways, its only MHO :).
Regards,
Yadwinder
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Re: [PATCH 09/16] clk: samsung: pll: Use new registration method for PLL45xx
};
+static struct __initdata samsung_pll_clock exynos4210_plls[nr_plls] = {
NIT: __initdata should be at last.
+ [apll] = PLL_A(pll_4508, fout_apll, fout_apll, fin_pll, APLL_LOCK,
+ APLL_CON0, fout_apll, NULL),
+ [mpll] = PLL_A(pll_4508, fout_mpll, fout_mpll, fin_pll,
+ E4210_MPLL_LOCK, E4210_MPLL_CON0, fout_mpll, NULL),
+};
+
static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
[apll] = PLL(pll_35xx, fout_apll, fout_apll, fin_pll,
APLL_LOCK, APLL_CON0, NULL),
@@ -1004,7 +1012,7 @@ static void __init exynos4_clk_init(struct device_node
*np,
enum exynos4_soc exynos4_soc,
void __iomem *reg_base, unsigned long xom)
{
- struct clk *apll, *mpll, *epll, *vpll;
+ struct clk *epll, *vpll;
reg_base = of_iomap(np, 0);
if (!reg_base)
@@ -1026,17 +1034,13 @@ static void __init exynos4_clk_init(struct
device_node *np,
exynos4_clk_register_finpll(xom);
if (exynos4_soc == EXYNOS4210) {
- apll = samsung_clk_register_pll45xx(fout_apll, fin_pll,
- reg_base + APLL_CON0, pll_4508);
- mpll = samsung_clk_register_pll45xx(fout_mpll, fin_pll,
- reg_base + E4210_MPLL_CON0, pll_4508);
+ samsung_clk_register_pll(exynos4210_plls,
+ ARRAY_SIZE(exynos4210_plls),
reg_base);
epll = samsung_clk_register_pll46xx(fout_epll, fin_pll,
reg_base + EPLL_CON0, pll_4600);
vpll = samsung_clk_register_pll46xx(fout_vpll,
mout_vpllsrc,
reg_base + VPLL_CON0, pll_4650c);
- samsung_clk_add_lookup(apll, fout_apll);
- samsung_clk_add_lookup(mpll, fout_mpll);
samsung_clk_add_lookup(epll, fout_epll);
samsung_clk_add_lookup(vpll, fout_vpll);
} else {
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 0775554..b0398d2 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -280,18 +280,10 @@ static const struct clk_ops samsung_pll36xx_clk_min_ops
= {
#define PLL45XX_PDIV_SHIFT (8)
#define PLL45XX_SDIV_SHIFT (0)
-struct samsung_clk_pll45xx {
- struct clk_hw hw;
- enum pll45xx_type type;
- const void __iomem *con_reg;
-};
-
-#define to_clk_pll45xx(_hw) container_of(_hw, struct samsung_clk_pll45xx, hw)
-
static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct samsung_clk_pll45xx *pll = to_clk_pll45xx(hw);
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 mdiv, pdiv, sdiv, pll_con;
u64 fvco = parent_rate;
@@ -313,43 +305,6 @@ static const struct clk_ops samsung_pll45xx_clk_ops = {
.recalc_rate = samsung_pll45xx_recalc_rate,
};
-struct clk * __init samsung_clk_register_pll45xx(const char *name,
- const char *pname, const void __iomem *con_reg,
- enum pll45xx_type type)
-{
- struct samsung_clk_pll45xx *pll;
- struct clk *clk;
- struct clk_init_data init;
-
- pll = kzalloc(sizeof(*pll), GFP_KERNEL);
- if (!pll) {
- pr_err(%s: could not allocate pll clk %s\n, __func__, name);
- return NULL;
- }
-
- init.name = name;
- init.ops = samsung_pll45xx_clk_ops;
- init.flags = CLK_GET_RATE_NOCACHE;
- init.parent_names = pname;
- init.num_parents = 1;
-
- pll-hw.init = init;
- pll-con_reg = con_reg;
- pll-type = type;
-
- clk = clk_register(NULL, pll-hw);
- if (IS_ERR(clk)) {
- pr_err(%s: failed to register pll clock %s\n, __func__,
- name);
- kfree(pll);
- }
-
- if (clk_register_clkdev(clk, name, NULL))
- pr_err(%s: failed to register lookup for %s, __func__,
name);
-
- return clk;
-}
-
/*
* PLL46xx Clock Type
*/
@@ -724,6 +679,11 @@ static void __init _samsung_clk_register_pll(struct
samsung_pll_clock *pll_clk,
else
init.ops = samsung_pll35xx_clk_ops;
break;
+ case pll_4500:
+ case pll_4502:
+ case pll_4508:
+ init.ops = samsung_pll45xx_clk_ops;
+ break;
/* clk_ops for 36xx and 2650 are similar */
case pll_36xx:
case pll_2650:
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index 2f70e88..f3faf24 100644
--- a/drivers/clk/samsung/clk-pll.h
+++
[PATCH V3 2/2] ARM: dts: exynos: change status property of dwmmc nodes
According to ePAPR, chapter 2.3.4, the status property has
defined that it should be set to disabled when the device
is not presently operational, but it might become operational
in the future.
So this patch disable dwmmc node by status = disabled in SOC
dts file and enable dwmmc node by status = okay in board specific
dts file.
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
---
arch/arm/boot/dts/exynos5250-arndale.dts | 10 ++
arch/arm/boot/dts/exynos5250-smdk5250.dts | 10 ++
arch/arm/boot/dts/exynos5250.dtsi |4
3 files changed, 8 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index 452d0b0..b741dd4 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -367,6 +367,7 @@
};
dwmmc_0: dwmmc0@1220 {
+ status = okay;
num-slots = 1;
supports-highspeed;
broken-cd;
@@ -385,11 +386,8 @@
};
};
- dwmmc_1: dwmmc1@1221 {
- status = disabled;
- };
-
dwmmc_2: dwmmc2@1222 {
+ status = okay;
num-slots = 1;
supports-highspeed;
fifo-depth = 0x80;
@@ -408,10 +406,6 @@
};
};
- dwmmc_3: dwmmc3@1223 {
- status = disabled;
- };
-
spi_0: spi@12d2 {
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 2538b32..bd19d55d 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -141,6 +141,7 @@
};
dwmmc0@1220 {
+ status = okay;
num-slots = 1;
supports-highspeed;
broken-cd;
@@ -158,11 +159,8 @@
};
};
- dwmmc1@1221 {
- status = disabled;
- };
-
dwmmc2@1222 {
+ status = okay;
num-slots = 1;
supports-highspeed;
fifo-depth = 0x80;
@@ -180,10 +178,6 @@
};
};
- dwmmc3@1223 {
- status = disabled;
- };
-
spi_0: spi@12d2 {
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 3c970fe..b1b6f61 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -394,6 +394,7 @@
reg = 0x1220 0x1000;
clocks = clock 280, clock 139;
clock-names = biu, ciu;
+ status = disabled;
};
dwmmc_1: dwmmc1@1221 {
@@ -404,6 +405,7 @@
reg = 0x1221 0x1000;
clocks = clock 281, clock 140;
clock-names = biu, ciu;
+ status = disabled;
};
dwmmc_2: dwmmc2@1222 {
@@ -414,6 +416,7 @@
reg = 0x1222 0x1000;
clocks = clock 282, clock 141;
clock-names = biu, ciu;
+ status = disabled;
};
dwmmc_3: dwmmc3@1223 {
@@ -424,6 +427,7 @@
#size-cells = 0;
clocks = clock 283, clock 142;
clock-names = biu, ciu;
+ status = disabled;
};
i2s0: i2s@0383 {
--
1.7.9.5
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[PATCH V3 1/2] ARM: dts: Move dwmmc nodes from exynos5.dtsi to exynos5250.dtsi
Exynos5 series SOC's 5250 and 5420 have different versions of
DWMMC controller.So there is a new compatible string to distinguish
between them.So these nodes should be moved out of Exynos5 series
common device tree source to SOC specific device tree source.
Changes since V2:
1.remove from exynos5.dtsi and add in exynos5250.dtsi
in single patch.
Changes since V1: none
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
---
arch/arm/boot/dts/exynos5.dtsi| 21 -
arch/arm/boot/dts/exynos5250.dtsi | 12
2 files changed, 12 insertions(+), 21 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 6afa57d..24140f0 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -50,27 +50,6 @@
interrupts = 1 9 0xf04;
};
- dwmmc_0: dwmmc0@1220 {
- compatible = samsung,exynos5250-dw-mshc;
- interrupts = 0 75 0;
- #address-cells = 1;
- #size-cells = 0;
- };
-
- dwmmc_1: dwmmc1@1221 {
- compatible = samsung,exynos5250-dw-mshc;
- interrupts = 0 76 0;
- #address-cells = 1;
- #size-cells = 0;
- };
-
- dwmmc_2: dwmmc2@1222 {
- compatible = samsung,exynos5250-dw-mshc;
- interrupts = 0 77 0;
- #address-cells = 1;
- #size-cells = 0;
- };
-
serial@12C0 {
compatible = samsung,exynos4210-uart;
reg = 0x12C0 0x100;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 1eec646..3c970fe 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -387,18 +387,30 @@
};
dwmmc_0: dwmmc0@1220 {
+ compatible = samsung,exynos5250-dw-mshc;
+ interrupts = 0 75 0;
+ #address-cells = 1;
+ #size-cells = 0;
reg = 0x1220 0x1000;
clocks = clock 280, clock 139;
clock-names = biu, ciu;
};
dwmmc_1: dwmmc1@1221 {
+ compatible = samsung,exynos5250-dw-mshc;
+ interrupts = 0 76 0;
+ #address-cells = 1;
+ #size-cells = 0;
reg = 0x1221 0x1000;
clocks = clock 281, clock 140;
clock-names = biu, ciu;
};
dwmmc_2: dwmmc2@1222 {
+ compatible = samsung,exynos5250-dw-mshc;
+ interrupts = 0 77 0;
+ #address-cells = 1;
+ #size-cells = 0;
reg = 0x1222 0x1000;
clocks = clock 282, clock 141;
clock-names = biu, ciu;
--
1.7.9.5
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[PATCH V3 0/2]exynos dwmmc device tree node
These patches were V3 versions of below patches. 1.[PATCH 1/2] ARM: dts: remove dwmmc nodes from exynos5 common dts file. http://www.spinics.net/lists/linux-samsung-soc/msg21602.html 2.[PATCH 2/2] ARM: dts: Add dwmmc nodes in SOC specific dts file http://www.spinics.net/lists/linux-samsung-soc/msg21603.html changes from V2: 1.remove from exynos5.dtsi and add in exynos5250.dtsi in single patch.Suggested by Tomasz Figa. 2.Separate patch for changing status property of dwmmc node in smdk5250 and arndale board dts file. Yuvaraj Kumar C D (2): ARM: dts: Move dwmmc nodes from exynos5.dtsi to exynos5250.dtsi ARM: dts: exynos: change status property of dwmmc nodes arch/arm/boot/dts/exynos5.dtsi| 21 - arch/arm/boot/dts/exynos5250-arndale.dts | 10 ++ arch/arm/boot/dts/exynos5250-smdk5250.dts | 10 ++ arch/arm/boot/dts/exynos5250.dtsi | 16 4 files changed, 20 insertions(+), 37 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2] i2c: move of helpers into the core
I2C of helpers used to live in of_i2c.c but experience (from SPI) shows that it is much cleaner to have this in the core. This also removes a circular dependency between the helpers and the core, and so we can finally register child nodes in the core instead of doing this manually in each driver. So, fix the drivers and documentation, too. Acked-by: Sylwester Nawrocki s.nawro...@amsung.com Acked-by: Rob Herring rob.herr...@calxeda.com Reviewed-by: Felipe Balbi ba...@ti.com Acked-by: Rafael J. Wysocki rafael.j.wyso...@intel.com Signed-off-by: Wolfram Sang w...@the-dreams.de --- V1 - V2: * Add #else branch to #if CONFIG_OF * EXPORT_SYMBOLs got attached to wrong functions * cosmetic change (of - OF) * properly based on 3.11-rc4 Documentation/acpi/enumeration.txt |1 - drivers/i2c/busses/i2c-at91.c |3 - drivers/i2c/busses/i2c-cpm.c|6 -- drivers/i2c/busses/i2c-davinci.c|2 - drivers/i2c/busses/i2c-designware-platdrv.c |2 - drivers/i2c/busses/i2c-gpio.c |3 - drivers/i2c/busses/i2c-i801.c |2 - drivers/i2c/busses/i2c-ibm_iic.c|4 - drivers/i2c/busses/i2c-imx.c|3 - drivers/i2c/busses/i2c-mpc.c|2 - drivers/i2c/busses/i2c-mv64xxx.c|3 - drivers/i2c/busses/i2c-mxs.c|3 - drivers/i2c/busses/i2c-nomadik.c|3 - drivers/i2c/busses/i2c-ocores.c |3 - drivers/i2c/busses/i2c-octeon.c |3 - drivers/i2c/busses/i2c-omap.c |3 - drivers/i2c/busses/i2c-pnx.c|3 - drivers/i2c/busses/i2c-powermac.c |9 +- drivers/i2c/busses/i2c-pxa.c|2 - drivers/i2c/busses/i2c-s3c2410.c|2 - drivers/i2c/busses/i2c-sh_mobile.c |2 - drivers/i2c/busses/i2c-sirf.c |3 - drivers/i2c/busses/i2c-stu300.c |2 - drivers/i2c/busses/i2c-tegra.c |3 - drivers/i2c/busses/i2c-versatile.c |2 - drivers/i2c/busses/i2c-wmt.c|3 - drivers/i2c/busses/i2c-xiic.c |3 - drivers/i2c/i2c-core.c | 109 +- drivers/i2c/i2c-mux.c |3 - drivers/i2c/muxes/i2c-arb-gpio-challenge.c |1 - drivers/i2c/muxes/i2c-mux-gpio.c|1 - drivers/i2c/muxes/i2c-mux-pinctrl.c |1 - drivers/media/platform/exynos4-is/fimc-is-i2c.c |3 - drivers/of/Kconfig |6 -- drivers/of/Makefile |1 - drivers/of/of_i2c.c | 114 --- include/linux/i2c.h | 20 include/linux/of_i2c.h | 46 - 38 files changed, 132 insertions(+), 253 deletions(-) delete mode 100644 drivers/of/of_i2c.c delete mode 100644 include/linux/of_i2c.h diff --git a/Documentation/acpi/enumeration.txt b/Documentation/acpi/enumeration.txt index d9be7a9..958266e 100644 --- a/Documentation/acpi/enumeration.txt +++ b/Documentation/acpi/enumeration.txt @@ -238,7 +238,6 @@ An I2C bus (controller) driver does: if (ret) /* handle error */ - of_i2c_register_devices(adapter); /* Enumerate the slave devices behind this bus via ACPI */ acpi_i2c_register_devices(adapter); diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c index 6bb839b..fd05930 100644 --- a/drivers/i2c/busses/i2c-at91.c +++ b/drivers/i2c/busses/i2c-at91.c @@ -28,7 +28,6 @@ #include linux/module.h #include linux/of.h #include linux/of_device.h -#include linux/of_i2c.h #include linux/platform_device.h #include linux/slab.h #include linux/platform_data/dma-atmel.h @@ -775,8 +774,6 @@ static int at91_twi_probe(struct platform_device *pdev) return rc; } - of_i2c_register_devices(dev-adapter); - dev_info(dev-dev, AT91 i2c bus driver.\n); return 0; } diff --git a/drivers/i2c/busses/i2c-cpm.c b/drivers/i2c/busses/i2c-cpm.c index 2e1f7eb..b2b8aa9 100644 --- a/drivers/i2c/busses/i2c-cpm.c +++ b/drivers/i2c/busses/i2c-cpm.c @@ -42,7 +42,6 @@ #include linux/dma-mapping.h #include linux/of_device.h #include linux/of_platform.h -#include linux/of_i2c.h #include sysdev/fsl_soc.h #include asm/cpm.h @@ -681,11 +680,6 @@ static int cpm_i2c_probe(struct platform_device *ofdev) dev_dbg(ofdev-dev, hw routines for %s registered.\n, cpm-adap.name); - /* -* register OF I2C devices -*/ - of_i2c_register_devices(cpm-adap); - return 0; out_shut: cpm_i2c_shutdown(cpm); diff --git a/drivers/i2c/busses/i2c-davinci.c
[PATCH 0/3] drm/exynos: fimd: get signal polarities from device tree
Hi, This patch series adds signal polarities parsing from display-timings devicetree node. To do it efficiently struct fb_videomode is replaced with struct videomode and some additional code cleaning is performed. The patches are for drm-exynos/exynos-drm-next branch. Regards Andrzej Hajda Andrzej Hajda (3): drm/exynos: fimd: replace struct fb_videomode with videomode drm/exynos: fimd: get signal polarities from device tree drm/exynos: fimd: move platform data parsing to separate function drivers/gpu/drm/exynos/exynos_drm_connector.c | 33 + drivers/gpu/drm/exynos/exynos_drm_fimd.c | 189 +- include/drm/exynos_drm.h | 3 +- 3 files changed, 103 insertions(+), 122 deletions(-) -- 1.8.1.2 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] drm/exynos: fimd: get signal polarities from device tree
The patch adds code to get signal polarization setting
from device tree display-timings node.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index a183ea7..6afcaf1 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -915,6 +915,15 @@ static int fimd_probe(struct platform_device *pdev)
DRM_ERROR(failed: of_get_videomode() : %d\n, ret);
return ret;
}
+
+ if (vm-flags DISPLAY_FLAGS_VSYNC_LOW)
+ pdata-vidcon1 |= VIDCON1_INV_VSYNC;
+ if (vm-flags DISPLAY_FLAGS_HSYNC_LOW)
+ pdata-vidcon1 |= VIDCON1_INV_HSYNC;
+ if (vm-flags DISPLAY_FLAGS_DE_LOW)
+ pdata-vidcon1 |= VIDCON1_INV_VDEN;
+ if (vm-flags DISPLAY_FLAGS_PIXDATA_NEGEDGE)
+ pdata-vidcon1 |= VIDCON1_INV_VCLK;
} else {
pdata = dev-platform_data;
if (!pdata) {
--
1.8.1.2
--
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[PATCH 3/3] drm/exynos: fimd: move platform data parsing to separate function
The patch moves platfrom_data and device tree parsing
to separate function.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 63
1 file changed, 31 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 6afcaf1..130dea5 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -122,7 +122,7 @@ struct fimd_context {
wait_queue_head_t wait_vsync_queue;
atomic_twait_vsync_event;
- struct exynos_drm_panel_info *panel;
+ struct exynos_drm_panel_info panel;
struct fimd_driver_data *driver_data;
};
@@ -164,7 +164,7 @@ static void *fimd_get_panel(struct device *dev)
{
struct fimd_context *ctx = get_fimd_context(dev);
- return ctx-panel;
+ return ctx-panel;
}
static int fimd_check_mode(struct device *dev, struct drm_display_mode *mode)
@@ -244,7 +244,7 @@ static void fimd_apply(struct device *subdrv_dev)
static void fimd_commit(struct device *dev)
{
struct fimd_context *ctx = get_fimd_context(dev);
- struct exynos_drm_panel_info *panel = ctx-panel;
+ struct exynos_drm_panel_info *panel = ctx-panel;
struct videomode *vm = panel-vm;
struct fimd_driver_data *driver_data;
u32 val;
@@ -755,7 +755,7 @@ static void fimd_subdrv_remove(struct drm_device *drm_dev,
struct device *dev)
static int fimd_configure_clocks(struct fimd_context *ctx, struct device *dev)
{
- struct videomode *vm = ctx-panel-vm;
+ struct videomode *vm = ctx-panel.vm;
unsigned long clk;
ctx-bus_clk = devm_clk_get(dev, fimd);
@@ -892,24 +892,13 @@ static int fimd_activate(struct fimd_context *ctx, bool
enable)
return 0;
}
-static int fimd_probe(struct platform_device *pdev)
+static int fimd_get_platform_data(struct fimd_context *ctx, struct device *dev)
{
- struct device *dev = pdev-dev;
- struct fimd_context *ctx;
- struct exynos_drm_subdrv *subdrv;
- struct exynos_drm_fimd_pdata *pdata;
- struct exynos_drm_panel_info *panel;
- struct resource *res;
- int win;
- int ret = -EINVAL;
-
if (dev-of_node) {
struct videomode *vm;
- pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
- if (!pdata)
- return -ENOMEM;
+ int ret;
- vm = pdata-panel.vm;
+ vm = ctx-panel.vm;
ret = of_get_videomode(dev-of_node, vm, OF_USE_NATIVE_MODE);
if (ret) {
DRM_ERROR(failed: of_get_videomode() : %d\n, ret);
@@ -917,31 +906,45 @@ static int fimd_probe(struct platform_device *pdev)
}
if (vm-flags DISPLAY_FLAGS_VSYNC_LOW)
- pdata-vidcon1 |= VIDCON1_INV_VSYNC;
+ ctx-vidcon1 |= VIDCON1_INV_VSYNC;
if (vm-flags DISPLAY_FLAGS_HSYNC_LOW)
- pdata-vidcon1 |= VIDCON1_INV_HSYNC;
+ ctx-vidcon1 |= VIDCON1_INV_HSYNC;
if (vm-flags DISPLAY_FLAGS_DE_LOW)
- pdata-vidcon1 |= VIDCON1_INV_VDEN;
+ ctx-vidcon1 |= VIDCON1_INV_VDEN;
if (vm-flags DISPLAY_FLAGS_PIXDATA_NEGEDGE)
- pdata-vidcon1 |= VIDCON1_INV_VCLK;
+ ctx-vidcon1 |= VIDCON1_INV_VCLK;
} else {
- pdata = dev-platform_data;
+ struct exynos_drm_fimd_pdata *pdata = dev-platform_data;
if (!pdata) {
DRM_ERROR(no platform data specified\n);
return -EINVAL;
}
+ ctx-vidcon0 = pdata-vidcon0;
+ ctx-vidcon1 = pdata-vidcon1;
+ ctx-default_win = pdata-default_win;
+ ctx-panel = pdata-panel;
}
- panel = pdata-panel;
- if (!panel) {
- dev_err(dev, panel is null.\n);
- return -EINVAL;
- }
+ return 0;
+}
+
+static int fimd_probe(struct platform_device *pdev)
+{
+ struct device *dev = pdev-dev;
+ struct fimd_context *ctx;
+ struct exynos_drm_subdrv *subdrv;
+ struct resource *res;
+ int win;
+ int ret = -EINVAL;
ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
if (!ctx)
return -ENOMEM;
+ ret = fimd_get_platform_data(ctx, dev);
+ if (ret)
+ return ret;
+
ret = fimd_configure_clocks(ctx, dev);
if (ret)
return ret;
@@ -968,10 +971,6 @@ static int fimd_probe(struct platform_device *pdev)
}
ctx-driver_data = drm_fimd_get_driver_data(pdev);
-
[PATCH 1/3] drm/exynos: fimd: replace struct fb_videomode with videomode
The patch replaces all occurrences of struct fb_videomode by
more accurate struct videomode. The change allows to remove
mode conversion function and simplifies clock divider calculation.
Clock configuration is moved to separate function.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_connector.c | 33 +--
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 131 +-
include/drm/exynos_drm.h | 3 +-
3 files changed, 70 insertions(+), 97 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_connector.c
b/drivers/gpu/drm/exynos/exynos_drm_connector.c
index de7c7b2..e082efb 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_connector.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_connector.c
@@ -29,35 +29,6 @@ struct exynos_drm_connector {
uint32_tdpms;
};
-/* convert exynos_video_timings to drm_display_mode */
-static inline void
-convert_to_display_mode(struct drm_display_mode *mode,
- struct exynos_drm_panel_info *panel)
-{
- struct fb_videomode *timing = panel-timing;
-
- mode-clock = timing-pixclock / 1000;
- mode-vrefresh = timing-refresh;
-
- mode-hdisplay = timing-xres;
- mode-hsync_start = mode-hdisplay + timing-right_margin;
- mode-hsync_end = mode-hsync_start + timing-hsync_len;
- mode-htotal = mode-hsync_end + timing-left_margin;
-
- mode-vdisplay = timing-yres;
- mode-vsync_start = mode-vdisplay + timing-lower_margin;
- mode-vsync_end = mode-vsync_start + timing-vsync_len;
- mode-vtotal = mode-vsync_end + timing-upper_margin;
- mode-width_mm = panel-width_mm;
- mode-height_mm = panel-height_mm;
-
- if (timing-vmode FB_VMODE_INTERLACED)
- mode-flags |= DRM_MODE_FLAG_INTERLACE;
-
- if (timing-vmode FB_VMODE_DOUBLE)
- mode-flags |= DRM_MODE_FLAG_DBLSCAN;
-}
-
static int exynos_drm_connector_get_modes(struct drm_connector *connector)
{
struct exynos_drm_connector *exynos_connector =
@@ -112,7 +83,9 @@ static int exynos_drm_connector_get_modes(struct
drm_connector *connector)
return 0;
}
- convert_to_display_mode(mode, panel);
+ drm_display_mode_from_videomode(panel-vm, mode);
+ mode-width_mm = panel-width_mm;
+ mode-height_mm = panel-height_mm;
connector-display_info.width_mm = mode-width_mm;
connector-display_info.height_mm = mode-height_mm;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index f8889d2..a183ea7 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -21,6 +21,7 @@
#include linux/pm_runtime.h
#include video/of_display_timing.h
+#include video/of_videomode.h
#include video/samsung_fimd.h
#include drm/exynos_drm.h
@@ -36,6 +37,8 @@
* CPU Interface.
*/
+#define FIMD_DEFAULT_FRAMERATE 60
+
/* position control register for hardware window 0, 2 ~ 4.*/
#define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
#define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
@@ -242,7 +245,7 @@ static void fimd_commit(struct device *dev)
{
struct fimd_context *ctx = get_fimd_context(dev);
struct exynos_drm_panel_info *panel = ctx-panel;
- struct fb_videomode *timing = panel-timing;
+ struct videomode *vm = panel-vm;
struct fimd_driver_data *driver_data;
u32 val;
@@ -254,22 +257,22 @@ static void fimd_commit(struct device *dev)
writel(ctx-vidcon1, ctx-regs + driver_data-timing_base + VIDCON1);
/* setup vertical timing values. */
- val = VIDTCON0_VBPD(timing-upper_margin - 1) |
- VIDTCON0_VFPD(timing-lower_margin - 1) |
- VIDTCON0_VSPW(timing-vsync_len - 1);
+ val = VIDTCON0_VBPD(vm-vback_porch - 1) |
+ VIDTCON0_VFPD(vm-vfront_porch - 1) |
+ VIDTCON0_VSPW(vm-vsync_len - 1);
writel(val, ctx-regs + driver_data-timing_base + VIDTCON0);
/* setup horizontal timing values. */
- val = VIDTCON1_HBPD(timing-left_margin - 1) |
- VIDTCON1_HFPD(timing-right_margin - 1) |
- VIDTCON1_HSPW(timing-hsync_len - 1);
+ val = VIDTCON1_HBPD(vm-hback_porch - 1) |
+ VIDTCON1_HFPD(vm-hfront_porch - 1) |
+ VIDTCON1_HSPW(vm-hsync_len - 1);
writel(val, ctx-regs + driver_data-timing_base + VIDTCON1);
/* setup horizontal and vertical display size. */
- val = VIDTCON2_LINEVAL(timing-yres - 1) |
- VIDTCON2_HOZVAL(timing-xres - 1) |
- VIDTCON2_LINEVAL_E(timing-yres - 1) |
- VIDTCON2_HOZVAL_E(timing-xres - 1);
+ val = VIDTCON2_LINEVAL(vm-vactive - 1) |
+
Re: [PATCH V2] i2c: move of helpers into the core
On 08/21/2013 03:47 PM, Wolfram Sang wrote: I2C of helpers used to live in of_i2c.c but experience (from SPI) shows that it is much cleaner to have this in the core. This also removes a circular dependency between the helpers and the core, and so we can finally register child nodes in the core instead of doing this manually in each driver. So, fix the drivers and documentation, too. Acked-by: Sylwester Nawrocki s.nawro...@amsung.com Acked-by: Rob Herring rob.herr...@calxeda.com Reviewed-by: Felipe Balbi ba...@ti.com Acked-by: Rafael J. Wysocki rafael.j.wyso...@intel.com Signed-off-by: Wolfram Sang w...@the-dreams.de With this patch there are still couple of of_i2c.h header file inclusions: $ git grep of_i2c.h arch/powerpc/platforms/44x/warp.c:#include linux/of_i2c.h drivers/gpu/drm/tilcdc/tilcdc_slave.c:#include linux/of_i2c.h drivers/gpu/drm/tilcdc/tilcdc_tfp410.c:#include linux/of_i2c.h drivers/gpu/host1x/drm/output.c:#include linux/of_i2c.h drivers/media/platform/exynos4-is/fimc-is.c:#include linux/of_i2c.h drivers/media/platform/exynos4-is/media-dev.c:#include linux/of_i2c.h drivers/staging/imx-drm/imx-tve.c:#include linux/of_i2c.h sound/soc/fsl/imx-sgtl5000.c:#include linux/of_i2c.h sound/soc/fsl/imx-wm8962.c:#include linux/of_i2c.h Please include also this chunk, without it I'm getting build errors. --8- diff --git a/drivers/media/platform/exynos4-is/fimc-is-i2c.c b/drivers/media/platform/exynos4-is/fimc-is-i2c.c index ca07b48..e38e9dc 100644 --- a/drivers/media/platform/exynos4-is/fimc-is-i2c.c +++ b/drivers/media/platform/exynos4-is/fimc-is-i2c.c @@ -11,6 +11,7 @@ */ #include linux/clk.h +#include linux/i2c.h #include linux/module.h #include linux/platform_device.h #include linux/pm_runtime.h diff --git a/drivers/media/platform/exynos4-is/fimc-is.c b/drivers/media/platform/exynos4-is/fimc-is.c index 6743ae3..63e4f1d 100644 --- a/drivers/media/platform/exynos4-is/fimc-is.c +++ b/drivers/media/platform/exynos4-is/fimc-is.c @@ -21,7 +21,6 @@ #include linux/interrupt.h #include linux/kernel.h #include linux/module.h -#include linux/of_i2c.h #include linux/of_irq.h #include linux/of_address.h #include linux/of_platform.h diff --git a/drivers/media/platform/exynos4-is/media-dev.c b/drivers/media/platform/exynos4-is/media-dev.c index c10dee2..00e5f91 100644 --- a/drivers/media/platform/exynos4-is/media-dev.c +++ b/drivers/media/platform/exynos4-is/media-dev.c @@ -22,7 +22,6 @@ #include linux/of.h #include linux/of_platform.h #include linux/of_device.h -#include linux/of_i2c.h #include linux/platform_device.h #include linux/pm_runtime.h #include linux/types.h --8- --- V1 - V2: * Add #else branch to #if CONFIG_OF * EXPORT_SYMBOLs got attached to wrong functions * cosmetic change (of - OF) * properly based on 3.11-rc4 Documentation/acpi/enumeration.txt |1 - drivers/i2c/busses/i2c-at91.c |3 - drivers/i2c/busses/i2c-cpm.c|6 -- drivers/i2c/busses/i2c-davinci.c|2 - drivers/i2c/busses/i2c-designware-platdrv.c |2 - drivers/i2c/busses/i2c-gpio.c |3 - drivers/i2c/busses/i2c-i801.c |2 - drivers/i2c/busses/i2c-ibm_iic.c|4 - drivers/i2c/busses/i2c-imx.c|3 - drivers/i2c/busses/i2c-mpc.c|2 - drivers/i2c/busses/i2c-mv64xxx.c|3 - drivers/i2c/busses/i2c-mxs.c|3 - drivers/i2c/busses/i2c-nomadik.c|3 - drivers/i2c/busses/i2c-ocores.c |3 - drivers/i2c/busses/i2c-octeon.c |3 - drivers/i2c/busses/i2c-omap.c |3 - drivers/i2c/busses/i2c-pnx.c|3 - drivers/i2c/busses/i2c-powermac.c |9 +- drivers/i2c/busses/i2c-pxa.c|2 - drivers/i2c/busses/i2c-s3c2410.c|2 - drivers/i2c/busses/i2c-sh_mobile.c |2 - drivers/i2c/busses/i2c-sirf.c |3 - drivers/i2c/busses/i2c-stu300.c |2 - drivers/i2c/busses/i2c-tegra.c |3 - drivers/i2c/busses/i2c-versatile.c |2 - drivers/i2c/busses/i2c-wmt.c|3 - drivers/i2c/busses/i2c-xiic.c |3 - drivers/i2c/i2c-core.c | 109 +- drivers/i2c/i2c-mux.c |3 - drivers/i2c/muxes/i2c-arb-gpio-challenge.c |1 - drivers/i2c/muxes/i2c-mux-gpio.c|1 - drivers/i2c/muxes/i2c-mux-pinctrl.c |1 - drivers/media/platform/exynos4-is/fimc-is-i2c.c |3 - drivers/of/Kconfig |6 -- drivers/of/Makefile |1 -
Re: [PATCH v5 0/4] mmc: dw_mmc: fixes for suspend/resume on exynos
Seungwon, On Wed, Aug 21, 2013 at 4:48 AM, Seungwon Jeon tgih@samsung.com wrote: Hi Doug, Do you have any update for this series? Please let me know. Thank you for the ping. The changes requested looked big enough that I knew I was going to have to devote some time to looking this all over again, which I haven't had time for. I'll make time for it today or tomorrow and repost. Sorry for the delay. -Doug -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V3] watchdog: s3c2410_wdt: remove the global variables
Hi All, Leela Krishna Amudala wrote: This patch removes the global variables in the driver file and group them into a structure. Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com (+ Wim Van Sebroeck) Looks good to me, Acked-by: Kukjin Kim kgene@samsung.com Thanks, Kukjin Can someone sent me the (unquoted) patch so that I can review and add it? Thanks in advance, Wim. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 7/7] ARM: dts: Add dts file for S3C6410-based SMDK6410 board
This patch adds basic device tree sources for SAMSUNG SMDK6410 board
based on SAMSUNG S3C6410 SoC.
Currently only UARTs, SD channel 0 and 100Mbps ethernet (SMSC911x) are
supported.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/s3c6410-smdk6410.dts | 103 +
2 files changed, 105 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/s3c6410-smdk6410.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 72f8af3..e55c644 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -194,7 +194,8 @@ dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
ccu8540.dtb \
ccu9540.dtb
dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
-dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb
+dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
+ s3c6410-smdk6410.dtb
dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
emev2-kzm9d-reference.dtb \
r8a7740-armadillo800eva.dtb \
diff --git a/arch/arm/boot/dts/s3c6410-smdk6410.dts
b/arch/arm/boot/dts/s3c6410-smdk6410.dts
new file mode 100644
index 000..ecf35ec
--- /dev/null
+++ b/arch/arm/boot/dts/s3c6410-smdk6410.dts
@@ -0,0 +1,103 @@
+/*
+ * Samsung S3C6410 based SMDK6410 board device tree source.
+ *
+ * Copyright (c) 2013 Tomasz Figa tomasz.f...@gmail.com
+ *
+ * Device tree source file for SAMSUNG SMDK6410 board which is based on
+ * Samsung's S3C6410 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+
+#include dt-bindings/gpio/gpio.h
+#include dt-bindings/interrupt-controller/irq.h
+
+#include s3c6410.dtsi
+
+/ {
+ model = SAMSUNG SMDK6410 board based on S3C6410;
+ compatible = samsung,mini6410, samsung,s3c6410;
+
+ memory {
+ reg = 0x5000 0x800;
+ };
+
+ chosen {
+ bootargs = console=ttySAC0,115200n8 earlyprintk rootwait
root=/dev/mmcblk0p1;
+ };
+
+ clocks {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ fin_pll: oscillator@0 {
+ compatible = fixed-clock;
+ reg = 0;
+ clock-frequency = 1200;
+ clock-output-names = fin_pll;
+ #clock-cells = 0;
+ };
+
+ xusbxti: oscillator@1 {
+ compatible = fixed-clock;
+ reg = 1;
+ clock-output-names = xusbxti;
+ clock-frequency = 4800;
+ #clock-cells = 0;
+ };
+ };
+
+ srom-cs1@1800 {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ reg = 0x1800 0x800;
+ ranges;
+
+ ethernet@1800 {
+ compatible = smsc,lan9115;
+ reg = 0x1800 0x1;
+ interrupt-parent = gpn;
+ interrupts = 10 IRQ_TYPE_LEVEL_LOW;
+ phy-mode = mii;
+ reg-io-width = 4;
+ smsc,force-internal-phy;
+ };
+ };
+};
+
+sdhci0 {
+ pinctrl-names = default;
+ pinctrl-0 = sd0_clk, sd0_cmd, sd0_cd, sd0_bus4;
+ bus-width = 4;
+ status = okay;
+};
+
+uart0 {
+ pinctrl-names = default;
+ pinctrl-0 = uart0_data, uart0_fctl;
+ status = okay;
+};
+
+uart1 {
+ pinctrl-names = default;
+ pinctrl-0 = uart1_data;
+ status = okay;
+};
+
+uart2 {
+ pinctrl-names = default;
+ pinctrl-0 = uart2_data;
+ status = okay;
+};
+
+uart3 {
+ pinctrl-names = default;
+ pinctrl-0 = uart3_data;
+ status = okay;
+};
--
1.8.3.2
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[PATCH v7 4/7] ARM: s3c64xx: Add board file for boot using Device Tree
This patch adds board file that will be used to boot S3C64xx-based boards
using Device Tree.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
arch/arm/mach-s3c64xx/Kconfig | 16 +++
arch/arm/mach-s3c64xx/Makefile | 1 +
arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c | 85 +
3 files changed, 102 insertions(+)
create mode 100644 arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 041da51..bd14e3a 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -306,3 +306,19 @@ config MACH_WLF_CRAGG_6410
select SAMSUNG_GPIO_EXTRA128
help
Machine support for the Wolfson Cragganmore S3C6410 variant.
+
+config MACH_S3C64XX_DT
+ bool Samsung S3C6400/S3C6410 machine using Device Tree
+ select CLKSRC_OF
+ select CPU_S3C6400
+ select CPU_S3C6410
+ select PINCTRL
+ select PINCTRL_S3C64XX
+ select USE_OF
+ help
+ Machine support for Samsung S3C6400/S3C6410 machines with Device Tree
+ enabled.
+ Select this if a fdt blob is available for your S3C64XX SoC based
+ board.
+ Note: This is under development and not all peripherals can be
+ supported with this machine file.
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 645a8fe..6faedcf 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -57,3 +57,4 @@ obj-$(CONFIG_MACH_SMARTQ7)+= mach-smartq7.o
obj-$(CONFIG_MACH_SMDK6400)+= mach-smdk6400.o
obj-$(CONFIG_MACH_SMDK6410)+= mach-smdk6410.o
obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o
mach-crag6410-module.o
+obj-$(CONFIG_MACH_S3C64XX_DT) += mach-s3c64xx-dt.o
diff --git a/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c
b/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c
new file mode 100644
index 000..7eb9a10
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c
@@ -0,0 +1,85 @@
+/*
+ * Samsung's S3C64XX flattened device tree enabled machine
+ *
+ * Copyright (c) 2013 Tomasz Figa tomasz.f...@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include linux/clk-provider.h
+#include linux/irqchip.h
+#include linux/of_platform.h
+
+#include asm/mach/arch.h
+#include asm/mach/map.h
+#include asm/system_misc.h
+
+#include plat/cpu.h
+#include plat/watchdog-reset.h
+
+#include mach/map.h
+
+#include common.h
+
+/*
+ * IO mapping for shared system controller IP.
+ *
+ * FIXME: Make remaining drivers use dynamic mapping.
+ */
+static struct map_desc s3c64xx_dt_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S3C_VA_SYS,
+ .pfn= __phys_to_pfn(S3C64XX_PA_SYSCON),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
+static void __init s3c64xx_dt_map_io(void)
+{
+ debug_ll_io_init();
+ iotable_init(s3c64xx_dt_iodesc, ARRAY_SIZE(s3c64xx_dt_iodesc));
+
+ s3c64xx_init_cpu();
+
+ if (!soc_is_s3c64xx())
+ panic(SoC is not S3C64xx!);
+}
+
+static void __init s3c64xx_dt_init_irq(void)
+{
+ of_clk_init(NULL);
+ samsung_wdt_reset_of_init();
+ irqchip_init();
+};
+
+static void __init s3c64xx_dt_init_machine(void)
+{
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static void s3c64xx_dt_restart(enum reboot_mode mode, const char *cmd)
+{
+ if (mode != REBOOT_SOFT)
+ samsung_wdt_reset();
+
+ /* if all else fails, or mode was for soft, jump to 0 */
+ soft_restart(0);
+}
+
+static char const *s3c64xx_dt_compat[] __initdata = {
+ samsung,s3c6400,
+ samsung,s3c6410,
+ NULL
+};
+
+DT_MACHINE_START(S3C6400_DT, Samsung S3C64xx (Flattened Device Tree))
+ /* Maintainer: Tomasz Figa tomasz.f...@gmail.com */
+ .dt_compat = s3c64xx_dt_compat,
+ .map_io = s3c64xx_dt_map_io,
+ .init_irq = s3c64xx_dt_init_irq,
+ .init_machine = s3c64xx_dt_init_machine,
+ .restart= s3c64xx_dt_restart,
+MACHINE_END
--
1.8.3.2
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[PATCH v7 6/7] ARM: dts: Add dts file for S3C6410-based Mini6410 board
This patch adds basic device tree sources for FriendlyARM Mini6410 board
based on Samsung S3C6410 SoC.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/s3c6410-mini6410.dts | 228 +
2 files changed, 229 insertions(+)
create mode 100644 arch/arm/boot/dts/s3c6410-mini6410.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ada589c..72f8af3 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -194,6 +194,7 @@ dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
ccu8540.dtb \
ccu9540.dtb
dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
+dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb
dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
emev2-kzm9d-reference.dtb \
r8a7740-armadillo800eva.dtb \
diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts
b/arch/arm/boot/dts/s3c6410-mini6410.dts
new file mode 100644
index 000..57e00f9
--- /dev/null
+++ b/arch/arm/boot/dts/s3c6410-mini6410.dts
@@ -0,0 +1,228 @@
+/*
+ * Samsung's S3C6410 based Mini6410 board device tree source
+ *
+ * Copyright (c) 2013 Tomasz Figa tomasz.f...@gmail.com
+ *
+ * Device tree source file for FriendlyARM Mini6410 board which is based on
+ * Samsung's S3C6410 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+
+#include dt-bindings/gpio/gpio.h
+#include dt-bindings/interrupt-controller/irq.h
+
+#include s3c6410.dtsi
+
+/ {
+ model = FriendlyARM Mini6410 board based on S3C6410;
+ compatible = friendlyarm,mini6410, samsung,s3c6410;
+
+ memory {
+ reg = 0x5000 0x1000;
+ };
+
+ chosen {
+ bootargs = console=ttySAC0,115200n8 earlyprintk rootwait
root=/dev/mmcblk0p1;
+ };
+
+ clocks {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ fin_pll: oscillator@0 {
+ compatible = fixed-clock;
+ reg = 0;
+ clock-frequency = 1200;
+ clock-output-names = fin_pll;
+ #clock-cells = 0;
+ };
+
+ xusbxti: oscillator@1 {
+ compatible = fixed-clock;
+ reg = 1;
+ clock-output-names = xusbxti;
+ clock-frequency = 4800;
+ #clock-cells = 0;
+ };
+ };
+
+ srom-cs1@1800 {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ reg = 0x1800 0x800;
+ ranges;
+
+ ethernet@1800 {
+ compatible = davicom,dm9000;
+ reg = 0x1800 0x2 0x1804 0x2;
+ interrupt-parent = gpn;
+ interrupts = 7 IRQ_TYPE_LEVEL_HIGH;
+ davicom,no-eeprom;
+ };
+ };
+
+ gpio-keys {
+ compatible = gpio-keys;
+ pinctrl-names = default;
+ pinctrl-0 = gpio_keys;
+ autorepeat;
+
+ button-k1 {
+ label = K1;
+ gpios = gpn 0 GPIO_ACTIVE_LOW;
+ linux,code = 2;
+ debounce-interval = 20;
+ };
+
+ button-k2 {
+ label = K2;
+ gpios = gpn 1 GPIO_ACTIVE_LOW;
+ linux,code = 3;
+ debounce-interval = 20;
+ };
+
+ button-k3 {
+ label = K3;
+ gpios = gpn 2 GPIO_ACTIVE_LOW;
+ linux,code = 4;
+ debounce-interval = 20;
+ };
+
+ button-k4 {
+ label = K4;
+ gpios = gpn 3 GPIO_ACTIVE_LOW;
+ linux,code = 5;
+ debounce-interval = 20;
+ };
+
+ button-k5 {
+ label = K5;
+ gpios = gpn 4 GPIO_ACTIVE_LOW;
+ linux,code = 6;
+ debounce-interval = 20;
+ };
+
+ button-k6 {
+ label = K6;
+ gpios = gpn 5 GPIO_ACTIVE_LOW;
+ linux,code = 7;
+ debounce-interval = 20;
+ };
+
+ button-k7 {
+ label = K7;
+ gpios = gpl 11 GPIO_ACTIVE_LOW;
+ linux,code = 8;
+ debounce-interval = 20;
+
[PATCH v7 3/7] gpio: samsung: Skip initialization if device tree is present
Since this driver does not handle GPIO on device tree enabled platforms
any more, it should be bypassed whenever device tree is available, to
not conflict with the new pinctrl-samsung driver.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
drivers/gpio/gpio-samsung.c | 34 +++---
1 file changed, 7 insertions(+), 27 deletions(-)
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index a1392f4..cc93b1b 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -2949,34 +2949,14 @@ static __init int samsung_gpiolib_init(void)
int i, nr_chips;
int group = 0;
-#if defined(CONFIG_PINCTRL_EXYNOS) || defined(CONFIG_PINCTRL_EXYNOS5440)
/*
- * This gpio driver includes support for device tree support and there
- * are platforms using it. In order to maintain compatibility with those
- * platforms, and to allow non-dt Exynos4210 platforms to use this
- * gpiolib support, a check is added to find out if there is a active
- * pin-controller driver support available. If it is available, this
- * gpiolib support is ignored and the gpiolib support available in
- * pin-controller driver is used. This is a temporary check and will go
- * away when all of the Exynos4210 platforms have switched to using
- * device tree and the pin-ctrl driver.
- */
- struct device_node *pctrl_np;
- static const struct of_device_id exynos_pinctrl_ids[] = {
- { .compatible = samsung,s3c2412-pinctrl, },
- { .compatible = samsung,s3c2416-pinctrl, },
- { .compatible = samsung,s3c2440-pinctrl, },
- { .compatible = samsung,s3c2450-pinctrl, },
- { .compatible = samsung,exynos4210-pinctrl, },
- { .compatible = samsung,exynos4x12-pinctrl, },
- { .compatible = samsung,exynos5250-pinctrl, },
- { .compatible = samsung,exynos5440-pinctrl, },
- { }
- };
- for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
- if (pctrl_np of_device_is_available(pctrl_np))
- return -ENODEV;
-#endif
+* Currently there are two drivers that can provide GPIO support for
+* Samsung SoCs. For device tree enabled platforms, the new
+* pinctrl-samsung driver is used, providing both GPIO and pin control
+* interfaces. For legacy (non-DT) platforms this driver is used.
+*/
+ if (of_have_populated_dt())
+ return -ENODEV;
samsung_gpiolib_set_cfg(samsung_gpio_cfgs,
ARRAY_SIZE(samsung_gpio_cfgs));
--
1.8.3.2
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[PATCH v7 5/7] ARM: dts: Add basic dts include files for Samsung S3C64xx SoCs
This patch adds basic device tree definitions for Samsung S3C64xx SoCs.
Since all the SoCs in the series are very similar, the files are created
hierarchically - one file for the whole series and then separate files
for particular SoCs including the common one.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
arch/arm/boot/dts/s3c6400.dtsi | 41 ++
arch/arm/boot/dts/s3c6410.dtsi | 57 +++
arch/arm/boot/dts/s3c64xx-pinctrl.dtsi | 687 +
arch/arm/boot/dts/s3c64xx.dtsi | 199 ++
4 files changed, 984 insertions(+)
create mode 100644 arch/arm/boot/dts/s3c6400.dtsi
create mode 100644 arch/arm/boot/dts/s3c6410.dtsi
create mode 100644 arch/arm/boot/dts/s3c64xx-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/s3c64xx.dtsi
diff --git a/arch/arm/boot/dts/s3c6400.dtsi b/arch/arm/boot/dts/s3c6400.dtsi
new file mode 100644
index 000..692f827
--- /dev/null
+++ b/arch/arm/boot/dts/s3c6400.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Samsung's S3C6400 SoC device tree source
+ *
+ * Copyright (c) 2013 Tomasz Figa tomasz.f...@gmail.com
+ *
+ * Samsung's S3C6400 SoC device nodes are listed in this file. S3C6400
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * S3C6400 SoC. As device tree coverage for S3C6400 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include s3c64xx.dtsi
+
+/ {
+ compatible = samsung,s3c6400;
+};
+
+vic0 {
+ interrupt-mask = 0xfe1f;
+ wakeup-mask = 0x0024;
+};
+
+vic1 {
+ interrupt-mask = 0x;
+ wakeup-mask = 0x5302;
+};
+
+soc {
+ clocks: clock-controller@7e00f000 {
+ compatible = samsung,s3c6400-clock;
+ reg = 0x7e00f000 0x1000;
+ #clock-cells = 1;
+ };
+};
diff --git a/arch/arm/boot/dts/s3c6410.dtsi b/arch/arm/boot/dts/s3c6410.dtsi
new file mode 100644
index 000..79c7083
--- /dev/null
+++ b/arch/arm/boot/dts/s3c6410.dtsi
@@ -0,0 +1,57 @@
+/*
+ * Samsung's S3C6410 SoC device tree source
+ *
+ * Copyright (c) 2013 Tomasz Figa tomasz.f...@gmail.com
+ *
+ * Samsung's S3C6410 SoC device nodes are listed in this file. S3C6410
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * S3C6410 SoC. As device tree coverage for S3C6410 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include s3c64xx.dtsi
+
+/ {
+ compatible = samsung,s3c6410;
+
+ aliases {
+ i2c1 = i2c1;
+ };
+};
+
+vic0 {
+ interrupt-mask = 0xff7f;
+ wakeup-mask = 0x0024;
+};
+
+vic1 {
+ interrupt-mask = 0x;
+ wakeup-mask = 0x5302;
+};
+
+soc {
+ clocks: clock-controller@7e00f000 {
+ compatible = samsung,s3c6410-clock;
+ reg = 0x7e00f000 0x1000;
+ #clock-cells = 1;
+ };
+
+ i2c1: i2c@7f00f000 {
+ compatible = samsung,s3c2440-i2c;
+ reg = 0x7f00f000 0x1000;
+ interrupt-parent = vic0;
+ interrupts = 5;
+ clock-names = i2c;
+ clocks = clocks PCLK_IIC1;
+ status = disabled;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+};
diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi
b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi
new file mode 100644
index 000..b1197d8
--- /dev/null
+++ b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi
@@ -0,0 +1,687 @@
+/*
+ * Samsung's S3C64xx SoC series common device tree source
+ * - pin control-related definitions
+ *
+ * Copyright (c) 2013 Tomasz Figa tomasz.f...@gmail.com
+ *
+ * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are
+ * listed as device tree nodes in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define PIN_PULL_NONE 0
+#define PIN_PULL_DOWN 1
+#define PIN_PULL_UP2
+
+pinctrl0 {
+ /*
+* Pin banks
+*/
+
+ gpa: gpa {
+ gpio-controller;
+ #gpio-cells = 2;
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpb: gpb {
+ gpio-controller;
+ #gpio-cells = 2;
+ interrupt-controller;
+
[PATCH v7 2/7] ARM: s3c64xx: Bypass legacy initialization when booting with DT
This patch allows bypassing most of legacy initialization when booting
an S3C64xx-based board using device tree, by adding conditional checks
for DT presence to initcalls which are no longer necessary when booting
with DT..
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
arch/arm/mach-s3c64xx/common.c | 12
arch/arm/mach-s3c64xx/dma.c | 9 +
arch/arm/mach-s3c64xx/irq-pm.c | 9 +
arch/arm/mach-s3c64xx/s3c6400.c | 9 +
arch/arm/mach-s3c64xx/s3c6410.c | 9 +
arch/arm/plat-samsung/init.c| 12 +++-
6 files changed, 59 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index 7d3cb58..7a3ce4c 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -14,6 +14,10 @@
* published by the Free Software Foundation.
*/
+/*
+ * NOTE: Code in this file is not used when booting with Device Tree support.
+ */
+
#include linux/kernel.h
#include linux/init.h
#include linux/module.h
@@ -203,6 +207,10 @@ void __init s3c64xx_init_io(struct map_desc *mach_desc,
int size)
static __init int s3c64xx_dev_init(void)
{
+ /* Not applicable when using DT. */
+ if (of_have_populated_dt())
+ return 0;
+
subsys_system_register(s3c64xx_subsys, NULL);
return device_register(s3c64xx_dev);
}
@@ -404,6 +412,10 @@ static int __init s3c64xx_init_irq_eint(void)
{
int irq;
+ /* On DT-enabled systems EINTs are handled by pinctrl-s3c64xx driver. */
+ if (of_have_populated_dt())
+ return -ENODEV;
+
for (irq = IRQ_EINT(0); irq = IRQ_EINT(27); irq++) {
irq_set_chip_and_handler(irq, s3c_irq_eint, handle_level_irq);
irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index c511dfa..7e22c21 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -12,6 +12,10 @@
* published by the Free Software Foundation.
*/
+/*
+ * NOTE: Code in this file is not used when booting with Device Tree support.
+ */
+
#include linux/kernel.h
#include linux/module.h
#include linux/interrupt.h
@@ -24,6 +28,7 @@
#include linux/err.h
#include linux/io.h
#include linux/amba/pl080.h
+#include linux/of.h
#include mach/dma.h
#include mach/map.h
@@ -726,6 +731,10 @@ static int __init s3c64xx_dma_init(void)
{
int ret;
+ /* This driver is not supported when booting with device tree. */
+ if (of_have_populated_dt())
+ return -ENODEV;
+
printk(KERN_INFO %s: Registering DMA channels\n, __func__);
dma_pool = dma_pool_create(DMA-LLI, NULL, sizeof(struct pl080s_lli),
16, 0);
diff --git a/arch/arm/mach-s3c64xx/irq-pm.c b/arch/arm/mach-s3c64xx/irq-pm.c
index c3da1b6..1649c0d 100644
--- a/arch/arm/mach-s3c64xx/irq-pm.c
+++ b/arch/arm/mach-s3c64xx/irq-pm.c
@@ -12,12 +12,17 @@
* published by the Free Software Foundation.
*/
+/*
+ * NOTE: Code in this file is not used when booting with Device Tree support.
+ */
+
#include linux/kernel.h
#include linux/syscore_ops.h
#include linux/interrupt.h
#include linux/serial_core.h
#include linux/irq.h
#include linux/io.h
+#include linux/of.h
#include mach/map.h
@@ -101,6 +106,10 @@ static struct syscore_ops s3c64xx_irq_syscore_ops = {
static __init int s3c64xx_syscore_init(void)
{
+ /* Appropriate drivers (pinctrl, uart) handle this when using DT. */
+ if (of_have_populated_dt())
+ return 0;
+
register_syscore_ops(s3c64xx_irq_syscore_ops);
return 0;
diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c
index 331fe8e..3db0c98 100644
--- a/arch/arm/mach-s3c64xx/s3c6400.c
+++ b/arch/arm/mach-s3c64xx/s3c6400.c
@@ -9,6 +9,10 @@
* published by the Free Software Foundation.
*/
+/*
+ * NOTE: Code in this file is not used when booting with Device Tree support.
+ */
+
#include linux/kernel.h
#include linux/types.h
#include linux/interrupt.h
@@ -20,6 +24,7 @@
#include linux/device.h
#include linux/serial_core.h
#include linux/platform_device.h
+#include linux/of.h
#include asm/mach/arch.h
#include asm/mach/map.h
@@ -76,6 +81,10 @@ static struct device s3c6400_dev = {
static int __init s3c6400_core_init(void)
{
+ /* Not applicable when using DT. */
+ if (of_have_populated_dt())
+ return 0;
+
return subsys_system_register(s3c6400_subsys, NULL);
}
diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c
index 7e6fa12..72b2278 100644
--- a/arch/arm/mach-s3c64xx/s3c6410.c
+++ b/arch/arm/mach-s3c64xx/s3c6410.c
@@ -10,6 +10,10 @@
* published by the Free Software Foundation.
*/
+/*
+ * NOTE: Code in this file is not used when booting with Device Tree support.
+ */
+
#include linux/kernel.h
#include linux/types.h
#include linux/interrupt.h
@@ -21,6 +25,7 @@
[PATCH v7 1/7] ARM: common: vic: Parse interrupt and resume masks from device tree
This patch extends vic_of_init to parse valid interrupt sources
and resume sources masks from device tree.
If mask values are not specified in device tree, all sources
are assumed to be valid, as before this patch.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
Documentation/devicetree/bindings/arm/vic.txt | 6 ++
drivers/irqchip/irq-vic.c | 7 ++-
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/vic.txt
b/Documentation/devicetree/bindings/arm/vic.txt
index 266716b..bb7137c 100644
--- a/Documentation/devicetree/bindings/arm/vic.txt
+++ b/Documentation/devicetree/bindings/arm/vic.txt
@@ -18,6 +18,9 @@ Required properties:
Optional properties:
- interrupts : Interrupt source for parent controllers if the VIC is nested.
+- interrupt-mask : Bit mask of valid interrupt sources (defaults to all valid)
+- wakeup-mask : Bit mask of interrupt sources that can wake up the system
+ (defaults to all allowed)
Example:
@@ -26,4 +29,7 @@ Example:
interrupt-controller;
#interrupt-cells = 1;
reg = 0x6 0x1000;
+
+ interrupt-mask = 0xff7f;
+ wakeup-mask = 0xff7f;
};
diff --git a/drivers/irqchip/irq-vic.c b/drivers/irqchip/irq-vic.c
index 2bbb004..d56750eb 100644
--- a/drivers/irqchip/irq-vic.c
+++ b/drivers/irqchip/irq-vic.c
@@ -469,6 +469,8 @@ void __init vic_init(void __iomem *base, unsigned int
irq_start,
int __init vic_of_init(struct device_node *node, struct device_node *parent)
{
void __iomem *regs;
+ u32 interrupt_mask = ~0;
+ u32 wakeup_mask = ~0;
if (WARN(parent, non-root VICs are not supported))
return -EINVAL;
@@ -477,10 +479,13 @@ int __init vic_of_init(struct device_node *node, struct
device_node *parent)
if (WARN_ON(!regs))
return -EIO;
+ of_property_read_u32(node, interrupt-mask, interrupt_mask);
+ of_property_read_u32(node, wakeup-mask, wakeup_mask);
+
/*
* Passing 0 as first IRQ makes the simple domain allocate descriptors
*/
- __vic_init(regs, 0, ~0, ~0, node);
+ __vic_init(regs, 0, interrupt_mask, wakeup_mask, node);
return 0;
}
--
1.8.3.2
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[PATCH v7 0/7] Initial Device Tree support for S3C64xx
This series adds Device Tree support for Samsung S3C64xx SoC series. It fixes several problems preventing from booting an S3C64xx-based system using Device Tree, adds all the infrastructure for Device Tree-based board support, including mach-s3c64xx-dt and dts include files for S3C64xx SoCs, and basic device tree source for FriendlyARM Mini6410 and SAMSUNG SMDK6410 boards. Current support is somewhat limite, but should be fine as a start and will be extended in future, hopefully with help of S3C64xx board maintainers. Depends on: - [PATCH v2 0/8] Common Clock Framework support for Samsung S3C64xx http://thread.gmane.org/gmane.linux.usb.general/90493 On Samsung S3C6410-based Mini6410 and SMDK6410 boards: Tested-by: Tomasz Figa tomasz.f...@gmail.com Changes since v6: - Rebased onto current for-next branch of Kgene's tree, - Dropped the idea of .init_platform() machine callback, - Added support for i2c controllers, - Replaced separate apb and ahb nodes with a single common soc node, - Updated cpus node according to CPU bindings, - Updated fixed rate clock nodes to use generic bindings, - Added support for PWM buzzer and I2C EEPROM on Mini6410 board, - Simplified the condition of skipping legacy GPIO initialization. Changes since v5: - Rebased onto current for-next branch of Kgene's tree, - Added support for new Common Clock Framework based clock driver, - Introduced hierarchical structure of device nodes (representing physical AHB and APB buses), - Bypassed most of legacy initialization when booting with DT, - Used preprocessor macros in dts files to improve readabilty, - Added support for SMDK6410 board. Changes since v4: - Rebased onto current for-next branch of Kgene's tree - Added support for pinctrl (driver merged through pinctrl tree) - Added labels to all nodes that can be overridden from board dts - Modified board dts to use the label syntax to reference device nodes Changes since v3: - Rebased onto current for-next branch of Kgene's tree - Updated timer node for next version of samsung-time patches - Replaced local s3c64xx_dt_init_irq with irqchip_init Changes since v2: - Updated timer node for next version of samsung-time patches Changes since v1: - Dropped two VIC-related patches that are no longer necessary - Added Device Tree-based instantation of system timers - Corrected VIC interrupt specifiers - Adjusted CPU compatible values and dropped @id Tomasz Figa (7): ARM: common: vic: Parse interrupt and resume masks from device tree ARM: s3c64xx: Bypass legacy initialization when booting with DT gpio: samsung: Skip initialization if device tree is present ARM: s3c64xx: Add board file for boot using Device Tree ARM: dts: Add basic dts include files for Samsung S3C64xx SoCs ARM: dts: Add dts file for S3C6410-based Mini6410 board ARM: dts: Add dts file for S3C6410-based SMDK6410 board Documentation/devicetree/bindings/arm/vic.txt | 6 + arch/arm/boot/dts/Makefile| 2 + arch/arm/boot/dts/s3c6400.dtsi| 41 ++ arch/arm/boot/dts/s3c6410-mini6410.dts| 228 + arch/arm/boot/dts/s3c6410-smdk6410.dts| 103 arch/arm/boot/dts/s3c6410.dtsi| 57 +++ arch/arm/boot/dts/s3c64xx-pinctrl.dtsi| 687 ++ arch/arm/boot/dts/s3c64xx.dtsi| 199 arch/arm/mach-s3c64xx/Kconfig | 16 + arch/arm/mach-s3c64xx/Makefile| 1 + arch/arm/mach-s3c64xx/common.c| 12 + arch/arm/mach-s3c64xx/dma.c | 9 + arch/arm/mach-s3c64xx/irq-pm.c| 9 + arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c | 85 arch/arm/mach-s3c64xx/s3c6400.c | 9 + arch/arm/mach-s3c64xx/s3c6410.c | 9 + arch/arm/plat-samsung/init.c | 12 +- drivers/gpio/gpio-samsung.c | 34 +- drivers/irqchip/irq-vic.c | 7 +- 19 files changed, 1497 insertions(+), 29 deletions(-) create mode 100644 arch/arm/boot/dts/s3c6400.dtsi create mode 100644 arch/arm/boot/dts/s3c6410-mini6410.dts create mode 100644 arch/arm/boot/dts/s3c6410-smdk6410.dts create mode 100644 arch/arm/boot/dts/s3c6410.dtsi create mode 100644 arch/arm/boot/dts/s3c64xx-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/s3c64xx.dtsi create mode 100644 arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c -- 1.8.3.2 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V3] watchdog: s3c2410_wdt: remove the global variables
On Wed, Aug 21, 2013 at 10:01:05PM +0200, Wim Van Sebroeck wrote: Hi All, Leela Krishna Amudala wrote: This patch removes the global variables in the driver file and group them into a structure. Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com (+ Wim Van Sebroeck) Looks good to me, Acked-by: Kukjin Kim kgene@samsung.com Thanks, Kukjin Can someone sent me the (unquoted) patch so that I can review and add it? Try this: wget http://download.gmane.org/gmane.linux.kernel.samsung-soc/21022/21023; Guenter -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/4] dmaengine: add driver for Samsung s3c24xx SoCs
On Mon, Aug 19, 2013 at 6:48 AM, Vinod Koul vinod.k...@intel.com wrote: On Wed, Aug 14, 2013 at 02:00:25PM +0200, Heiko Stübner wrote: Conceptually the s3c24xx-dma feels like a distant relative of the pl08x with numerous virtual channels being mapped to a lot less physical ones. The driver therefore borrows a lot from the amba-pl08x driver in this regard. Functionality-wise the driver gains a memcpy ability in addition to the slave_sg one. If that is the case why cant we have this driver supported from pl08x driver? If the delta is only mapping then can that be seprated or both mapping hanlded? Maybe you and Linus have already though about that? I took a look at the register list and couldn't find a way to save code by trying to shoehorn it into the PL08x, the registers and bit layouts are totally different. IIRC this driver does not have LLIs either so it's quite different and would look strange. Yours, Linus Walleij -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] pinctrl: samsung: Parse pin groups before calling pinctrl_register()
On Tue, Aug 20, 2013 at 6:16 PM, Tomasz Figa t.f...@samsung.com wrote: Calling pinctrl_register() means that the driver is fully initialized and might accept pinmux/pinconf requests, so pin groups must be parsed before. This patch fixes this problem by moving device tree parsing before call to pinctrl_register(). In addition, this fixes support for hogs on pin controllers handled by pinctrl-samsung driver. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com Patch applied. Yours, Linus Walleij -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 1/7] ARM: common: vic: Parse interrupt and resume masks from device tree
On Wed, Aug 21, 2013 at 11:21 PM, Tomasz Figa tomasz.f...@gmail.com wrote: +++ b/Documentation/devicetree/bindings/arm/vic.txt @@ -18,6 +18,9 @@ Required properties: Optional properties: - interrupts : Interrupt source for parent controllers if the VIC is nested. +- interrupt-mask : Bit mask of valid interrupt sources (defaults to all valid) +- wakeup-mask : Bit mask of interrupt sources that can wake up the system + (defaults to all allowed) The interrupt-mask is called valid-mask on the FPGA IRQ controller See Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt Example: reg = 0x1040 0x100; clear-mask = 0x; valid-mask = 0x0007; Please use the same name. (wakeup-mask is fine). Yours, Linus Walleij -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 3/7] gpio: samsung: Skip initialization if device tree is present
On Wed, Aug 21, 2013 at 11:21 PM, Tomasz Figa tomasz.f...@gmail.com wrote: Since this driver does not handle GPIO on device tree enabled platforms any more, it should be bypassed whenever device tree is available, to not conflict with the new pinctrl-samsung driver. Signed-off-by: Tomasz Figa tomasz.f...@gmail.com This seems like something I should apply to the GPIO tree right now, shall I? Yours, Linus Walleij -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] PCI: exynos: add support for MSI
On Monday, August 12, 2013 6:13 PM, Sachin Kamat wrote:
On 12 August 2013 14:26, Jingoo Han jg1@samsung.com wrote:
This patch adds support for Message Signaled Interrupt in the
Exynops PCIe diver using Synopsys designware PCIe core IP.
s/Exynops PCIe diver/Exynos PCIe driver
OK, I will fix this typo.
Signed-off-by: Siva Reddy Kallam siva.kal...@samsung.com
Signed-off-by: Srikanth T Shivanand ts.srika...@samsung.com
Signed-off-by: Jingoo Han jg1@samsung.com
Cc: Pratyush Anand pratyush.an...@st.com
Cc: Mohit KUMAR mohit.ku...@st.com
---
arch/arm/boot/dts/exynos5440.dtsi |2 +
arch/arm/mach-exynos/Kconfig |1 +
drivers/pci/host/pci-exynos.c | 60 ++
drivers/pci/host/pcie-designware.c | 213
drivers/pci/host/pcie-designware.h |8 ++
5 files changed, 284 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5440.dtsi
b/arch/arm/boot/dts/exynos5440.dtsi
index 586134e..3746835 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -249,6 +249,7 @@
interrupt-map-mask = 0 0 0 0;
interrupt-map = 0x0 0 gic 53;
num-lanes = 4;
+ msi-base = 200;
Please update the bindings documentation too.
OK, I will updated the bindings documentation.
[.]
+#ifdef CONFIG_PCI_MSI
+static void exynos_pcie_clear_irq_level(struct pcie_port *pp)
+{
+ u32 val;
+ struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ void __iomem *elbi_base = exynos_pcie-elbi_base;
+
+ val = readl(elbi_base + PCIE_IRQ_LEVEL);
+ writel(val, elbi_base + PCIE_IRQ_LEVEL);
Sorry, I did not get this. Writing the value read from the same
register without any operation.
It was intended to clear the bits by writing 1 of each bit.
But I will remove this function.
My coworker, Srikanth T Shivanand found that this function is
unnecessary. This is because PCIE_IRQ_LEVEL register is read-only
register. Also, PCIE_IRQ_LEVEL register is already cleared before
this function is called.
Thank you for your comment.
Best regards,
Jingoo Han
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